 
cpldfit:  version E.37                              Xilinx Inc.
                                  Fitter Report
Design Name: main43                              Date:  6- 6-2002,  1:28AM
Device Used: XCR3064XL-6-PC44
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
39 /64  ( 60%) 191 /192  ( 99%) 32 /64  ( 50%) 32 /32  (100%) 92 /160 ( 57%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    4           4    |  I/O              :    28        0
Output        :   12          12    |  GCK/IO           :     4        0
Bidirectional :   15          15    |  
GCK           :    1           1    |  
                 ----        ----
        Total      32          32 

MACROCELL RESOURCES:

Total Macrocells Available                    64
Registered Macrocells                         32
Non-registered Macrocell driving I/O           1

GLOBAL RESOURCES:

Signal 'rd' mapped onto global clock net GCK1.
Universal Control Terms (Used/Available)                  : 2/2

BLOCK RESOURCES:

Total Function Block Local Control Terms (Used/Available) : 1/32
Total Foldback NANDs (Used/Available)                     : 0/32

End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total Signals Loc     Slew Pin  Pin       Pin          
Name                Pt    Used            Rate #    Type      Use          
N212                2       3     FB4_6             (b)       (b)
N213                3       4     FB4_8             (b)       (b)
N214                3       5     FB4_13            (b)       (b)
N215                3       6     FB4_14            (b)       (b)
N216                3       7     FB4_16            (b)       (b)
N217                3       8     FB4_1        13   TMS/I/O   (b)
N_PZ_277            1       2     FB3_1        32   TCK/I/O   (b)
N_PZ_281            1       3     FB1_9        38   TDO/I/O   (b)
N_PZ_297            2       4     FB2_9        7    TDI/I/O   (b)
N_PZ_298            2       3     FB4_7             (b)       (b)
N_PZ_302            2       2     FB4_3             (b)       (b)
N_PZ_320            3       6     FB4_15            (b)       (b)
ad<0>               12      10    FB4_2   FAST 14   I/O       I/O
ad<10>              11      14    FB1_11  FAST 36   I/O       O
ad<11>              10      13    FB1_8   FAST 39   I/O       O
ad<12>              8       10    FB1_1   FAST 41   I/O       O
ad<13>              10      12    FB3_9   FAST 28   I/O       O
ad<14>              10      11    FB3_10  FAST 27   I/O       O
ad<15>              9       13    FB3_4   FAST 29   I/O       I/O
ad<1>               10      14    FB2_10  FAST 8    I/O       I/O
ad<2>               12      14    FB2_3   FAST 6    I/O       I/O
ad<3>               9       14    FB2_2   FAST 5    I/O       I/O
ad<4>               8       13    FB2_11  FAST 9    I/O       I/O
ad<5>               11      13    FB1_10  FAST 37   I/O       I/O
ad<6>               13      14    FB2_1   FAST 4    I/O       O
ad<7>               11      13    FB3_2   FAST 31   I/O       O
ad<8>               10      10    FB3_11  FAST 26   I/O       O
ad<9>               11      12    FB1_2   FAST 40   I/O       O
d<0>                4       7     FB3_12  FAST 25   I/O       I/O
d<1>                4       7     FB4_4   FAST 16   I/O       I/O
d<2>                4       7     FB4_5   FAST 17   I/O       I/O
d<3>                4       7     FB4_9   FAST 18   I/O       I/O
d<4>                4       7     FB4_10  FAST 19   I/O       I/O
d<5>                4       7     FB4_11  FAST 20   I/O       I/O
d<6>                4       7     FB4_12  FAST 21   I/O       I/O
d<7>                4       8     FB2_14  FAST 11   I/O       I/O
mmc_clk             1       2     FB1_14  FAST 34   I/O       O
mmc_cs              2       4     FB1_15  FAST 33   I/O       O
mmc_out             3       7     FB2_15  FAST 12   I/O       O

** INPUTS **
Signal                            Loc          Pin  Pin       Pin      I/O 
Name                                           #    Type      Use     Style
cs                                FB3_13       24   I/O       I                  
mmc_in                                         1    GCK       I                  
ramcs                                          44   GCK       I                  
rd                                             2    GCK       GCK/I              
wr                                             43   GCK       I                  

End of Resources Used by Successfully Mapped Logic

Legend: PU  - Pull Up
*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1           8          18          18           48         6/1        7   
FB2           8          20          20           48         2/5        7   
FB3           7          21          21           48         4/2        7   
FB4          16          33          33           47         0/7        7   
            ----                                -----       -----     ----- 
             39                                  191        12/15      28   
*********************************** FB1 ***********************************
Number of signals used by logic mapping into function block:  18
Number of function block inputs used/remaining:               18/22
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  2/6
Number of PLA product terms used/remaining:                   48/0
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
ad<12>                              8    FB1_1      41   I/O     O
ad<9>                              11    FB1_2      40   I/O     O
(unused)                            0    FB1_3           (b)      
(unused)                            0    FB1_4           (b)      
(unused)                            0    FB1_5           (b)      
(unused)                            0    FB1_6           (b)      
(unused)                            0    FB1_7           (b)      
ad<11>                             10    FB1_8      39   I/O     O
N_PZ_281                            1    FB1_9      38TDO/I/O   (b)
ad<5>                              11    FB1_10     37   I/O   I/O
ad<10>                             11    FB1_11     36   I/O     O
(unused)                            0    FB1_12          (b)      
(unused)                            0    FB1_13          (b)      
mmc_clk                             1    FB1_14     34   I/O     O
mmc_cs                              2    FB1_15     33   I/O     O
(unused)                            0    FB1_16          (b)      

Signals Used by Logic in Function Block
  1: N212               7: N_PZ_277          13: cs 
  2: N213               8: N_PZ_297          14: "d<0>".PIN 
  3: N214               9: N_PZ_298          15: "d<7>".PIN 
  4: N215              10: N_PZ_302          16: ramcs 
  5: N216              11: N_PZ_320          17: rd 
  6: N217              12: "ad<15>".PIN      18: wr 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
ad<12>            XXXXXX....X.X.X.X....................... 10      10
ad<9>             XXXXXX..XXX.X.X.X....................... 12      12
ad<11>            XXXXXX.XXXX.X.X.X....................... 13      13
N_PZ_281          ...........X...X.X...................... 3       3
ad<5>             XXXXXX.XXXX.X.X.X....................... 13      13
ad<10>            XXXXXXXXXXX.X.X.X....................... 14      14
mmc_clk           ............X.X......................... 2       2
mmc_cs            ...........X.X.X.X...................... 4       4
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           (b)      - Buried macrocell
*********************************** FB2 ***********************************
Number of signals used by logic mapping into function block:  20
Number of function block inputs used/remaining:               20/20
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  3/5
Number of PLA product terms used/remaining:                   48/0
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
ad<6>                              13    FB2_1       4   I/O     O
ad<3>                               9    FB2_2       5   I/O   I/O
ad<2>                              12    FB2_3       6   I/O   I/O
(unused)                            0    FB2_4           (b)      
(unused)                            0    FB2_5           (b)      
(unused)                            0    FB2_6           (b)      
(unused)                            0    FB2_7           (b)      
(unused)                            0    FB2_8           (b)      
N_PZ_297                            2    FB2_9       7TDI/I/O   (b)
ad<1>                              10    FB2_10      8   I/O   I/O
ad<4>                               8    FB2_11      9   I/O   I/O
(unused)                            0    FB2_12          (b)      
(unused)                            0    FB2_13          (b)      
d<7>                                4    FB2_14     11   I/O   I/O
mmc_out                             3    FB2_15     12   I/O     O
(unused)                            0    FB2_16          (b)      

Signals Used by Logic in Function Block
  1: N212               8: N_PZ_281          15: "d<6>" 
  2: N213               9: N_PZ_297          16: "d<7>".PIN 
  3: N214              10: N_PZ_298          17: mmc_clk 
  4: N215              11: N_PZ_302          18: ramcs 
  5: N216              12: N_PZ_320          19: rd 
  6: N217              13: "ad<15>".PIN      20: wr 
  7: N_PZ_277          14: cs               

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
ad<6>             XXXXXXX.XXXX.X.X..X..................... 14      14
ad<3>             XXXXXXX.XXXX.X.X..X..................... 14      14
ad<2>             XXXXXXX.XXXX.X.X..X..................... 14      14
N_PZ_297          XXXX.................................... 4       4
ad<1>             XXXXXXX.XXXX.X.X..X..................... 14      14
ad<4>             XXX.XXX.XXXX.X.X..X..................... 13      13
d<7>              .......X....X.XXXXXX.................... 8       8
mmc_out           .......X....X.XXXX.X.................... 7       7
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           (b)      - Buried macrocell
*********************************** FB3 ***********************************
Number of signals used by logic mapping into function block:  21
Number of function block inputs used/remaining:               21/19
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  2/6
Number of PLA product terms used/remaining:                   48/0
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
N_PZ_277                            1    FB3_1      32TCK/I/O   (b)
ad<7>                              11    FB3_2      31   I/O     O
(unused)                            0    FB3_3           (b)      
ad<15>                              9    FB3_4      29   I/O   I/O
(unused)                            0    FB3_5           (b)      
(unused)                            0    FB3_6           (b)      
(unused)                            0    FB3_7           (b)      
(unused)                            0    FB3_8           (b)      
ad<13>                             10    FB3_9      28   I/O     O
ad<14>                             10    FB3_10     27   I/O     O
ad<8>                              10    FB3_11     26   I/O     O
d<0>                                4    FB3_12     25   I/O   I/O
(unused)                            0    FB3_13     24   I/O     I
(unused)                            0    FB3_14          (b)      
(unused)                            0    FB3_15          (b)      
(unused)                            0    FB3_16          (b)      

Signals Used by Logic in Function Block
  1: N212               8: N_PZ_281          15: "d<0>".PIN 
  2: N213               9: N_PZ_297          16: "d<7>".PIN 
  3: N214              10: N_PZ_298          17: mmc_clk 
  4: N215              11: N_PZ_302          18: mmc_in 
  5: N216              12: N_PZ_320          19: ramcs 
  6: N217              13: "ad<15>".PIN      20: rd 
  7: N_PZ_277          14: cs                21: wr 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
N_PZ_277          ....XX.................................. 2       2
ad<7>             XXXXXXX.X.XX.X.X...X.................... 13      13
ad<15>            XXXXXXX.X.XX.X.X...X.................... 13      13
ad<13>            XXXXX...XXXX.X.X...X.................... 12      12
ad<14>            XXXXX....XXX.X.X...X.................... 11      11
ad<8>             XXXXXX...X...X.X...X.................... 10      10
d<0>              .......X....X.X.XXX.X................... 7       7
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           (b)      - Buried macrocell
*********************************** FB4 ***********************************
Number of signals used by logic mapping into function block:  33
Number of function block inputs used/remaining:               33/7
Number of foldback NANDs used/remaining:                      0/8
Number of function block local control terms used/remaining:  2/6
Number of PLA product terms used/remaining:                   47/1
Signal                            Total   Loc     Pin    Pin   Pin        
Name                              Pt               #     Type  Use        
N217                                3    FB4_1      13TMS/I/O   (b)
ad<0>                              12    FB4_2      14   I/O   I/O
N_PZ_302                            2    FB4_3           (b)   (b)
d<1>                                4    FB4_4      16   I/O   I/O
d<2>                                4    FB4_5      17   I/O   I/O
N212                                2    FB4_6           (b)   (b)
N_PZ_298                            2    FB4_7           (b)   (b)
N213                                3    FB4_8           (b)   (b)
d<3>                                4    FB4_9      18   I/O   I/O
d<4>                                4    FB4_10     19   I/O   I/O
d<5>                                4    FB4_11     20   I/O   I/O
d<6>                                4    FB4_12     21   I/O   I/O
N214                                3    FB4_13          (b)   (b)
N215                                3    FB4_14          (b)   (b)
N_PZ_320                            3    FB4_15          (b)   (b)
N216                                3    FB4_16          (b)   (b)

Signals Used by Logic in Function Block
  1: N212              12: "ad<2>".PIN       23: "d<3>".PIN 
  2: N213              13: "ad<3>".PIN       24: "d<4>" 
  3: N214              14: "ad<4>".PIN       25: "d<4>".PIN 
  4: N215              15: "ad<5>".PIN       26: "d<5>" 
  5: N216              16: cs                27: "d<5>".PIN 
  6: N217              17: "d<0>"            28: "d<6>".PIN 
  7: N_PZ_277          18: "d<1>"            29: "d<7>".PIN 
  8: N_PZ_281          19: "d<1>".PIN        30: mmc_clk 
  9: "ad<0>".PIN       20: "d<2>"            31: ramcs 
 10: "ad<15>".PIN      21: "d<2>".PIN        32: rd 
 11: "ad<1>".PIN       22: "d<3>"            33: wr 

Signal                     1         2         3         4 Signals FB
Name             0----+----0----+----0----+----0----+----0 Used    Inputs
N217              XXXXXX........XX........................ 8       8
ad<0>             XXXXXXX........X............X..X........ 10      10
N_PZ_302          X..X.................................... 2       2
d<1>              .......X.X......X.X..........XX.X....... 7       7
d<2>              .......X.X.......X..X........XX.X....... 7       7
N212              X.......X......X........................ 3       3
N_PZ_298          X..X.X.................................. 3       3
N213              XX........X....X........................ 4       4
d<3>              .......X.X.........X..X......XX.X....... 7       7
d<4>              .......X.X...........X..X....XX.X....... 7       7
d<5>              .......X.X.............X..X..XX.X....... 7       7
d<6>              .......X.X...............X.X.XX.X....... 7       7
N214              XXX........X...X........................ 5       5
N215              XXXX........X..X........................ 6       6
N_PZ_320          XXXXXX.................................. 6       6
N216              XXXXX........X.X........................ 7       7
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           (b)      - Buried macrocell
;;-----------------------------------------------------------------;;
; Implemented Equations.

/"ad<0>" := N216 * N217
	+ /N212 * /N213 * N216
	+ /N212 * N214 * N_PZ_277
	+ /N213 * N216 * N215
	+ N212 * N213 * N215 * N217
	+ N213 * /N214 * /N215 * N217
	+ N212 * /N213 * N214 * N215 * /N217
	+ /N212 * N213 * /N216 * N215 * /N217
	+ /N212 * /N216 * /N214 * /N215 * /N217
	+ /N213 * /N216 * /N214 * /N215 * /N217
	+ N212 * N213 * /N216 * N214 * /N215 * /N217
   /"ad<0>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<0>".CLKF  =  rd	;GCK
    "ad<0>".PRLD  =  Gnd

/N212.T := N212 * cs * "ad<0>".PIN
	+ /N212 * cs * /"ad<0>".PIN
    N212.CLKF  =  rd	;GCK
    N212.PRLD  =  Gnd

/N213.T := /N212 * /cs
	+ cs * N213 * "ad<1>".PIN
	+ cs * /N213 * /"ad<1>".PIN
    N213.CLKF  =  rd	;GCK
    N213.PRLD  =  Gnd

 N216.T := cs * N216 * /"ad<4>".PIN
	+ cs * /N216 * "ad<4>".PIN
	+ N212 * /cs * N213 * N214 * N215
    N216.CLKF  =  rd	;GCK
    N216.PRLD  =  Gnd

 N214.T := N212 * /cs * N213
	+ cs * N214 * /"ad<2>".PIN
	+ cs * /N214 * "ad<2>".PIN
    N214.CLKF  =  rd	;GCK
    N214.PRLD  =  Gnd

 N215.T := cs * N215 * /"ad<3>".PIN
	+ cs * /N215 * "ad<3>".PIN
	+ N212 * /cs * N213 * N214
    N215.CLKF  =  rd	;GCK
    N215.PRLD  =  Gnd

 N217.T := cs * N217 * /"ad<5>".PIN
	+ cs * /N217 * "ad<5>".PIN
	+ N212 * /cs * N213 * N216 * N214 * N215
    N217.CLKF  =  rd	;GCK
    N217.PRLD  =  Gnd

/N_PZ_277 = /N216 * /N217

/"ad<10>" := N216 * N_PZ_320
	+ /N214 * N_PZ_297
	+ /N214 * N_PZ_320
	+ /N212 * N213 * N_PZ_277
	+ /N212 * /N214 * N_PZ_298
	+ /N213 * N215 * N217
	+ N216 * /N214 * /N215
	+ N212 * /N213 * N216 * /N_PZ_302
	+ /N212 * /N213 * /N216 * /N217
	+ N212 * N213 * /N216 * N214 * /N_PZ_302
   /"ad<10>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<10>".CLKF  =  rd	;GCK
    "ad<10>".PRLD  =  Gnd

 N_PZ_298 = N217
	Xor /N212 * N215

 N_PZ_297 = /N213 * /N214 * N215
	+ /N212 * N213 * N214 * N215

 N_PZ_302 = N212 * N215
	+ /N212 * /N215

 N_PZ_320 = N216 * N217
	+ N213 * N214 * N217
	+ N212 * N213 * N215 * N217

/"ad<11>" := N216 * N_PZ_320
	+ N217 * /N_PZ_298
	+ /N213 * N215 * /N_PZ_297
	+ N212 * /N213 * N216 * N214
	+ N213 * /N216 * N214 * N_PZ_302
	+ N216 * /N214 * N215 * N_PZ_302
	+ /N216 * /N214 * /N215 * /N217
	+ N212 * N213 * /N216 * /N214 * /N_PZ_302
	+ /N213 * /N216 * /N214 * /N217 * /N_PZ_298
   /"ad<11>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<11>".CLKF  =  rd	;GCK
    "ad<11>".PRLD  =  Gnd

/"ad<12>" := N_PZ_320
	+ /N212 * N213 * /N215 * /N217
	+ /N212 * /N213 * N216 * /N214
	+ N213 * /N216 * /N215 * /N217
	+ N212 * N213 * N216 * N214 * N215
	+ N212 * /N216 * /N214 * /N215 * /N217
	+ /N212 * /N213 * /N214 * /N215 * N217
   /"ad<12>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<12>".CLKF  =  rd	;GCK
    "ad<12>".PRLD  =  Gnd

/"ad<13>" := N_PZ_320
	+ /N212 * /N216 * N_PZ_298 * /N_PZ_297
	+ N213 * /N216 * /N215 * N_PZ_302
	+ /N213 * N216 * N215 * /N_PZ_297
	+ /N213 * /N216 * N215 * /N_PZ_302
	+ /N213 * N214 * /N_PZ_298 * /N_PZ_302
	+ N216 * N214 * /N215 * /N_PZ_302
	+ /N216 * N214 * /N215 * N_PZ_302
	+ N212 * N213 * /N214 * /N215 * /N_PZ_298
   /"ad<13>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<13>".CLKF  =  rd	;GCK
    "ad<13>".PRLD  =  Gnd

/"ad<14>" := N216 * N_PZ_320
	+ N213 * N216 * /N_PZ_302
	+ /N213 * N214 * N_PZ_298
	+ N216 * N214 * /N_PZ_302
	+ /N212 * /N213 * /N216 * /N214
	+ N213 * N216 * N214 * N215
	+ N213 * N214 * /N_PZ_298 * /N_PZ_302
	+ N213 * /N215 * N_PZ_298 * /N_PZ_320
	+ /N216 * /N214 * N215 * N_PZ_302 * /N_PZ_320
   /"ad<14>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<14>".CLKF  =  rd	;GCK
    "ad<14>".PRLD  =  Gnd

/"ad<15>" := N216 * N_PZ_320
	+ /N217 * N_PZ_297
	+ /N213 * N216 * N214
	+ N212 * N214 * N_PZ_277 * /N_PZ_302
	+ /N212 * /N216 * /N214 * /N217
	+ N213 * /N214 * /N215 * N_PZ_302
	+ /N213 * /N215 * N_PZ_277 * /N_PZ_302
	+ N212 * /N216 * N214 * /N217 * N_PZ_302
   /"ad<15>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<15>".CLKF  =  rd	;GCK
    "ad<15>".PRLD  =  Gnd

/"ad<1>" := N216 * N_PZ_320
	+ /N212 * /N213 * N217
	+ N213 * N216 * N_PZ_302
	+ /N216 * /N217 * N_PZ_297
	+ N212 * /N214 * N_PZ_277 * /N_PZ_302
	+ N213 * /N214 * /N215 * /N_PZ_298
	+ /N213 * N214 * /N_PZ_298 * /N_PZ_302
	+ /N216 * /N215 * /N217 * N_PZ_302
	+ N215 * N_PZ_277 * /N_PZ_298 * /N_PZ_297
   /"ad<1>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<1>".CLKF  =  rd	;GCK
    "ad<1>".PRLD  =  Gnd

/"ad<2>" := N216 * N_PZ_320
	+ N_PZ_277 * N_PZ_297
	+ /N212 * /N213 * N216
	+ /N212 * N214 * /N_PZ_298
	+ /N213 * N217 * /N_PZ_302
	+ N213 * N216 * N214 * N215
	+ N213 * N216 * /N214 * /N_PZ_302
	+ /N216 * N214 * /N217 * N_PZ_302
	+ /N214 * /N215 * N_PZ_298 * N_PZ_302
	+ N213 * /N216 * N214 * /N217 * /N_PZ_298
	+ /N216 * /N214 * N215 * /N217 * /N_PZ_297
   /"ad<2>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<2>".CLKF  =  rd	;GCK
    "ad<2>".PRLD  =  Gnd

/"ad<3>" := N216 * N_PZ_320
	+ N212 * /N213 * N_PZ_298 * N_PZ_302
	+ /N212 * N213 * N216 * N214
	+ /N216 * /N217 * N_PZ_298 * /N_PZ_297
	+ N212 * N213 * N214 * /N215 * /N_PZ_320
	+ N213 * /N215 * N_PZ_277 * N_PZ_302 * /N_PZ_320
	+ /N213 * /N216 * /N214 * /N_PZ_297 * /N_PZ_302
	+ /N216 * /N214 * N215 * /N217 * /N_PZ_297
   /"ad<3>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<3>".CLKF  =  rd	;GCK
    "ad<3>".PRLD  =  Gnd

/"ad<4>" := N216 * N_PZ_320
	+ N214 * N_PZ_302
	+ N_PZ_277 * N_PZ_297
	+ /N212 * N213 * N217
	+ N213 * /N216 * N214
	+ N212 * /N214 * /N_PZ_297 * /N_PZ_320
	+ /N213 * N214 * /N217 * /N_PZ_298
   /"ad<4>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<4>".CLKF  =  rd	;GCK
    "ad<4>".PRLD  =  Gnd

/"ad<5>" := N216 * N_PZ_320
	+ N212 * /N215 * N_PZ_298
	+ N213 * /N_PZ_298 * N_PZ_302
	+ /N213 * N216 * N_PZ_298
	+ /N216 * N214 * N_PZ_297
	+ /N214 * N217 * /N_PZ_298
	+ /N214 * /N_PZ_298 * N_PZ_302
	+ N212 * /N213 * /N216 * /N_PZ_302
	+ N212 * N216 * N214 * /N_PZ_302
	+ /N212 * /N213 * N_PZ_298 * /N_PZ_297
   /"ad<5>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<5>".CLKF  =  rd	;GCK
    "ad<5>".PRLD  =  Gnd

/"ad<6>" := N216 * N_PZ_320
	+ N212 * /N213 * N_PZ_298
	+ /N213 * /N214 * N_PZ_298
	+ N216 * /N214 * N_PZ_297
	+ N214 * N217 * /N_PZ_298
	+ N212 * N213 * N_PZ_277 * /N_PZ_302
	+ /N212 * N213 * N214 * /N_PZ_298
	+ N213 * /N216 * /N214 * /N_PZ_302
	+ N216 * N214 * /N215 * N_PZ_302
	+ N212 * N213 * /N216 * /N214 * /N217
	+ /N212 * /N213 * /N216 * /N214 * /N217
	+ N212 * /N213 * /N216 * N214 * /N217 * /N_PZ_302
   /"ad<6>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<6>".CLKF  =  rd	;GCK
    "ad<6>".PRLD  =  Gnd

/"ad<7>" := N216 * N_PZ_297
	+ N216 * N_PZ_320
	+ N213 * /N214 * N217
	+ /N213 * N214 * N217
	+ N216 * N214 * N215
	+ N216 * /N214 * N_PZ_302
	+ N212 * N213 * /N216 * /N217
	+ N212 * /N214 * N_PZ_277 * N_PZ_302
	+ /N216 * N214 * /N215 * /N_PZ_302
	+ /N213 * /N216 * /N214 * /N217 * /N_PZ_297
   /"ad<7>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<7>".CLKF  =  rd	;GCK
    "ad<7>".PRLD  =  Gnd

/"ad<8>" := N216 * N217
	+ N214 * N_PZ_298
	+ /N213 * /N215 * N217
	+ N212 * N213 * N214 * /N215
	+ N212 * /N214 * N215 * /N217
	+ /N212 * /N213 * /N216 * /N215
	+ N213 * N216 * N214 * /N215
	+ N213 * N216 * /N214 * N215
	+ N213 * /N216 * /N214 * /N215 * /N217
   /"ad<8>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<8>".CLKF  =  rd	;GCK
    "ad<8>".PRLD  =  Gnd

/"ad<9>" := /N_PZ_302 * N_PZ_320
	+ N212 * N216 * N214
	+ /N212 * N214 * N217
	+ N213 * N216 * N215
	+ N213 * /N214 * /N_PZ_302
	+ /N213 * N215 * N217
	+ N216 * /N214 * N_PZ_298
	+ N212 * /N213 * /N216 * /N214
	+ N213 * N214 * N_PZ_302 * /N_PZ_320
	+ N213 * /N216 * /N215 * /N217 * N_PZ_302
   /"ad<9>".TRST  =  /cs * /rd * /"d<7>".PIN
    "ad<9>".CLKF  =  rd	;GCK
    "ad<9>".PRLD  =  Gnd

/"d<0>" := /mmc_in * N_PZ_281
	+ /"ad<15>".PIN * /ramcs * /wr * /"d<0>".PIN
   /"d<0>".TRST  =  /rd * /wr
    "d<0>".CLKF  =  mmc_clk
    "d<0>".PRLD  =  Gnd

/N_PZ_281 = /"ad<15>".PIN * /ramcs * /wr

/mmc_clk = /cs * "d<7>".PIN

/"d<1>" := N_PZ_281 * /"d<0>"
	+ /"ad<15>".PIN * /ramcs * /wr * /"d<1>".PIN
   /"d<1>".TRST  =  /rd * /wr
    "d<1>".CLKF  =  mmc_clk
    "d<1>".PRLD  =  Gnd

/"d<2>" := N_PZ_281 * /"d<1>"
	+ /"ad<15>".PIN * /ramcs * /wr * /"d<2>".PIN
   /"d<2>".TRST  =  /rd * /wr
    "d<2>".CLKF  =  mmc_clk
    "d<2>".PRLD  =  Gnd

/"d<3>" := N_PZ_281 * /"d<2>"
	+ /"ad<15>".PIN * /ramcs * /wr * /"d<3>".PIN
   /"d<3>".TRST  =  /rd * /wr
    "d<3>".CLKF  =  mmc_clk
    "d<3>".PRLD  =  Gnd

/"d<4>" := N_PZ_281 * /"d<3>"
	+ /"ad<15>".PIN * /ramcs * /wr * /"d<4>".PIN
   /"d<4>".TRST  =  /rd * /wr
    "d<4>".CLKF  =  mmc_clk
    "d<4>".PRLD  =  Gnd

/"d<5>" := N_PZ_281 * /"d<4>"
	+ /"ad<15>".PIN * /ramcs * /wr * /"d<5>".PIN
   /"d<5>".TRST  =  /rd * /wr
    "d<5>".CLKF  =  mmc_clk
    "d<5>".PRLD  =  Gnd

/"d<6>" := N_PZ_281 * /"d<5>"
	+ /"ad<15>".PIN * /ramcs * /wr * /"d<6>".PIN
   /"d<6>".TRST  =  /rd * /wr
    "d<6>".CLKF  =  mmc_clk
    "d<6>".PRLD  =  Gnd

/"d<7>" := N_PZ_281 * /"d<6>"
	+ /"d<7>".PIN * /"ad<15>".PIN * /ramcs * /wr
   /"d<7>".TRST  =  /rd * /wr
    "d<7>".CLKF  =  mmc_clk
    "d<7>".PRLD  =  Gnd

 mmc_cs := "d<0>".PIN
    mmc_cs.CLKF  =  /("ad<15>".PIN * /ramcs * /wr)
    mmc_cs.PRLD  =  Gnd

/mmc_out := N_PZ_281 * /"d<6>"
	+ /"d<7>".PIN * /"ad<15>".PIN * /ramcs * /wr
    mmc_out.CLKF  =  mmc_clk
    mmc_out.PRLD  =  Gnd

****************************  Device Pin Out ****************************

Device : XCR3064XL-6-PC44


                         m           a     
          a  a  a        m  r        d  a  
          d  d  d        c  a        <  d  
          <  <  <  V     _  m     G  1  <  
          2  3  6  C  r  i  c  w  N  2  9  
          >  >  >  C  d  n  s  r  D  >  >  
          --------------------------------  
         /6  5  4  3  2  1  44 43 42 41 40 \
    TDI | 7                             39 | ad<11>
  ad<1> | 8                             38 | TDO
  ad<4> | 9                             37 | ad<5>
     PE | 10                            36 | ad<10>
   d<7> | 11       XCR3064XL-6-PC44     35 | VCC
mmc_out | 12                            34 | mmc_clk
    TMS | 13                            33 | mmc_cs
  ad<0> | 14                            32 | TCK
    VCC | 15                            31 | ad<7>
   d<1> | 16                            30 | GND
   d<2> | 17                            29 | ad<15>
        \ 18 19 20 21 22 23 24 25 26 27 28 /
          --------------------------------  
          d  d  d  d  G  V  c  d  a  a  a  
          <  <  <  <  N  C  s  <  d  d  d  
          3  4  5  6  D  C     0  <  <  <  
          >  >  >  >           >  8  1  1  
                                  >  4  3  
                                     >  >  


Legend :  NC  = Not Connected, unbonded pin
          PE  = Port Enable pin
         WPU  = Unused with Internal Weak Pull Up
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XCR3*XL*-*
Use Timing Constraints                      : ON
Use Design Location Constraints             : ON
Reserve JTAG Port Pins for ISP              : ON
Use Fast Input Registers                    : ON
Use Foldback NANDs                          : OFF
Default Register Initial State              : RESET
Output Slew Rate                            : FAST
Optimizing Method                           : DENSITY
Collapsing Pterm Limit                      : 28
Collapsing Input Limit                      : 32
Function Block Input Limit                  : 38
Multi Level Logic Optimization              : ON
Enable WYSIWYG mode                         : OFF
Enable Exhaustive Fitting                   : OFF
