 
cpldfit:  version E.37                              Xilinx Inc.
                                  Fitter Report
Design Name: main_k                              Date:  6-18-2002,  8:55PM
Device Used: XC9572XL-5-PC44
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
35 /72  ( 48%) 326 /360  ( 90%) 34 /72  ( 47%) 32 /34  ( 94%) 70 /216 ( 32%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    5           5    |  I/O              :    27        1
Output        :   19          19    |  GCK/IO           :     2        1
Bidirectional :    8           8    |  GTS/IO           :     2        0
GCK           :    0           0    |  GSR/IO           :     1        0
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     32          32

MACROCELL RESOURCES:

Total Macrocells Available                    72
Registered Macrocells                         34
Non-registered Macrocell driving I/O           1

GLOBAL RESOURCES:

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 35 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 35 macrocells used (MC).

End of Resource Summary
****************************  Errors and Warnings  *************************

WARNING:Cpld:824 - Signal 'N158.CE' has been minimized to 'VCC'.
     The signal is removed.
WARNING:Cpld:824 - Signal 'N160.CE' has been minimized to 'VCC'.
     The signal is removed.
WARNING:Cpld:824 - Signal 'N159.CE' has been minimized to 'VCC'.
     The signal is removed.
WARNING:Cpld:824 - Signal 'N162.CE' has been minimized to 'VCC'.
     The signal is removed.
WARNING:Cpld:824 - Signal 'N163.CE' has been minimized to 'VCC'.
     The signal is removed.
WARNING:Cpld:824 - Signal 'N164.CE' has been minimized to 'VCC'.
     The signal is removed.
WARNING:Cpld:824 - Signal 'N161.CE' has been minimized to 'VCC'.
     The signal is removed.
WARNING:Cpld:824 - Signal 'N157.CE' has been minimized to 'VCC'.
     The signal is removed.
WARNING:Cpld:825 - Signal 'N153.CLKF' has been minimized to 'GND'.
WARNING:Cpld:825 - Signal 'N152.CLKF' has been minimized to 'GND'.
WARNING:Cpld:825 - Signal 'N151.CLKF' has been minimized to 'GND'.
WARNING:Cpld:825 - Signal 'N150.CLKF' has been minimized to 'GND'.
WARNING:Cpld:825 - Signal 'N149.CLKF' has been minimized to 'GND'.
WARNING:Cpld:825 - Signal 'N148.CLKF' has been minimized to 'GND'.
WARNING:Cpld:825 - Signal 'N147.CLKF' has been minimized to 'GND'.
WARNING:Cpld:825 - Signal 'N146.CLKF' has been minimized to 'GND'.
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
N157                3       4       FB3_14  STD       19   I/O       I
N158                4       5       FB4_18  STD            (b)       (b)
N159                4       6       FB4_16  STD            (b)       (b)
N160                4       7       FB4_13  STD            (b)       (b)
N161                4       8       FB4_1   STD            (b)       (b)
N162                4       9       FB3_10  STD            (b)       (b)
N163                4       10      FB1_16  STD            (b)       (b)
N164                4       11      FB2_1   STD            (b)       (b)
ad<0>               15      10      FB2_5   STD  FAST 36   I/O       I/O
ad<10>              16      10      FB1_14  STD  FAST 7    GCK/I/O   O
ad<11>              12      10      FB3_11  STD  FAST 18   I/O       O
ad<12>              16      10      FB1_17  STD  FAST 9    I/O       O
ad<13>              17      10      FB1_2   STD  FAST 1    I/O       O
ad<14>              14      10      FB3_5   STD  FAST 12   I/O       O
ad<15>              16      10      FB2_17  STD  FAST 44   I/O       O
ad<1>               15      10      FB2_8   STD  FAST 38   I/O       I/O
ad<2>               12      10      FB3_15  STD  FAST 20   I/O       I/O
ad<3>               15      10      FB2_11  STD  FAST 40   GTS/I/O   I/O
ad<4>               15      10      FB3_17  STD  FAST 22   I/O       I/O
ad<5>               17      10      FB1_6   STD  FAST 3    I/O       I/O
ad<6>               15      10      FB3_2   STD  FAST 11   I/O       I/O
ad<7>               13      10      FB3_8   STD  FAST 13   I/O       I/O
ad<8>               17      10      FB1_9   STD  FAST 5    GCK/I/O   O
ad<9>               16      10      FB2_2   STD  FAST 35   I/O       O
d<0>                6       7       FB4_2   STD  FAST 25   I/O       O
d<1>                6       7       FB4_5   STD  FAST 26   I/O       O
d<2>                6       7       FB4_8   STD  FAST 27   I/O       O
d<3>                6       7       FB4_11  STD  FAST 28   I/O       O
d<4>                6       7       FB4_14  STD  FAST 29   I/O       O
d<5>                6       7       FB4_15  STD  FAST 33   I/O       O
d<6>                6       7       FB4_17  STD  FAST 34   I/O       O
d<7>                6       7       FB2_14  STD  FAST 42   GTS/I/O   O
mmc_clk             1       3       FB3_16  STD  FAST 24   I/O       O
mmc_cs              3       6       FB1_5   STD  FAST 2    I/O       O
mmc_out             2       5       FB2_15  STD  FAST 43   I/O       O

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
mmc_in                              FB1_15            8    I/O       I
ramcs                               FB3_14            19   I/O       I
rd                                  FB2_6             37   I/O       I
romcs                               FB2_9             39   GSR/I/O   I
wr                                  FB1_8             4    I/O       I

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1           7          16          16           90         5/1        9   
FB2           8          18          18           89         4/3        9   
FB3           9          14          14           89         3/4        9   
FB4          11          22          22           58         7/0        7   
            ----                                -----       -----     ----- 
             35                                  326        19/8       34   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               16/38
Number of signals used by logic mapping into function block:  16
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0   /\5   0     FB1_1               (b)     (b)
ad<13>               17      13<- /\1   0     FB1_2   STD   1     I/O     O
(unused)              0       0   /\5   0     FB1_3               (b)     (b)
(unused)              0       0   /\5   0     FB1_4               (b)     (b)
mmc_cs                3       1<- /\3   0     FB1_5   STD   2     I/O     O
ad<5>                17      13<- /\1   0     FB1_6   STD   3     I/O     I/O
(unused)              0       0   /\5   0     FB1_7               (b)     (b)
(unused)              0       0   /\5   0     FB1_8         4     I/O     I
ad<8>                17      15<- /\3   0     FB1_9   STD   5     GCK/I/O O
(unused)              0       0   /\5   0     FB1_10              (b)     (b)
(unused)              0       0   /\5   0     FB1_11        6     GCK/I/O (b)
(unused)              0       0   /\5   0     FB1_12              (b)     (b)
(unused)              0       0   \/5   0     FB1_13              (b)     (b)
ad<10>               16      11<-   0   0     FB1_14  STD   7     GCK/I/O O
(unused)              0       0   /\5   0     FB1_15        8     I/O     I
N163                  4       0   /\1   0     FB1_16  STD         (b)     (b)
ad<12>               16      11<-   0   0     FB1_17  STD   9     I/O     O
(unused)              0       0   /\5   0     FB1_18              (b)     (b)

Signals Used by Logic in Function Block
  1: N157               7: N163              12: romcs 
  2: N158               8: N164              13: rd 
  3: N159               9: "ad<0>".PIN       14: wr 
  4: N160              10: "ad<1>".PIN       15: ramcs 
  5: N161              11: "ad<6>".PIN       16: "d<0>" 
  6: N162             

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
ad<13>               XXXXXXXX...XX........................... 10      10
mmc_cs               ........XX..XXXX........................ 6       6
ad<5>                XXXXXXXX...XX........................... 10      10
ad<8>                XXXXXXXX...XX........................... 10      10
ad<10>               XXXXXXXX...XX........................... 10      10
N163                 XXXXXXX...XXX........................... 10      10
ad<12>               XXXXXXXX...XX........................... 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               18/36
Number of signals used by logic mapping into function block:  18
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
N164                  4       0   /\1   0     FB2_1   STD         (b)     (b)
ad<9>                16      11<-   0   0     FB2_2   STD   35    I/O     O
(unused)              0       0   /\5   0     FB2_3               (b)     (b)
(unused)              0       0   /\5   0     FB2_4               (b)     (b)
ad<0>                15      11<- /\1   0     FB2_5   STD   36    I/O     I/O
(unused)              0       0   /\5   0     FB2_6         37    I/O     I
(unused)              0       0   /\5   0     FB2_7               (b)     (b)
ad<1>                15      11<- /\1   0     FB2_8   STD   38    I/O     I/O
(unused)              0       0   /\5   0     FB2_9         39    GSR/I/O I
(unused)              0       0   /\5   0     FB2_10              (b)     (b)
ad<3>                15      11<- /\1   0     FB2_11  STD   40    GTS/I/O I/O
(unused)              0       0   /\5   0     FB2_12              (b)     (b)
(unused)              0       0   /\5   0     FB2_13              (b)     (b)
d<7>                  6       3<- /\1   1     FB2_14  STD   42    GTS/I/O O
mmc_out               2       0   /\3   0     FB2_15  STD   43    I/O     O
(unused)              0       0   \/5   0     FB2_16              (b)     (b)
ad<15>               16      11<-   0   0     FB2_17  STD   44    I/O     O
(unused)              0       0   /\5   0     FB2_18              (b)     (b)

Signals Used by Logic in Function Block
  1: N157               7: N163              13: rd 
  2: N158               8: N164              14: wr 
  3: N159               9: "ad<0>".PIN       15: ramcs 
  4: N160              10: "ad<1>".PIN       16: "d<6>" 
  5: N161              11: "ad<7>".PIN       17: "d<7>" 
  6: N162              12: romcs             18: mmc_cs 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
N164                 XXXXXXXX..XXX........................... 11      11
ad<9>                XXXXXXXX...XX........................... 10      10
ad<0>                XXXXXXXX...XX........................... 10      10
ad<1>                XXXXXXXX...XX........................... 10      10
ad<3>                XXXXXXXX...XX........................... 10      10
d<7>                 ........XX..XXXXX....................... 7       7
mmc_out              ........XX....X.XX...................... 5       5
ad<15>               XXXXXXXX...XX........................... 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining:               14/40
Number of signals used by logic mapping into function block:  14
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0   /\5   0     FB3_1               (b)     (b)
ad<6>                15      11<- /\1   0     FB3_2   STD   11    I/O     I/O
(unused)              0       0   /\5   0     FB3_3               (b)     (b)
(unused)              0       0   /\5   0     FB3_4               (b)     (b)
ad<14>               14      10<- /\1   0     FB3_5   STD   12    I/O     O
(unused)              0       0   /\5   0     FB3_6               (b)     (b)
(unused)              0       0   /\5   0     FB3_7               (b)     (b)
ad<7>                13       8<-   0   0     FB3_8   STD   13    I/O     I/O
(unused)              0       0   /\5   0     FB3_9         14    I/O     (b)
N162                  4       2<- /\3   0     FB3_10  STD         (b)     (b)
ad<11>               12       9<- /\2   0     FB3_11  STD   18    I/O     O
(unused)              0       0   /\5   0     FB3_12              (b)     (b)
(unused)              0       0   /\4   1     FB3_13              (b)     (b)
N157                  3       0   \/2   0     FB3_14  STD   19    I/O     I
ad<2>                12       7<-   0   0     FB3_15  STD   20    I/O     I/O
mmc_clk               1       1<- /\5   0     FB3_16  STD   24    I/O     O
ad<4>                15      11<- /\1   0     FB3_17  STD   22    I/O     I/O
(unused)              0       0   /\5   0     FB3_18              (b)     (b)

Signals Used by Logic in Function Block
  1: N157               6: N162              11: "ad<5>".PIN 
  2: N158               7: N163              12: romcs 
  3: N159               8: N164              13: rd 
  4: N160               9: "ad<0>".PIN       14: ramcs 
  5: N161              10: "ad<1>".PIN      

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
ad<6>                XXXXXXXX...XX........................... 10      10
ad<14>               XXXXXXXX...XX........................... 10      10
ad<7>                XXXXXXXX...XX........................... 10      10
N162                 XXXXXX....XXX........................... 9       9
ad<11>               XXXXXXXX...XX........................... 10      10
N157                 X.......X..XX........................... 4       4
ad<2>                XXXXXXXX...XX........................... 10      10
mmc_clk              ........XX...X.......................... 3       3
ad<4>                XXXXXXXX...XX........................... 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining:               22/32
Number of signals used by logic mapping into function block:  22
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
N161                  4       0   /\1   0     FB4_1   STD         (b)     (b)
d<0>                  6       2<-   0   1     FB4_2   STD   25    I/O     O
(unused)              0       0   /\2   3     FB4_3               (b)     (b)
(unused)              0       0   \/1   4     FB4_4               (b)     (b)
d<1>                  6       2<-   0   1     FB4_5   STD   26    I/O     O
(unused)              0       0   /\1   4     FB4_6               (b)     (b)
(unused)              0       0   \/1   4     FB4_7               (b)     (b)
d<2>                  6       2<-   0   1     FB4_8   STD   27    I/O     O
(unused)              0       0   /\1   4     FB4_9               (b)     (b)
(unused)              0       0   \/2   3     FB4_10              (b)     (b)
d<3>                  6       2<-   0   1     FB4_11  STD   28    I/O     O
(unused)              0       0   \/2   3     FB4_12              (b)     (b)
N160                  4       2<- \/3   0     FB4_13  STD         (b)     (b)
d<4>                  6       3<- \/1   1     FB4_14  STD   29    I/O     O
d<5>                  6       2<-   0   1     FB4_15  STD   33    I/O     O
N159                  4       0   /\1   0     FB4_16  STD         (b)     (b)
d<6>                  6       2<-   0   1     FB4_17  STD   34    I/O     O
N158                  4       1<- /\2   0     FB4_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: N157               9: "ad<3>".PIN       16: "d<0>" 
  2: N158              10: "ad<4>".PIN       17: "d<1>" 
  3: N159              11: romcs             18: "d<2>" 
  4: N160              12: rd                19: "d<3>" 
  5: N161              13: mmc_in            20: "d<4>" 
  6: "ad<0>".PIN       14: wr                21: "d<5>" 
  7: "ad<1>".PIN       15: ramcs             22: "d<6>" 
  8: "ad<2>".PIN      

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
N161                 XXXXX....XXX............................ 8       8
d<0>                 .....XX....XXXXX........................ 7       7
d<1>                 .....XX....X.XXXX....................... 7       7
d<2>                 .....XX....X.XX.XX...................... 7       7
d<3>                 .....XX....X.XX..XX..................... 7       7
N160                 XXXX....X.XX............................ 7       7
d<4>                 .....XX....X.XX...XX.................... 7       7
d<5>                 .....XX....X.XX....XX................... 7       7
N159                 XXX....X..XX............................ 6       6
d<6>                 .....XX....X.XX.....XX.................. 7       7
N158                 XX....X...XX............................ 5       5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

/"d<0>"  :=  "ad<0>".PIN * /mmc_in
	+ /"ad<1>".PIN * /mmc_in
	+ ramcs * /mmc_in
;Imported pterms FB4_3
	+ wr * /mmc_in
	+ rd * /"d<0>" * /"ad<0>".PIN * "ad<1>".PIN * 
	/ramcs * /wr
    "d<0>".CLKF  =  Gnd
   /"d<0>".TRST  =  /rd * /"ad<0>".PIN * "ad<1>".PIN * /ramcs
    "d<0>".PRLD  =  GND    

/"d<1>"  :=  /"d<0>" * "ad<0>".PIN
	+ /"d<0>" * /"ad<1>".PIN
	+ /"d<0>" * ramcs
;Imported pterms FB4_4
	+ /"d<0>" * wr
;Imported pterms FB4_6
	+ rd * /"d<1>" * /"ad<0>".PIN * "ad<1>".PIN * 
	/ramcs * /wr
    "d<1>".CLKF  =  Gnd
   /"d<1>".TRST  =  /rd * /"ad<0>".PIN * "ad<1>".PIN * /ramcs
    "d<1>".PRLD  =  GND    

/"d<2>"  :=  /"d<1>" * "ad<0>".PIN
	+ /"d<1>" * /"ad<1>".PIN
	+ /"d<1>" * ramcs
;Imported pterms FB4_7
	+ /"d<1>" * wr
;Imported pterms FB4_9
	+ rd * /"d<2>" * /"ad<0>".PIN * "ad<1>".PIN * 
	/ramcs * /wr
    "d<2>".CLKF  =  Gnd
   /"d<2>".TRST  =  /rd * /"ad<0>".PIN * "ad<1>".PIN * /ramcs
    "d<2>".PRLD  =  GND    

/"d<3>"  :=  /"d<2>" * "ad<0>".PIN
	+ /"d<2>" * /"ad<1>".PIN
	+ /"d<2>" * ramcs
;Imported pterms FB4_10
	+ /"d<2>" * wr
	+ rd * /"d<3>" * /"ad<0>".PIN * "ad<1>".PIN * 
	/ramcs * /wr
    "d<3>".CLKF  =  Gnd
   /"d<3>".TRST  =  /rd * /"ad<0>".PIN * "ad<1>".PIN * /ramcs
    "d<3>".PRLD  =  GND    

/"d<4>"  :=  /"d<3>" * "ad<0>".PIN
	+ /"d<3>" * /"ad<1>".PIN
;Imported pterms FB4_13
	+ /"d<3>" * ramcs
	+ /"d<3>" * wr
	+ rd * /"d<4>" * /"ad<0>".PIN * "ad<1>".PIN * 
	/ramcs * /wr
    "d<4>".CLKF  =  Gnd
   /"d<4>".TRST  =  /rd * /"ad<0>".PIN * "ad<1>".PIN * /ramcs
    "d<4>".PRLD  =  GND    

/"d<5>"  :=  /"d<4>" * "ad<0>".PIN
	+ /"d<4>" * /"ad<1>".PIN
	+ /"d<4>" * ramcs
;Imported pterms FB4_14
	+ /"d<4>" * wr
;Imported pterms FB4_16
	+ rd * /"d<5>" * /"ad<0>".PIN * "ad<1>".PIN * 
	/ramcs * /wr
    "d<5>".CLKF  =  Gnd
   /"d<5>".TRST  =  /rd * /"ad<0>".PIN * "ad<1>".PIN * /ramcs
    "d<5>".PRLD  =  GND    

/"d<6>"  :=  /"d<5>" * "ad<0>".PIN
	+ /"d<5>" * /"ad<1>".PIN
	+ /"d<5>" * ramcs
;Imported pterms FB4_18
	+ /"d<5>" * wr
	+ rd * /"d<6>" * /"ad<0>".PIN * "ad<1>".PIN * 
	/ramcs * /wr
    "d<6>".CLKF  =  Gnd
   /"d<6>".TRST  =  /rd * /"ad<0>".PIN * "ad<1>".PIN * /ramcs
    "d<6>".PRLD  =  GND    

/"d<7>"  :=  /"d<6>" * "ad<0>".PIN
	+ /"d<6>" * /"ad<1>".PIN
;Imported pterms FB2_15
	+ /"d<6>" * ramcs
	+ /"d<6>" * wr
	+ rd * /"d<7>" * /"ad<0>".PIN * "ad<1>".PIN * 
	/ramcs * /wr
    "d<7>".CLKF  =  Gnd
   /"d<7>".TRST  =  /rd * /"ad<0>".PIN * "ad<1>".PIN * /ramcs
    "d<7>".PRLD  =  GND    

/mmc_clk  =  ;Imported pterms FB3_17
	  /"ad<0>".PIN * /"ad<1>".PIN * /ramcs    

 mmc_cs  :=  "d<0>"
;Imported pterms FB1_6
	+ /rd * /"ad<0>".PIN * "ad<1>".PIN * /ramcs
    mmc_cs.CLKF  =  "ad<0>".PIN * /"ad<1>".PIN * /ramcs * /wr
    mmc_cs.PRLD  =  VCC    

 mmc_out  :=  "d<7>"
    mmc_out.CLKF  =  /"ad<0>".PIN * /"ad<1>".PIN * /ramcs * /mmc_cs
    mmc_out.PRLD  =  GND    

 N157  :=  "ad<0>".PIN * romcs
	+ /N157 * /romcs
    N157.CLKF  =  rd * /romcs
    N157.PRLD  =  GND    

 N158  :=  "ad<1>".PIN * romcs
	+ N157 * /N158 * /romcs
;Imported pterms FB4_1
	+ /N157 * N158 * /romcs
    N158.CLKF  =  rd * /romcs
    N158.PRLD  =  GND    

 N159.T  =  N157 * N158 * /romcs
	+ N159 * romcs * /"ad<2>".PIN
	+ /N159 * romcs * "ad<2>".PIN
    N159.CLKF  =  rd * /romcs
    N159.PRLD  =  GND    

 N160.T  =  N157 * N158 * N159 * /romcs
;Imported pterms FB4_12
	+ N160 * romcs * /"ad<3>".PIN
	+ /N160 * romcs * "ad<3>".PIN
    N160.CLKF  =  rd * /romcs
    N160.PRLD  =  GND    

 N161.T  =  N161 * romcs * /"ad<4>".PIN
	+ /N161 * romcs * "ad<4>".PIN
	+ N157 * N158 * N159 * N160 * /romcs
    N161.CLKF  =  rd * /romcs
    N161.PRLD  =  GND    

 N162.T  =  N157 * N158 * N161 * N159 * N160 * /romcs
;Imported pterms FB3_11
	+ N162 * romcs * /"ad<5>".PIN
	+ /N162 * romcs * "ad<5>".PIN
    N162.CLKF  =  rd * /romcs
    N162.PRLD  =  GND    

 N163.T  =  N163 * romcs * /"ad<6>".PIN
	+ /N163 * romcs * "ad<6>".PIN
	+ N157 * N158 * N161 * N159 * N162 * N160 * 
	/romcs
    N163.CLKF  =  rd * /romcs
    N163.PRLD  =  GND    

 N164.T  =  N164 * romcs * /"ad<7>".PIN
	+ /N164 * romcs * "ad<7>".PIN
	+ N157 * N158 * N161 * N159 * N162 * N160 * 
	N163 * /romcs
    N164.CLKF  =  rd * /romcs
    N164.PRLD  =  GND    

 "ad<0>"  :=  N157 * N161 * N159 * /N162 * N160 * /N163 * 
	/N164
	+ /N158 * N161 * /N159 * N162 * /N160 * /N163 * 
	/N164
;Imported pterms FB2_6
	+ N157 * /N161 * /N159 * /N162 * /N160 * /N164
	+ N158 * /N161 * /N159 * /N162 * /N160 * /N164
	+ N157 * N158 * N161 * /N162 * N160 * /N163 * 
	/N164
	+ N157 * /N158 * /N159 * N162 * /N160 * /N163 * 
	/N164
	+ /N157 * N158 * /N161 * /N159 * /N160 * /N163 * 
	/N164
;Imported pterms FB2_7
	+ /N158 * /N161 * /N159 * /N162 * /N163 * /N164
	+ N157 * /N158 * /N161 * N159 * N160 * /N163 * 
	/N164
	+ /N157 * /N158 * N161 * N159 * N162 * /N163 * 
	/N164
	+ /N157 * /N158 * /N159 * /N162 * N160 * /N163 * 
	/N164
	+ /N157 * N161 * N159 * N162 * /N160 * /N163 * 
	/N164
;Imported pterms FB2_8
	+ N157 * N161 * /N159 * N162 * /N160 * /N163 * 
	/N164
    "ad<0>".CLKF  =  rd
    "ad<0>".TRST  =  /rd * /romcs
    "ad<0>".PRLD  =  GND    

 "ad<10>"  :=  /N158 * /N161 * /N159 * N162 * /N163 * /N164
	+ N157 * /N158 * N161 * N162 * /N160 * /N163 * 
	/N164
	+ /N157 * N158 * /N161 * N159 * /N162 * /N163 * 
	/N164
;Imported pterms FB1_13
	+ N157 * N158 * /N161 * /N159 * N160 * /N163 * 
	/N164
	+ N157 * N161 * N159 * N162 * N160 * /N163 * 
	/N164
	+ /N157 * N158 * N161 * N162 * /N160 * /N163 * 
	/N164
	+ /N157 * N158 * /N161 * /N159 * /N160 * /N163 * 
	/N164
	+ N158 * /N161 * N159 * /N162 * /N160 * /N163 * 
	/N164
;Imported pterms FB1_15
	+ N157 * /N158 * /N161 * N159 * /N162 * /N163 * 
	/N164
	+ /N157 * /N158 * /N161 * /N159 * N160 * /N163 * 
	/N164
	+ /N157 * /N158 * /N159 * N162 * N160 * /N163 * 
	/N164
	+ N157 * N158 * /N161 * /N159 * /N162 * /N160 * 
	N163 * /N164
	+ N157 * /N158 * N161 * /N159 * /N162 * N160 * 
	/N163 * /N164
;Imported pterms FB1_16
	+ /N157 * /N158 * /N161 * /N159 * /N162 * /N160 * 
	N163 * /N164
    "ad<10>".CLKF  =  rd
    "ad<10>".TRST  =  /rd * /romcs
    "ad<10>".PRLD  =  GND    

 "ad<11>"  :=  N157 * /N158 * N161 * /N159 * /N160 * /N163 * 
	/N164
;Imported pterms FB3_12
	+ /N157 * N158 * /N159 * /N160 * /N163 * /N164
	+ /N157 * /N161 * N162 * /N160 * /N163 * /N164
	+ N161 * N159 * N162 * N160 * /N163 * /N164
	+ N161 * /N159 * /N162 * N160 * /N163 * /N164
	+ /N158 * /N161 * /N159 * N162 * /N160 * /N163 * 
	/N164
;Imported pterms FB3_13
	+ N157 * /N158 * N159 * N160 * /N163 * /N164
	+ /N157 * N158 * N161 * /N162 * /N160 * /N163 * 
	/N164
	+ N157 * N158 * /N161 * /N159 * /N162 * /N160 * 
	N163 * /N164
	+ /N157 * N158 * /N161 * N159 * /N162 * N160 * 
	/N163 * /N164
    "ad<11>".CLKF  =  rd
    "ad<11>".TRST  =  /rd * /romcs
    "ad<11>".PRLD  =  GND    

 "ad<12>"  :=  N157 * N161 * N160 * /N163 * /N164
	+ /N158 * N161 * /N159 * /N163 * /N164
	+ /N157 * N158 * /N161 * N159 * N160 * /N163 * 
	/N164
;Imported pterms FB1_18
	+ /N157 * /N159 * /N160 * /N163 * /N164
	+ /N157 * N158 * /N159 * /N162 * /N163 * /N164
	+ N158 * N159 * N162 * N160 * /N163 * /N164
	+ /N158 * /N161 * N162 * /N160 * /N163 * /N164
	+ /N158 * N159 * /N162 * N160 * /N163 * /N164
;Imported pterms FB1_1
	+ N157 * N158 * N162 * N160 * /N163 * /N164
	+ N157 * /N161 * N159 * N162 * /N163 * /N164
	+ /N157 * /N158 * N161 * N162 * /N163 * /N164
	+ N158 * N161 * /N162 * /N160 * /N163 * /N164
	+ /N157 * /N158 * /N161 * /N159 * /N162 * /N160 * 
	/N164
;Imported pterms FB1_2
	+ N157 * N158 * /N161 * /N159 * /N162 * /N160 * 
	N163 * /N164
    "ad<12>".CLKF  =  rd
    "ad<12>".TRST  =  /rd * /romcs
    "ad<12>".PRLD  =  GND    

/"ad<13>"  :=  N164
	+ /N157 * N163
;Imported pterms FB1_3
	+ /N158 * N163
	+ N161 * N163
	+ N159 * N163
	+ N162 * N163
	+ N160 * N163
;Imported pterms FB1_4
	+ /N157 * /N161 * /N159 * N162
	+ N157 * N158 * N159 * N162 * /N160
	+ /N157 * N158 * N161 * N162 * /N160
	+ /N157 * N158 * N159 * /N162 * N160
	+ N158 * N161 * N159 * /N162 * N160
;Imported pterms FB1_5
	+ N157 * /N158 * N161 * N159 * N162
	+ N157 * /N158 * N161 * /N159 * /N162 * N160
	+ N157 * /N158 * /N161 * N159 * /N162 * /N160
    "ad<13>".CLKF  =  rd
    "ad<13>".TRST  =  /rd * /romcs
    "ad<13>".PRLD  =  GND    

 "ad<14>"  :=  N157 * /N161 * /N159 * /N162 * /N160 * /N164
	+ /N158 * /N161 * N159 * N162 * /N160 * /N163 * 
	/N164
;Imported pterms FB3_6
	+ N157 * /N158 * N161 * N160 * /N163 * /N164
	+ N157 * N161 * /N159 * N160 * /N163 * /N164
	+ /N157 * N158 * N159 * N160 * /N163 * /N164
	+ /N157 * N158 * /N162 * N160 * /N163 * /N164
	+ /N157 * N161 * N159 * N162 * /N160 * /N163 * 
	/N164
;Imported pterms FB3_7
	+ N158 * N161 * /N162 * /N163 * /N164
	+ N157 * /N161 * N159 * N162 * /N163 * /N164
	+ /N157 * N158 * /N159 * /N160 * /N163 * /N164
	+ /N157 * N159 * /N162 * N160 * /N163 * /N164
	+ N161 * /N159 * /N162 * /N160 * /N163 * /N164
    "ad<14>".CLKF  =  rd
    "ad<14>".TRST  =  /rd * /romcs
    "ad<14>".PRLD  =  GND    

 "ad<15>"  :=  N157 * N158 * /N161 * /N159 * /N162 * /N160 * 
	/N164
	+ N157 * N161 * /N159 * /N162 * N160 * /N163 * 
	/N164
	+ /N158 * /N161 * N159 * N162 * /N160 * /N163 * 
	/N164
;Imported pterms FB2_16
	+ N157 * N158 * N161 * /N162 * /N163 * /N164
	+ /N157 * N158 * /N159 * /N160 * /N163 * /N164
	+ N157 * N158 * /N161 * N159 * /N160 * /N163 * 
	/N164
	+ N157 * N161 * N159 * N162 * N160 * /N163 * 
	/N164
	+ /N157 * N158 * /N161 * N159 * N160 * /N163 * 
	/N164
;Imported pterms FB2_18
	+ N158 * N161 * /N162 * /N160 * /N163 * /N164
	+ N157 * /N158 * /N161 * N159 * N162 * /N163 * 
	/N164
	+ N157 * /N161 * /N159 * /N162 * /N160 * /N163 * 
	/N164
	+ /N157 * /N158 * N161 * N159 * /N162 * N160 * 
	/N163 * /N164
	+ /N157 * /N158 * N161 * /N159 * N162 * N160 * 
	/N163 * /N164
;Imported pterms FB2_1
	+ /N157 * /N158 * /N161 * /N159 * /N162 * /N160 * 
	N163 * /N164
    "ad<15>".CLKF  =  rd
    "ad<15>".TRST  =  /rd * /romcs
    "ad<15>".PRLD  =  GND    

 "ad<1>"  :=  /N157 * N159 * N162 * /N160 * /N163 * /N164
	+ N157 * N161 * /N159 * /N162 * N160 * /N163 * 
	/N164
;Imported pterms FB2_9
	+ /N157 * /N161 * N159 * /N160 * /N163 * /N164
	+ N157 * /N158 * N161 * /N162 * N160 * /N163 * 
	/N164
	+ N157 * /N161 * /N159 * /N162 * /N160 * /N163 * 
	/N164
	+ N158 * /N161 * N159 * N162 * /N160 * /N163 * 
	/N164
	+ /N158 * /N161 * /N159 * /N162 * N160 * /N163 * 
	/N164
;Imported pterms FB2_10
	+ /N157 * N158 * /N161 * /N159 * /N162 * /N160 * 
	/N164
	+ /N157 * /N158 * /N159 * N162 * N160 * /N163 * 
	/N164
	+ N158 * /N161 * /N159 * N162 * N160 * /N163 * 
	/N164
	+ /N158 * N161 * N159 * N162 * /N160 * /N163 * 
	/N164
	+ N157 * N158 * N161 * N159 * N162 * N160 * 
	/N163 * /N164
;Imported pterms FB2_11
	+ N157 * N158 * N161 * /N159 * N162 * /N160 * 
	/N163 * /N164
    "ad<1>".CLKF  =  rd
    "ad<1>".TRST  =  /rd * /romcs
    "ad<1>".PRLD  =  GND    

 "ad<2>"  :=  N157 * /N161 * /N162 * /N160 * /N163 * /N164
	+ N157 * /N158 * /N161 * /N159 * N160 * /N163 * 
	/N164
	+ /N157 * N158 * /N161 * /N159 * N162 * /N163 * 
	/N164
;Imported pterms FB3_14
	+ /N157 * N158 * N159 * N162 * /N160 * /N163 * 
	/N164
	+ /N157 * /N158 * N159 * /N162 * /N160 * /N163 * 
	/N164
;Imported pterms FB3_16
	+ N157 * N158 * N161 * /N159 * N162 * /N160 * 
	/N163 * /N164
	+ N157 * /N158 * N161 * N159 * N162 * N160 * 
	/N163 * /N164
	+ /N157 * N158 * N161 * /N159 * /N162 * /N160 * 
	/N163 * /N164
	+ /N157 * N158 * /N161 * N159 * /N162 * N160 * 
	/N163 * /N164
	+ /N157 * N158 * /N161 * /N159 * /N162 * /N160 * 
	N163 * /N164
    "ad<2>".CLKF  =  rd
    "ad<2>".TRST  =  /rd * /romcs
    "ad<2>".PRLD  =  GND    

 "ad<3>"  :=  N158 * /N161 * N159 * /N160 * /N163 * /N164
	+ N157 * N161 * /N159 * /N162 * N160 * /N163 * 
	/N164
;Imported pterms FB2_12
	+ N157 * N158 * /N161 * /N162 * /N160 * /N163 * 
	/N164
	+ N157 * /N158 * /N161 * /N159 * /N162 * /N163 * 
	/N164
	+ /N157 * N158 * N159 * /N162 * N160 * /N163 * 
	/N164
	+ /N157 * /N161 * N159 * /N162 * /N160 * /N163 * 
	/N164
	+ N158 * N161 * N159 * /N162 * N160 * /N163 * 
	/N164
;Imported pterms FB2_13
	+ N157 * /N158 * N161 * N159 * N162 * /N163 * 
	/N164
	+ N157 * /N158 * N159 * N162 * N160 * /N163 * 
	/N164
	+ /N157 * N158 * N161 * /N159 * N162 * /N163 * 
	/N164
	+ N158 * N161 * /N159 * N162 * /N160 * /N163 * 
	/N164
	+ /N157 * N158 * /N161 * /N159 * /N162 * /N160 * 
	N163 * /N164
;Imported pterms FB2_14
	+ /N157 * /N158 * /N161 * /N159 * N162 * N160 * 
	/N163 * /N164
    "ad<3>".CLKF  =  rd
    "ad<3>".TRST  =  /rd * /romcs
    "ad<3>".PRLD  =  GND    

 "ad<4>"  :=  /N157 * /N158 * /N161 * N162 * /N160 * /N163 * 
	/N164
	+ N158 * /N161 * /N159 * /N162 * /N160 * N163 * 
	/N164
;Imported pterms FB3_18
	+ N158 * N161 * /N162 * N160 * /N163 * /N164
	+ N157 * N158 * /N161 * N159 * N162 * /N163 * 
	/N164
	+ N157 * /N158 * N161 * /N159 * /N162 * /N163 * 
	/N164
	+ /N157 * N158 * N159 * N162 * /N160 * /N163 * 
	/N164
	+ /N157 * N158 * N159 * /N162 * N160 * /N163 * 
	/N164
;Imported pterms FB3_1
	+ N157 * /N159 * /N162 * N160 * /N163 * /N164
	+ N157 * N158 * /N161 * N159 * /N160 * /N163 * 
	/N164
	+ N157 * /N158 * N161 * N159 * N160 * /N163 * 
	/N164
	+ /N157 * N158 * /N161 * /N159 * /N162 * /N160 * 
	/N164
	+ N158 * N161 * /N159 * N162 * /N160 * /N163 * 
	/N164
;Imported pterms FB3_2
	+ /N157 * N158 * /N161 * /N159 * N162 * N160 * 
	/N163 * /N164
    "ad<4>".CLKF  =  rd
    "ad<4>".TRST  =  /rd * /romcs
    "ad<4>".PRLD  =  GND    

 "ad<5>"  :=  /N157 * /N161 * N159 * /N162 * N160 * /N163 * 
	/N164
	+ N158 * /N161 * N159 * N162 * /N160 * /N163 * 
	/N164
;Imported pterms FB1_7
	+ N157 * /N158 * N161 * N160 * /N163 * /N164
	+ /N157 * /N161 * /N159 * N162 * /N163 * /N164
	+ N157 * /N158 * /N159 * /N162 * N160 * /N163 * 
	/N164
	+ N157 * N161 * N159 * /N162 * N160 * /N163 * 
	/N164
	+ N157 * N161 * /N159 * N162 * N160 * /N163 * 
	/N164
;Imported pterms FB1_8
	+ /N157 * N158 * N161 * /N162 * /N160 * /N163 * 
	/N164
	+ /N157 * N158 * /N159 * /N162 * N160 * /N163 * 
	/N164
	+ N158 * N161 * /N159 * N162 * /N160 * /N163 * 
	/N164
	+ /N158 * N161 * N159 * N162 * /N160 * /N163 * 
	/N164
	+ /N158 * N161 * /N159 * /N162 * /N160 * /N163 * 
	/N164
;Imported pterms FB1_9
	+ N157 * N158 * /N161 * /N159 * /N162 * /N160 * 
	/N163 * /N164
	+ /N157 * N158 * N161 * N159 * N162 * N160 * 
	/N163 * /N164
	+ /N157 * N158 * /N161 * /N159 * /N162 * /N160 * 
	N163 * /N164
    "ad<5>".CLKF  =  rd
    "ad<5>".TRST  =  /rd * /romcs
    "ad<5>".PRLD  =  GND    

 "ad<6>"  :=  N157 * /N158 * /N159 * /N162 * N160 * /N163 * 
	/N164
	+ N158 * /N161 * /N159 * /N162 * /N160 * N163 * 
	/N164
;Imported pterms FB3_3
	+ N157 * /N161 * /N159 * /N162 * N160 * /N163 * 
	/N164
	+ /N157 * N158 * /N161 * /N162 * N160 * /N163 * 
	/N164
	+ /N157 * /N161 * /N159 * N162 * /N160 * /N163 * 
	/N164
	+ /N157 * /N161 * /N159 * /N162 * /N160 * N163 * 
	/N164
	+ N158 * /N161 * N159 * N162 * /N160 * /N163 * 
	/N164
;Imported pterms FB3_4
	+ /N157 * N158 * /N159 * /N162 * N160 * /N163 * 
	/N164
	+ N158 * N161 * /N159 * N162 * /N160 * /N163 * 
	/N164
	+ N157 * N158 * N161 * N159 * /N162 * N160 * 
	/N163 * /N164
	+ N157 * /N158 * N161 * N159 * N162 * N160 * 
	/N163 * /N164
	+ /N157 * /N158 * N161 * N159 * N162 * /N160 * 
	/N163 * /N164
;Imported pterms FB3_5
	+ /N157 * /N158 * N161 * /N159 * /N162 * /N160 * 
	/N163 * /N164
    "ad<6>".CLKF  =  rd
    "ad<6>".TRST  =  /rd * /romcs
    "ad<6>".PRLD  =  GND    

 "ad<7>"  :=  N157 * /N158 * /N159 * /N162 * N160 * /N163 * 
	/N164
	+ /N157 * /N161 * /N159 * N162 * /N160 * /N163 * 
	/N164
	+ N158 * N161 * N159 * /N162 * N160 * /N163 * 
	/N164
;Imported pterms FB3_9
	+ /N157 * N158 * N162 * /N160 * /N163 * /N164
	+ /N157 * N158 * N161 * N159 * N160 * /N163 * 
	/N164
	+ /N157 * N158 * N159 * /N162 * N160 * /N163 * 
	/N164
	+ N158 * N161 * /N159 * N162 * /N160 * /N163 * 
	/N164
	+ N158 * /N161 * N159 * N162 * /N160 * /N163 * 
	/N164
;Imported pterms FB3_10
	+ N157 * /N158 * N161 * N159 * N160 * /N163 * 
	/N164
	+ N157 * /N158 * /N161 * /N159 * /N162 * /N163 * 
	/N164
	+ /N157 * N158 * /N161 * /N159 * /N162 * /N160 * 
	N163 * /N164
    "ad<7>".CLKF  =  rd
    "ad<7>".TRST  =  /rd * /romcs
    "ad<7>".PRLD  =  GND    

 "ad<8>"  :=  ;Imported pterms FB1_10
	  N157 * N158 * /N161 * /N159 * /N162 * /N160 * 
	/N164
	+ /N157 * N158 * /N161 * N159 * /N162 * /N163 * 
	/N164
	+ /N157 * N158 * /N159 * N162 * /N160 * /N163 * 
	/N164
	+ /N157 * /N158 * N161 * N162 * N160 * /N163 * 
	/N164
	+ /N158 * N161 * /N159 * /N162 * N160 * /N163 * 
	/N164
;Imported pterms FB1_11
	+ N157 * N158 * N161 * N159 * N160 * /N163 * 
	/N164
	+ N157 * N161 * N159 * N162 * N160 * /N163 * 
	/N164
	+ /N157 * N158 * N161 * /N159 * N162 * /N163 * 
	/N164
	+ N158 * N161 * /N159 * N162 * /N160 * /N163 * 
	/N164
	+ N158 * /N161 * /N159 * /N162 * /N160 * /N163 * 
	/N164
;Imported pterms FB1_12
	+ /N157 * /N158 * /N159 * /N162 * N160 * /N163 * 
	/N164
	+ /N158 * /N161 * /N159 * /N162 * /N160 * N163 * 
	/N164
	+ N157 * N158 * /N161 * N159 * N162 * /N160 * 
	/N163 * /N164
	+ N157 * /N158 * /N161 * /N159 * N162 * /N160 * 
	/N163 * /N164
	+ /N157 * /N158 * N161 * N159 * /N162 * /N160 * 
	/N163 * /N164
    "ad<8>".CLKF  =  rd
    "ad<8>".TRST  =  /rd * /romcs
    "ad<8>".PRLD  =  GND    

 "ad<9>"  :=  /N161 * /N159 * N162 * N160 * /N163 * /N164
	+ N157 * N161 * /N159 * N162 * /N160 * /N163 * 
	/N164
	+ N157 * /N161 * N159 * /N162 * /N160 * /N163 * 
	/N164
;Imported pterms FB2_3
	+ N157 * N158 * /N161 * /N159 * N160 * /N163 * 
	/N164
	+ N157 * /N158 * N161 * N162 * /N160 * /N163 * 
	/N164
	+ N157 * /N158 * /N161 * N159 * /N162 * /N163 * 
	/N164
	+ N157 * /N158 * /N161 * /N159 * /N160 * /N163 * 
	/N164
	+ /N157 * /N158 * /N159 * /N162 * N160 * /N163 * 
	/N164
;Imported pterms FB2_4
	+ /N158 * N161 * /N159 * N162 * /N160 * /N163 * 
	/N164
	+ N157 * N158 * /N161 * /N159 * /N162 * /N160 * 
	N163 * /N164
	+ /N157 * N158 * N161 * N159 * N162 * /N160 * 
	/N163 * /N164
	+ /N157 * N158 * N161 * N159 * /N162 * N160 * 
	/N163 * /N164
	+ /N157 * N158 * /N161 * /N159 * /N162 * /N160 * 
	/N163 * /N164
;Imported pterms FB2_5
	+ /N157 * /N158 * N161 * N159 * /N162 * /N160 * 
	/N163 * /N164
    "ad<9>".CLKF  =  rd
    "ad<9>".TRST  =  /rd * /romcs
    "ad<9>".PRLD  =  GND    

****************************  Device Pin Out ****************************

Device : XC9572XL-5-PC44


                              m           
                     m  a  a  m           
            a     a  m  d  d  c        a  
            d     d  c  <  <  _  d     d  
         T  <     <  _  1  1  o  <  V  <  
         I  8  w  5  c  3  5  u  7  C  3  
         E  >  r  >  s  >  >  t  >  C  >  
         --------------------------------  
        /6  5  4  3  2  1  44 43 42 41 40 \
ad<10> | 7                             39 | romcs
mmc_in | 8                             38 | ad<1>
ad<12> | 9                             37 | rd
   GND | 10                            36 | ad<0>
 ad<6> | 11        XC9572XL-5-PC44     35 | ad<9>
ad<14> | 12                            34 | d<6>
 ad<7> | 13                            33 | d<5>
   TIE | 14                            32 | VCC
   TDI | 15                            31 | GND
   TMS | 16                            30 | TDO
   TCK | 17                            29 | d<4>
       \ 18 19 20 21 22 23 24 25 26 27 28 /
         --------------------------------  
         a  r  a  V  a  G  m  d  d  d  d  
         d  a  d  C  d  N  m  <  <  <  <  
         <  m  <  C  <  D  c  0  1  2  3  
         1  c  2     4     _  >  >  >  >  
         1  s  >     >     c              
         >                 l              
                           k              


Legend :  NC  = Not Connected, unbonded pin
         TIE  = Tie pin to GND or board trace driven to valid logic level
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
         PE   = Port Enable pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XC9572XL-5-PC44
Use Timing Constraints                      : ON
Use Design Location Constraints             : ON
Create Programmable Ground Pins             : OFF
Use Advanced Fitting                        : ON
Use Local Feedback                          : OFF
Use Pin Feedback                            : OFF
Default Power Setting                       : STD
Default Output Slew Rate                    : FAST
Multi Level Logic Optimization              : ON
Timing Optimization                         : ON
Power/Slew Optimization                     : OFF
High Fitting Effort                         : ON
Automatic Wire-ANDing                       : OFF
Xor Synthesis                               : ON
D/T Synthesis                               : ON
Use Boolean Minimization                    : ON
Global Clock(GCK) Optimization              : ON
Global Set/Reset(GSR) Optimization          : ON
Global Output Enable(GTS) Optimization      : ON
Collapsing pterm limit                      : 25
Collapsing input limit                      : 54
