Synthesis and Ngdbuild Report synthesis: version Diamond_1.4_Production (87) Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Sun Jun 10 22:10:57 2012 Command Line: synthesis -f qfn32samples_rom128_lattice.synproj -- all messages logged in file synthesis.log Synthesis Options INFO: Synthesis Options: (LSE-1022) INFO: -a option is = MachXO2 INFO: -s option is = 4 INFO: -t option is = QFN32 INFO: -d option is = LCMXO2-256HC INFO: Using package QFN32 INFO: Using performance grade 4 INFO: INFO: ########################################################## INFO: ### Lattice Family : MachXO2 INFO: ### Device : LCMXO2-256HC INFO: ### Package : QFN32 INFO: ### Speed : 4 INFO: ########################################################## INFO: INFO: Optimization Goal = Area INFO: -top option is not used WARNING: Ignoring Frequency option in Area Mode, Setting to default frequency of 1.0 MHz INFO: Target Frequency = 1.000000 MHz INFO: Max Fanout = 1000 INFO: Timing Path count = 3 INFO: bram Utilization = 100.000000 % INFO: dsp usage = TRUE (default) INFO: dsp utilization = 100 (default) INFO: fsm_encoding_style = auto INFO: Mux style = Auto INFO: Use Carry Chain = TRUE INFO: carry_chain_length = 0 INFO: Use IO Insertion = TRUE INFO: Use IO Reg = TRUE INFO: Resource Sharing = TRUE INFO: Propagate Constants = TRUE INFO: Remove Duplicate Registers = TRUE INFO: force_gsr = auto INFO: ROM style = auto INFO: RAM style = auto INFO: -comp option is FALSE INFO: -syn option is FALSE INFO: -p C:/Documents and Settings/suz/My Documents/lattice/xo2qfn (searchpath added) INFO: -p C:/lscc/diamond/1.4/ispfpga/xo2c00/data (searchpath added) INFO: -p C:/Documents and Settings/suz/My Documents/lattice/xo2qfn/rom128 (searchpath added) INFO: -p C:/Documents and Settings/suz/My Documents/lattice/xo2qfn (searchpath added) INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/lattice/xo2qfn/src/rom128.v INFO: Ngd file = qfn32samples_rom128.ngd INFO: -sdc option: sdc file input not used INFO: -lpf option: output file option is OFF INFO: hardtimer checking is enabled (default); -dt option not used INFO: -r option is OFF [ Remove LOC Properties is OFF ] -- Technology check ok...MachXO, MachXO2... INFO: The default vhdl library search path is now "c:/lscc/diamond/1.4/cae_library/vhdl_packages/vdbs" (VHDL-1504) INFO: * compile design * Compile Design INFO: Compile Design Begin c:/documents and settings/suz/my documents/lattice/xo2qfn/src/rom128.v(45): INFO: compiling module rom128 (VERI-1018) c:/documents and settings/suz/my documents/lattice/xo2qfn/src/rom128.v(61): INFO: compiling module sram(SIZE=128) (VERI-1018) INFO: ######## Found 1 RAM Nets in design (LSE-1115) INFO: ######## Mapping RAM Net \sram_impl/mem to 16 Distributed blocks in SINGLE_PORT Mode INFO: GSR Instance connected to net: n206 (LSE-1148) INFO: GSR will not be inferred since no asynchronous signal was found in netlist (LSE-1147) WARNING: No lpf file will be written because -lpf option is not used or set to 0 INFO: Applying 1.000000 MHz constraint to all clocks (LSE-5000) INFO: Results of ngd drc checks are available in rom128_drc.log INFO: All blocks are expanded and NGD expansion is successful INFO: Writing ngd file qfn32samples_rom128.ngd ################### Begin Area Report (rom128)###################### Number of register bits => 0 of 1090 (0 % ) BB => 8 GSR => 1 IB => 8 LUT4 => 8 MUX81 => 8 SPR16X4C => 16 ################### End Area Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : VCC_net, loads : 16 Clock Enable Nets Number of Clock Enables: 0 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : A_c_6, loads : 16 Net : A_c_5, loads : 16 Net : A_c_4, loads : 16 Net : A_c_3, loads : 16 Net : A_c_2, loads : 16 Net : A_c_1, loads : 16 Net : A_c_0, loads : 16 Net : OE_c, loads : 8 Net : D_out_7, loads : 8 Net : D_out_6, loads : 8 ################### End Clock Report ################## Peak Memory Usage: 39.480 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 2.453 secs --------------------------------------------------------------