Synthesis and Ngdbuild  Report
#Build: Synplify Pro F-2011.09L, Build 022R, Oct 19 2011
#install: C:\lscc\diamond\1.4\synpbase
#OS: Windows XP 5.1
#Hostname: BANDIT

$ Start of Compile
#Sat Jun 09 17:27:42 2012

Synopsys Verilog Compiler, version comp560rcp1, Build 045R, built Oct 18 2011
@N|Running in 32-bit mode
Copyright (C) 1994-2011 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@I::"C:\lscc\diamond\1.4\synpbase\lib\lucent\machxo2.v"
@I::"C:\lscc\diamond\1.4\synpbase\lib\vlog\scemi_objects.v"
@I::"C:\lscc\diamond\1.4\synpbase\lib\vlog\hypermods.v"
@I::"C:\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo2.v"
@I::"C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\alu281\source\SN74281.v"
Verilog syntax check successful!
Selecting top level module SN74281
@N: CG364 :"C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\alu281\source\SN74281.v":103:7:103:15|Synthesizing module alu_74281

	ALU_WIDTH=32'b00000000000000000000000000000100
   Generated name = alu_74281_4s

@N: CG364 :"C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\alu281\source\SN74281.v":203:7:203:15|Synthesizing module acc_74281

	ALU_WIDTH=32'b00000000000000000000000000000100
   Generated name = acc_74281_4s

@N: CG179 :"C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\alu281\source\SN74281.v":232:4:232:6|Removing redundant assignment
@W: CG532 :"C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\alu281\source\SN74281.v":235:4:235:10|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
@N: CG364 :"C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\alu281\source\SN74281.v":39:7:39:13|Synthesizing module SN74281

@END
Premap Report (contents appended below)
@N:"C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\alu281\synlog\qfn32samples_alu281_premap.srr"
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 239R, Built Oct 19 2011 10:56:21
Copyright (C) 1994-2011, Synopsys Inc.  All Rights Reserved
Product Version F-2011.09L

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled 
@N: MF546 |Generated clock conversion enabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

syn_allowed_resources : blockrams=0  set on top level netlist SN74281

Finished Pre Mapping Phase. (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 77MB)

Pre Mapping successful!

At Mapper Exit (Time elapsed 0h:00m:01s; Memory used current: 42MB peak: 77MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Jun 09 17:27:46 2012

###########################################################]
Map & Optimize Report (contents appended below)
@N:"C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\alu281\synlog\qfn32samples_alu281_fpga_mapper.srr"
Synopsys Lattice Technology Mapper, Version maplat, Build 239R, Built Oct 19 2011 10:56:21
Copyright (C) 1994-2011, Synopsys Inc.  All Rights Reserved
Product Version F-2011.09L

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled 
@N: MF546 |Generated clock conversion enabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF203 |Set autoconstraint_io 


Starting Optimization and Mapping (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 76MB)


Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 76MB)


Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 76MB)



#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[

======================================================================================
                                Instance:Pin        Generated Clock Optimization Status
======================================================================================


##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]


Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 76MB)



Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 76MB)


Starting Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 76MB)


Finished Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 76MB)


Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 76MB)


Finished preparing to map (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 76MB)


Finished technology mapping (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 76MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 76MB)

@N: FX164 |The option to pack flops in the IOB has not been specified 

Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 76MB)

Writing Analyst data base C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\alu281\qfn32samples_alu281.srm

Finished Writing Netlist Databases (Time elapsed 0h:00m:03s; Memory used current: 75MB peak: 76MB)

Writing EDIF Netlist and constraint files
F-2011.09L

Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:05s; Memory used current: 79MB peak: 80MB)


Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:05s; Memory used current: 79MB peak: 80MB)

@N: MF276 |Gated clock conversion enabled, but no gated clocks found in design 

Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:05s; Memory used current: 79MB peak: 80MB)


Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:05s; Memory used current: 79MB peak: 80MB)

@N: MF333 |Generated clock conversion enabled, but no generated clocks found in design 

Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:05s; Memory used current: 79MB peak: 80MB)

@W: MT420 |Found inferred clock SN74281|CP with period 1000.00ns. Please declare a user-defined clock on object "p:CP"



##### START OF TIMING REPORT #####[
# Timing Report written on Sat Jun 09 17:27:53 2012
#


Top view:               SN74281
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.


Performance Summary 
*******************


Worst slack in design: 987.457

                   Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack       Type         Group              
-----------------------------------------------------------------------------------------------------------------------
SN74281|CP         1.0 MHz       122.3 MHz     1000.000      8.177         991.823     inferred     Inferred_clkgroup_0
System             1.0 MHz       79.7 MHz      1000.000      12.543        987.457     system       system_clkgroup    
=======================================================================================================================





Clock Relationships
*******************

Clocks                  |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------
Starting    Ending      |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------
System      System      |  1000.000    987.457  |  No paths    -      |  No paths    -      |  No paths    -    
System      SN74281|CP  |  1000.000    990.684  |  No paths    -      |  No paths    -      |  No paths    -    
SN74281|CP  System      |  1000.000    988.597  |  No paths    -      |  No paths    -      |  No paths    -    
SN74281|CP  SN74281|CP  |  1000.000    991.824  |  No paths    -      |  No paths    -      |  No paths    -    
================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port      Starting            User           Arrival     Required          
Name      Reference           Constraint     Time        Time         Slack
          Clock                                                            
---------------------------------------------------------------------------
AS[0]     System (rising)     NA             0.000       987.457           
AS[1]     System (rising)     NA             0.000       987.469           
AS[2]     System (rising)     NA             0.000       987.679           
A[0]      System (rising)     NA             0.000       987.589           
A[1]      System (rising)     NA             0.000       987.946           
A[2]      System (rising)     NA             0.000       987.946           
A[3]      System (rising)     NA             0.000       988.792           
CP        NA                  NA             NA          NA           NA   
C_IN      System (rising)     NA             0.000       988.924           
M         System (rising)     NA             0.000       990.545           
RC        System (rising)     NA             0.000       992.943           
RS[0]     System (rising)     NA             0.000       992.761           
RS[1]     System (rising)     NA             0.000       992.761           
SIO0      System (rising)     NA             0.000       997.044           
SIO3      System (rising)     NA             0.000       997.820           
===========================================================================


Output Ports: 

Port      Starting            User           Arrival     Required          
Name      Reference           Constraint     Time        Time         Slack
          Clock                                                            
---------------------------------------------------------------------------
C_OUT     System (rising)     NA             11.136      1000.000          
F[0]      System (rising)     NA             10.323      1000.000          
F[1]      System (rising)     NA             11.383      1000.000          
F[2]      System (rising)     NA             11.415      1000.000          
F[3]      System (rising)     NA             11.526      1000.000          
SIO0      System (rising)     NA             10.323      1000.000          
SIO3      System (rising)     NA             12.543      1000.000          
===========================================================================


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report
Part: lcmxo2_256hc-4

Register bits: 4 of 256 (2%)
PIC Latch:       0
I/O cells:       20


Details:
BB:             2
CCU2D:          3
FD1P3AX:        4
GSR:            1
IB:             13
OB:             5
ORCALUT4:       43
PFUMX:          8
PUR:            1
VHI:            1
VLO:            1
false:          3
true:           3
Mapper successful!

At Mapper Exit (Time elapsed 0h:00m:06s; Memory used current: 24MB peak: 80MB)

Process took 0h:00m:06s realtime, 0h:00m:06s cputime
# Sat Jun 09 17:27:53 2012

###########################################################]