Lattice Mapping Report File for Design Module 'alu281' Design Information Command line: map -a MachXO2 -p LCMXO2-256HC -t QFN32 -s 4 -oc Commercial qfn32samples_alu281.ngd -o qfn32samples_alu281_map.ncd -pr qfn32samples_alu281.prf -mp qfn32samples_alu281.mrp C:/Documents and Settings/suz/My Documents/lattice/xo2qfn/src/alu281.lpf -c 0 Target Vendor: LATTICE Target Device: LCMXO2-256HCQFN32 Target Performance: 4 Mapper: xo2c00, version: Diamond_1.4_Production (87) Mapped on: 06/10/12 21:53:21 Design Summary Number of registers: 4 PFU registers: 4 PIO registers: 0 Number of SLICEs: 39 out of 128 (30%) SLICEs(logic/ROM): 32 out of 32 (100%) SLICEs(logic/ROM/RAM): 7 out of 96 (7%) As RAM: 0 out of 96 (0%) As Logic/ROM: 7 out of 96 (7%) Number of logic LUT4s: 78 Number of distributed RAM: 0 (0 LUT4s) Number of ripple logic: 0 (0 LUT4s) Number of shift registers: 0 Total number of LUT4s: 78 Number of PIO sites used: 20 out of 22 (91%) Number of block RAMs: 0 out of 0 Number of GSRs: 0 out of 1 (0%) EFB used : No JTAG used : No Readback used : No Oscillator used : No Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 1 Net CP_c: 4 loads, 4 rising, 0 falling (Driver: PIO CP ) Number of Clock Enables: 2 Net ALU/n320: 3 loads, 3 LSLICEs Net ALU/n5: 1 loads, 1 LSLICEs Number of LSRs: 0 Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net M_c: 16 loads Net AS_c_0: 12 loads Net AS_c_2: 12 loads Net AS_c_1: 11 loads Net ALU/n94_adj_1: 10 loads Net RS_c_1: 10 loads Net A_c_0: 9 loads Net n5: 9 loads Net ALU/B_0: 8 loads Net ALU/B_2: 8 loads Number of warnings: 2 Number of errors: 0 Design Errors/Warnings WARNING: The JTAG port has been disabled in this project and JTAG pins will be configured as General Purpose IO. You have to use JTAGENB pin in hardware to change the personality of the port from JTAG pins to general purpose IO. Reference MACHXO2 Handbook for details on dual function JTAG port. WARNING: All configuration ports of the design have been disabled. Reference MachXO2 Handbook for information on the Configuration Ports of MachXO2 IO (PIO) Attributes +---------------------+-----------+-----------+------------+ | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | +---------------------+-----------+-----------+------------+ | A_0 | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | F_0 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | F_1 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | A_1 | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | A_2 | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | A_3 | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | C_IN | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | F_2 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | F_3 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | CP | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | RC | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | RS_0 | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | RS_1 | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | AS_0 | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | SIO0 | BIDIR | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | SIO3 | BIDIR | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | AS_1 | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | AS_2 | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | M | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | C_OUT | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ Removed logic Block i2 undriven or does not drive anything - clipped. Block GSR_INST undriven or does not drive anything - clipped. Signal GND_net undriven or does not drive anything - clipped. Signal VCC_net undriven or does not drive anything - clipped. Block i1 was optimized away. Memory Usage Run Time and Memory Usage ------------------------- Total CPU Time: 1 secs Total REAL Time: 2 secs Peak Memory Usage: 25 MB Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.