PAR: Place And Route Diamond_1.4_Production (87).
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.
Sun Jun 10 21:53:23 2012

C:/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_alu281.p2t
qfn32samples_alu281_map.ncd qfn32samples_alu281.dir qfn32samples_alu281.prf

Preference file: qfn32samples_alu281.prf.

Cost Table Summary
Level/      Number      Timing      Run         NCD
Cost [ncd]  Unrouted    Score       Time        Status
----------  --------    --------    -----       ------------
5_1   *     0           0           22          Complete        


* : Design saved.

par done!

Lattice Place and Route Report for Design "qfn32samples_alu281_map.ncd"
Sun Jun 10 21:53:23 2012


Best Par Run
PAR: Place And Route Diamond_1.4_Production (87).
Command Line: C:/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_alu281.p2t
qfn32samples_alu281_map.ncd qfn32samples_alu281.dir qfn32samples_alu281.prf
Preference file: qfn32samples_alu281.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file qfn32samples_alu281_map.ncd.
Design name: alu281
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-256HC
Package:     QFN32
Performance: 4
Loading device for application par from file 'xo2c256.nph' in environment: C:/lscc/diamond/1.4/ispfpga.
Package Status:                     Advanced       Version 1.34
Performance Hardware Data Status:   Final)         Version 22.4
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)      20/56           35% used
                     20/22           90% bonded

   SLICE             39/128          30% used



Number of Signals: 97
Number of Connections: 305
WARNING - par: The JTAG Port has been disabled in this project and JTAG pins will be configured as General Purpose IO.  You have to use JTAGENB pin in hardware to change the personality of the port from JTAG pins to general purpose IO.  This mux control pin is dedicated to selection of JTAG pins for GPIO use by user design.  Reference MachXO2 Handbook for details on dual-function JTAG port.

Pin Constraint Summary:
   20 out of 20 pins locked (100% locked).

No signal is selected as primary clock.


No signal is selected as secondary clock.

No signal is selected as Global Set/Reset.
Starting Placer Phase 0.

Finished Placer Phase 0.  REAL time: 3 secs 

Starting Placer Phase 1.
..................
Placer score = 12373.
Finished Placer Phase 1.  REAL time: 19 secs 

Starting Placer Phase 2.
.
Placer score =  12373
Finished Placer Phase 2.  REAL time: 19 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 0 out of 8 (0%)
  DCM        : 0 out of 2 (0%)
  DCC        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:

  PRIMARY  : 0 out of 8 (0%)
  SECONDARY: 0 out of 8 (0%)




I/O Usage Summary (final):
   20 out of 56 (35.7%) PIO sites used.
   20 out of 22 (90.9%) bonded PIO sites used.
   Number of PIO comps: 20; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
+----------+--------------+------------+-----------+
| I/O Bank | Usage        | Bank Vccio | Bank Vref |
+----------+--------------+------------+-----------+
| 0        | 8 / 9 ( 88%) | 2.5V       | -         |
| 1        | 2 / 2 (100%) | 2.5V       | -         |
| 2        | 9 / 9 (100%) | 2.5V       | -         |
| 3        | 1 / 2 ( 50%) | 2.5V       | -         |
+----------+--------------+------------+-----------+

Total placer CPU time: 18 secs 

Dumping design to file qfn32samples_alu281.dir/5_1.ncd.

0 connections routed; 305 unrouted.
Starting router resource preassignment

WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
   Signal=CP_c loads=4 clock_loads=4

Completed router resource preassignment. Real time: 20 secs 
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
305 successful; 0 unrouted; (0) real time: 21 secs 
Dumping design to file qfn32samples_alu281.dir/5_1.ncd.
Total CPU time 19 secs 
Total REAL time: 21 secs 
Completely routed.
End of route.  305 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.

Timing score: 0 

Total REAL time to completion: 22 secs 

Dumping design to file qfn32samples_alu281.dir/5_1.ncd.


All signals are completely routed.


par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.