I/O Timing Report WARNING - Source clock net WE_mem is not directly constrained. For this preference to work properly, please make sure the source of this clock is constrained. It appears in MULTICYCLE FROM CLKNET "WE_mem" 6.000000 X ; . Preserving this preference. // Design: mcpu // Package: QFN32 // ncd File: qfn32samples_mcpu3_efb.ncd // Version: Diamond_1.4_Production (87) // Written on Tue Jun 26 06:30:42 2012 // M: Minimum Performance Grade // iotiming qfn32samples_mcpu3_efb.ncd qfn32samples_mcpu3_efb.prf I/O Timing Report (All units are in ns) Worst Case Results across Performance Grades (M, 6, 5, 4): // Input Setup and Hold Times Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- RST CLK_2X R 4.356 4 0.615 4 SDA SCL R 2.243 4 2.099 4 // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ O_PORT_0 RST R 12.529 4 3.245 M O_PORT_1 RST R 12.529 4 3.245 M O_PORT_2 RST R 12.368 4 3.191 M O_PORT_3 RST R 12.368 4 3.191 M O_PORT_4 RST R 12.348 4 3.198 M O_PORT_5 RST R 12.348 4 3.198 M O_PORT_6 RST R 12.348 4 3.198 M O_PORT_7 RST R 12.337 4 3.192 M SDA SCL F 9.560 4 2.432 M // Internal_Clock to Input Port Internal_Clock -------------------------------------------------------- RST master_clk // Internal_Clock to Output Port Internal_Clock -------------------------------------------------------- O_STB master_clk SCL i2c1_sclo SDA i2c1_sclo