Lattice Mapping Report File for Design Module 'mcpu' Design Information Command line: map -a MachXO2 -p LCMXO2-256HC -t QFN32 -s 4 -oc Commercial qfn32samples_mcpu3_efb.ngd -o qfn32samples_mcpu3_efb_map.ncd -pr qfn32samples_mcpu3_efb.prf -mp qfn32samples_mcpu3_efb.mrp Z:/XC2C/xo2qfn-w08/src/mcpu3_efb.lpf -c 0 Target Vendor: LATTICE Target Device: LCMXO2-256HCQFN32 Target Performance: 4 Mapper: xo2c00, version: Diamond_1.4_Production (87) Mapped on: 06/26/12 16:36:25 Design Summary Number of registers: 40 PFU registers: 32 PIO registers: 8 Number of SLICEs: 109 out of 128 (85%) SLICEs(logic/ROM): 32 out of 32 (100%) SLICEs(logic/ROM/RAM): 77 out of 96 (80%) As RAM: 6 out of 96 (6%) As Logic/ROM: 71 out of 96 (74%) Number of logic LUT4s: 197 Number of distributed RAM: 6 (12 LUT4s) Number of ripple logic: 4 (8 LUT4s) Number of shift registers: 0 Total number of LUT4s: 217 Number of PIO sites used: 13 out of 22 (59%) Number of block RAMs: 0 out of 0 Number of GSRs: 1 out of 1 (100%) EFB used : Yes JTAG used : No Readback used : No Oscillator used : No Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 4 Net CLK_2X_c: 8 loads, 8 rising, 0 falling (Driver: PIO CLK_2X ) Net i2c1_scli: 1 loads, 1 rising, 0 falling (Driver: PIO SCL ) Net master_clk: 14 loads, 14 rising, 0 falling (Driver: master_clk_95 ) Net O_STB_c: 8 loads, 8 rising, 0 falling (Driver: i3_4_lut ) Number of Clock Enables: 5 Net n911: 4 loads, 4 LSLICEs Net n1352: 4 loads, 4 LSLICEs Net alu_impl_I/alu_impl/alu_hi/n3747: 1 loads, 1 LSLICEs Net n3021: 1 loads, 1 LSLICEs Net n3743: 1 loads, 1 LSLICEs Number of local set/reset loads for net RST_NEG merged into GSR: 1 Number of LSRs: 4 Net n1423: 2 loads, 2 LSLICEs Net RST_c: 12 loads, 11 LSLICEs Net wb_stat_1: 1 loads, 1 LSLICEs Net n1424: 2 loads, 2 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net pc_2: 68 loads Net pc_3: 68 loads Net pc_1: 67 loads Net pc_4: 61 loads Net pc_5: 31 loads Net pc_0: 29 loads Net inst_1: 19 loads Net inst_2: 19 loads Net int_c_adj_24: 19 loads Net RST_c: 19 loads Number of warnings: 2 Number of errors: 0 Design Errors/Warnings WARNING: logical net 'add_62_1/CI' has no driver WARNING: Using local reset signal 'RST_NEG' to infer global GSR net. IO (PIO) Attributes +---------------------+-----------+-----------+------------+ | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | +---------------------+-----------+-----------+------------+ | SCL | BIDIR | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | SDA | BIDIR | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | RST | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | CLK_2X | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_STB | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_PORT_0 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | O_PORT_1 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | O_PORT_2 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | O_PORT_3 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | O_PORT_4 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | O_PORT_5 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | O_PORT_6 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | O_PORT_7 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ Removed logic Signal n1186 was merged into signal wb_stat_1 Signal GND_net undriven or does not drive anything - clipped. Signal add_62_7/CO undriven or does not drive anything - clipped. Signal add_62_1/S0 undriven or does not drive anything - clipped. Signal add_62_1/CI undriven or does not drive anything - clipped. Block i2709_4_lut_2_lut was optimized away. Block i1 was optimized away. Memory Usage /sram_impl/mem0: EBRs: 0 RAM SLICEs: 3 Logic SLICEs: 0 PFU Registers: 0 /sram_impl/mem1: EBRs: 0 RAM SLICEs: 3 Logic SLICEs: 0 PFU Registers: 0 Embedded Functional Block Connection Summary: --------------------------------------------- Desired WISHBONE clock frequency: 50.0 MHz Clock source: CLK_2X_c Reset source: RST_c Functions mode: I2C #1 (Primary) Function: ENABLED I2C #2 (Secondary) Function: DISABLED SPI Function: DISABLED Timer/Counter Function: ENABLED Timer/Counter Mode: WB UFM Connection: DISABLED PLL0 Connection: DISABLED PLL1 Connection: DISABLED I2C Function Summary: -------------------- I2C Component: PRIMARY I2C Addressing: 7BIT I2C Performance: 400kHz Slave Address: 0b1010001 General Call: DISABLED I2C Wake Up: DISABLED I2C Component: UFM/Configuration I2C Addressing: 7BIT I2C Performance: 400kHz Slave Address: 0b1010000 SPI Function Summary: -------------------- None Timer/Counter Function Summary: ------------------------------ TC_MODE: CTCM TC_SCLK_SEL: Positive Edge TC_CCLK_SEL: 1 GSR: ENABLED TC_TOP_SET: 65535 TC_OCR_SET: 32767 TC_OC_MODE: TOGGLE TC_RESETN: DISABLED TC_TOP_SEL: ON TC_OV_INT: OFF TC_OCR_INT: OFF TC_ICR_INT: OFF TC_OVERFLOW: DISABLED TC_ICAPTURE: DISABLED UFM Function Summary: -------------------- UFM Utilization: General Purpose Flash Memory Available General Purpose Flash Memory: 0 Pages (0*128 Bits) EBR Blocks with Unique Initialization Data: 0 WID EBR Instance --- ------------ ASIC Components --------------- Instance Name: efb_impl/EFBInst_0 Type: EFB GSR Usage --------- GSR Component: The local reset signal 'RST_NEG' of the design has been inferred as Global Set Reset (GSR). The reset signal used for GSR control is 'RST_NEG'. GSR Property: The design components with GSR property set to ENABLED will respond to global set reset while the components with GSR property set to DISABLED will not. Run Time and Memory Usage ------------------------- Total CPU Time: 2 secs Total REAL Time: 21 secs Peak Memory Usage: 26 MB Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.