Synthesis and Ngdbuild  Report
synthesis:  version Diamond_1.4_Production (87) 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp.   All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved. Copyright (c) 2001 Agere Systems   All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.
Tue Jun 26 16:35:36 2012 

Command Line:  synthesis -f qfn32samples_mcpu3_efb_lattice.synproj 

-- all messages logged in file synthesis.log

Synthesis Options

INFO: Synthesis Options: (LSE-1022)
INFO: -a option is = MachXO2
INFO: -s option is = 4
INFO: -t option is = QFN32
INFO: -d option is = LCMXO2-256HC
INFO: Using package QFN32
INFO: Using performance grade 4
INFO:                                                           
INFO: ##########################################################
INFO: ### Lattice Family : MachXO2
INFO: ### Device  : LCMXO2-256HC
INFO: ### Package : QFN32
INFO: ### Speed   : 4
INFO: ##########################################################
INFO:                                                           
INFO: Optimization Goal = Area
INFO: -top option is not used
WARNING: Ignoring Frequency option in Area Mode, Setting to default frequency of 1.0 MHz
INFO: Target Frequency = 1.000000 MHz
INFO: Max Fanout = 1000
INFO: Timing Path count = 3
INFO: bram Utilization = 100.000000 %
INFO: dsp usage = TRUE (default)
INFO: dsp utilization = 100 (default)
INFO: fsm_encoding_style = auto
INFO: Mux style = Auto
INFO: Use Carry Chain = TRUE
INFO: carry_chain_length = 0
INFO: Use IO Insertion = TRUE
INFO: Use IO Reg = TRUE
INFO: Resource Sharing = TRUE
INFO: Propagate Constants = TRUE
INFO: Remove Duplicate Registers = TRUE
INFO: force_gsr = auto
INFO: ROM style = auto
INFO: RAM style = auto
INFO: -comp option is FALSE
INFO: -syn option is FALSE
INFO: -p Z:/XC2C/xo2qfn-w08 (searchpath added)
INFO: -p Y:/Program_Files/lscc/diamond/1.4/ispfpga/xo2c00/data (searchpath added)
INFO: -p Z:/XC2C/xo2qfn-w08/mcpu3_efb (searchpath added)
INFO: -p Z:/XC2C/xo2qfn-w08 (searchpath added)
INFO: Verilog design file = Z:/XC2C/xo2qfn-w08/src/mcpu3_efb.v
INFO: Verilog design file = Z:/XC2C/xo2qfn-w08/src/rtavr_alu2.v
INFO: Verilog design file = Z:/XC2C/xo2qfn-w08/src/alu4.v
INFO: Verilog design file = Z:/XC2C/xo2qfn-w08/src/alu8.v
INFO: Verilog design file = Z:/XC2C/xo2qfn-w08/src/EFB_tc_i2c.v
INFO: Ngd file = qfn32samples_mcpu3_efb.ngd
INFO: -sdc option: sdc file input not used
INFO: -lpf option: output file option is OFF
INFO: hardtimer checking is enabled (default); -dt option not used
INFO: -r option is OFF [ Remove LOC Properties is OFF ]
-- Technology check ok...MachXO, MachXO2...
INFO: The default vhdl library search path is now "y:/program_files/lscc/diamond/1.4/cae_library/vhdl_packages/vdbs" (VHDL-1504)
INFO: * compile design *

Compile Design

INFO: Compile Design Begin
z:/xc2c/xo2qfn-w08/src/mcpu3_efb.v(76): INFO: compiling module mcpu (VERI-1018)
z:/xc2c/xo2qfn-w08/src/efb_tc_i2c.v(8): INFO: compiling module EFB_tc_i2c (VERI-1018)
z:/xc2c/xo2qfn-w08/src/mcpu3_efb.v(305): INFO: compiling module sram (VERI-1018)
z:/xc2c/xo2qfn-w08/src/mcpu3_efb.v(352): INFO: compiling module rom (VERI-1018)
z:/xc2c/xo2qfn-w08/src/rtavr_alu2.v(41): INFO: compiling module rtavr_alu (VERI-1018)
z:/xc2c/xo2qfn-w08/src/alu8.v(54): INFO: compiling module alu8 (VERI-1018)
z:/xc2c/xo2qfn-w08/src/alu4.v(54): INFO: compiling module alu4 (VERI-1018)
z:/xc2c/xo2qfn-w08/src/mcpu3_efb.v(362): WARNING: ram mem_original_ramnet has no write-port on it (VDB-1038)
INFO: ######## Missing driver on net : \efb_impl/tc_ic, patching with GND... (LSE-1017)


INFO: ######## Found 1 RAM Nets in design (LSE-1115)
INFO: ######## Mapping RAM Net \sram_impl/mem to 2 Distributed blocks in SINGLE_PORT Mode
WARNING: Skipping pad insertion on SCL due to black_box_pad_pin attribute (LSE-1155)
WARNING: Skipping pad insertion on SDA due to black_box_pad_pin attribute (LSE-1155)
INFO: GSR Instance connected to net: n1 (LSE-1148)
INFO: GSR will not be inferred since no asynchronous signal was found in netlist (LSE-1147)
WARNING: No lpf file will be written because -lpf option is not used or set to 0
INFO: Applying 1.000000 MHz constraint to all clocks (LSE-5000)
INFO: Results of ngd drc checks are available in mcpu_drc.log
INFO: All blocks are expanded and NGD expansion is successful
INFO: Writing ngd file qfn32samples_mcpu3_efb.ngd

################### Begin Area Report (mcpu)######################
Number of register bits => 40 of 1090 (3 % )
BB => 2
CCU2D => 4
EFB => 1
FD1P3AX => 8
FD1P3IX => 10
FD1S3IX => 13
FD1S3JX => 1
GSR => 1
IB => 2
INV => 2
L6MUX21 => 3
LUT4 => 142
OB => 9
OFS1P3DX => 8
PFUMX => 18
ROM64X1A => 13
SPR16X4C => 2
################### End Area Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 4
  Net : master_clk, loads : 20
  Net : CLK_2X_c, loads : 13
  Net : O_STB_c, loads : 9
  Net : WE_mem, loads : 2
Clock Enable Nets
Number of Clock Enables: 6
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : pc_2, loads : 29
  Net : pc_1, loads : 29
  Net : pc_0, loads : 29
  Net : pc_3, loads : 28
  Net : RST_c, loads : 25
  Net : pc_4, loads : 21
  Net : inst_2, loads : 19
  Net : inst_1, loads : 19
  Net : inst_0, loads : 18
  Net : pc_5, loads : 17
################### End Clock Report ##################

Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk2 [get_nets O_STB_c]                 |            -|            -|     0  
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk1 [get_nets master_clk]              |    1.000 MHz|   36.407 MHz|    18  
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk0 [get_nets CLK_2X_c]                |    1.000 MHz|  180.734 MHz|     3  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.


Peak Memory Usage: 45.246  MB

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Elapsed CPU time for LSE flow : 6.734  secs
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