Synthesis and Ngdbuild Report synthesis: version Diamond_1.4_Production (87) Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Mon Jun 18 11:33:56 2012 Command Line: synthesis -f qfn32samples_jtag_comm_lattice.synproj -- all messages logged in file synthesis.log Synthesis Options INFO: Synthesis Options: (LSE-1022) INFO: -a option is = MachXO2 INFO: -s option is = 4 INFO: -t option is = QFN32 INFO: -d option is = LCMXO2-256HC INFO: Using package QFN32 INFO: Using performance grade 4 INFO: INFO: ########################################################## INFO: ### Lattice Family : MachXO2 INFO: ### Device : LCMXO2-256HC INFO: ### Package : QFN32 INFO: ### Speed : 4 INFO: ########################################################## INFO: INFO: Optimization Goal = Area INFO: -top option is not used WARNING: Ignoring Frequency option in Area Mode, Setting to default frequency of 1.0 MHz INFO: Target Frequency = 1.000000 MHz INFO: Max Fanout = 1000 INFO: Timing Path count = 3 INFO: bram Utilization = 100.000000 % INFO: dsp usage = TRUE (default) INFO: dsp utilization = 100 (default) INFO: fsm_encoding_style = auto INFO: Mux style = Auto INFO: Use Carry Chain = TRUE INFO: carry_chain_length = 0 INFO: Use IO Insertion = TRUE INFO: Use IO Reg = TRUE INFO: Resource Sharing = TRUE INFO: Propagate Constants = TRUE INFO: Remove Duplicate Registers = TRUE INFO: force_gsr = auto INFO: ROM style = auto INFO: RAM style = auto INFO: -comp option is FALSE INFO: -syn option is FALSE INFO: -p Z:/XC2C/xo2qfn (searchpath added) INFO: -p Y:/Program_Files/lscc/diamond/1.4/ispfpga/xo2c00/data (searchpath added) INFO: -p Z:/XC2C/xo2qfn/jtag_comm (searchpath added) INFO: -p Z:/XC2C/xo2qfn (searchpath added) INFO: Verilog design file = Z:/XC2C/xo2qfn/src/jtag_comm.v INFO: Verilog design file = Z:/XC2C/xo2qfn/src/jtag_spi.v INFO: Verilog design file = Z:/XC2C/xo2qfn/src/EFB_tc_i2c.v INFO: Ngd file = qfn32samples_jtag_comm.ngd INFO: -sdc option: sdc file input not used INFO: -lpf option: output file option is OFF INFO: hardtimer checking is enabled (default); -dt option not used INFO: -r option is OFF [ Remove LOC Properties is OFF ] -- Technology check ok...MachXO, MachXO2... INFO: The default vhdl library search path is now "y:/program_files/lscc/diamond/1.4/cae_library/vhdl_packages/vdbs" (VHDL-1504) INFO: * compile design * Compile Design INFO: Compile Design Begin z:/xc2c/xo2qfn/src/jtag_comm.v(5): INFO: compiling module tool_test (VERI-1018) z:/xc2c/xo2qfn/src/jtag_spi.v(63): INFO: compiling module jtag_spi (VERI-1018) z:/xc2c/xo2qfn/src/efb_tc_i2c.v(8): INFO: compiling module EFB_tc_i2c (VERI-1018) INFO: ######## Missing driver on net : SPI_DATA_I[7], patching with GND... (LSE-1017) INFO: ######## Missing driver on net : SPI_DATA_I[6], patching with GND... (LSE-1017) INFO: ######## Missing driver on net : SPI_DATA_I[5], patching with GND... (LSE-1017) INFO: ######## Missing driver on net : SPI_DATA_I[4], patching with GND... (LSE-1017) INFO: ######## Missing driver on net : SPI_DATA_I[3], patching with GND... (LSE-1017) INFO: ######## Missing driver on net : SPI_DATA_I[2], patching with GND... (LSE-1017) INFO: ######## Missing driver on net : SPI_DATA_I[1], patching with GND... (LSE-1017) INFO: ######## Missing driver on net : SPI_DATA_I[0], patching with GND... (LSE-1017) INFO: ######## Missing driver on net : JTDO2, patching with GND... (LSE-1017) INFO: ######## Missing driver on net : \efb_impl/tc_ic, patching with GND... (LSE-1017) INFO: ######## Missing driver on net : n198, patching with GND... (LSE-1017) z:/xc2c/xo2qfn/src/jtag_comm.v(163): WARNING: Bit 0 of Register wb_adr is stuck at Zero (VDB-5010) WARNING: Skipping pad insertion on SDA due to black_box_pad_pin attribute (LSE-1155) WARNING: Skipping pad insertion on SCL due to black_box_pad_pin attribute (LSE-1155) z:/xc2c/xo2qfn/src/jtag_spi.v(127): WARNING: Register \JTAG_SPI/r_spi_out_i0_i0 is stuck at Zero (VDB-5013) INFO: GSR Instance connected to net: \efb_impl/scuba_vlo (LSE-1148) INFO: GSR will not be inferred since no asynchronous signal was found in netlist (LSE-1147) INFO: Duplicate Register/Latch removal : wb_stb_88 is one to one match with wb_cyc_87 WARNING: No lpf file will be written because -lpf option is not used or set to 0 INFO: Applying 1.000000 MHz constraint to all clocks (LSE-5000) INFO: Results of ngd drc checks are available in tool_test_drc.log INFO: All blocks are expanded and NGD expansion is successful INFO: Writing ngd file qfn32samples_jtag_comm.ngd ################### Begin Area Report (tool_test)###################### Number of register bits => 38 of 1090 (3 % ) BB => 2 DCMA => 1 EFB => 1 FD1P3AX => 21 FD1P3IX => 5 FD1P3JX => 1 FD1S3AX => 6 FD1S3IX => 5 GSR => 1 IB => 4 INV => 3 JTAGF => 1 LUT4 => 36 OB => 1 OBZ => 1 OSCH => 1 PFUMX => 1 PUR => 1 ################### End Area Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 2 Net : CLK, loads : 22 Net : n4, loads : 2 Clock Enable Nets Number of Clock Enables: 12 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : r_jtck, loads : 10 Net : r_cs1, loads : 10 Net : wb_stat_1, loads : 8 Net : wb_stat_0, loads : 8 Net : r_sck, loads : 8 Net : n231, loads : 8 Net : n221, loads : 7 Net : RESET, loads : 5 Net : reset_cnt_0, loads : 5 Net : SPI_DATA_REQ, loads : 5 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 1000.000000 -name | | | clk0 [get_nets CLK] | 1.000 MHz| 87.997 MHz| 4 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 39.672 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 3.563 secs --------------------------------------------------------------