I/O Timing Report
// Design: udrv
// Package: QFN32
// ncd File: qfn32samples_udrv.ncd
// Version: Diamond_1.4_Production (87)
// Written on Thu Jul 05 09:59:48 2012
// M: Minimum Performance Grade
// iotiming qfn32samples_udrv.ncd qfn32samples_udrv.prf

I/O Timing Report (All units are in ns)

Worst Case Results across Performance Grades (M, 6, 5, 4):

// Input Setup and Hold Times

Port  Clock  Edge  Setup Performance_Grade  Hold Performance_Grade
----------------------------------------------------------------------
DB_0  CLK_4X F     1.627      4       0.232     6
DB_1  CLK_4X F     1.301      4       0.838     4
DB_2  CLK_4X F     2.719      4       0.189     6
DB_3  CLK_4X F     0.350      4       1.112     4
DB_4  CLK_4X F     1.109      4       0.971     4
DB_5  CLK_4X F     0.361      4       1.503     4
DB_6  CLK_4X F     0.815      4       1.034     4
DB_7  CLK_4X F     0.493      4       1.042     4
DP    CLK_4X R     4.252      4       0.293     4
RS    CLK_4X F    -0.033      4       1.571     4
nCS   CLK_4X F     2.723      4       1.336     4
nRD   CLK_4X F     2.805      4       1.336     4
nWR   CLK_4X F    -0.147      M       1.767     4


// Clock to Output Delay

Port        Clock  Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
------------------------------------------------------------------------
DB_0        CLK_4X F    16.352         4        3.806          M
DB_1        CLK_4X F    16.750         4        3.934          M
DB_2        CLK_4X F    15.414         4        3.563          M
DB_3        CLK_4X F    15.757         4        3.649          M
DB_4        CLK_4X F    14.806         4        3.149          M
DB_5        CLK_4X F    16.738         4        3.567          M
DB_6        CLK_4X F    14.759         4        3.399          M
DB_7        CLK_4X F    14.054         4        3.166          M
nDATA_EMPTY CLK_4X F    15.776         4        3.544          M
nDATA_FULL  CLK_4X F    12.153         4        3.272          M
nDATA_RDY   CLK_4X F    11.889         4        3.180          M


// Internal_Clock to Input

Port  Internal_Clock
--------------------------------------------------------
DB_0  CLK           
DB_1  CLK           
DM    CLK           
DP    CLK           
RS    CLK           
nCS   CLK           
nWR   CLK           


// Internal_Clock to Output

Port       Internal_Clock
--------------------------------------------------------
DB_0       CLK           
DB_1       CLK           
DB_2       CLK           
DB_3       CLK           
DB_4       CLK           
DB_7       CLK           
DM         CLK           
DP         CLK           
nBUSY      CLK           
nCRC_ERROR CLK           
nDATA_RDY  CLK