-------------------------------------------------------------------------------- Lattice TRACE Report - Hold Mon Jun 25 15:00:56 2012 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design file: mcpu Device,speed: LCMXO2-256HC,M Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "CLK" 36.000000 MHz ; 30 items scored, 15 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 3.653ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i5 (from CLK_c +) Destination: FF Data in sram_impl/mem0/RAM0 (to WE_mem +) FF sram_impl/mem0/RAM0 Delay: 0.464ns (28.2% logic, 71.8% route), 2 logic levels. Constraint Details: 0.464ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_12 to SLICE_5 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.988ns skew requirement (totaling 4.117ns) by 3.653ns Physical Path Details: Data path alu_impl_I/alu_impl/alu_hi/SLICE_12 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C7B.CLK to R3C7B.Q1 alu_impl_I/alu_impl/alu_hi/SLICE_12 (from CLK_c) ROUTE 8 0.333 R3C7B.Q1 to R4C5C.B1 akku_5 ZERO_DEL --- 0.000 R4C5C.B1 to R4C5C.WDO1 sram_impl/mem0/SLICE_4 ROUTE 1 0.000 R4C5C.WDO1 to R4C5A.WD1 sram_impl/mem0/WD1_INT (to WE_mem) -------- 0.464 (28.2% logic, 71.8% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_12: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R3C7B.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.151 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 0.826 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.174 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.249 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.267 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.098 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.729 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 0.358 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.174 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 0.788 R5C4A.F0 to R4C5A.WCK WE_mem -------- 5.611 (26.3% logic, 73.7% route), 7 logic levels. Error: The following path exceeds requirements by 3.589ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i4 (from CLK_c +) Destination: FF Data in sram_impl/mem0/RAM0 (to WE_mem +) FF sram_impl/mem0/RAM0 Delay: 0.528ns (24.8% logic, 75.2% route), 2 logic levels. Constraint Details: 0.528ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_12 to SLICE_5 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.988ns skew requirement (totaling 4.117ns) by 3.589ns Physical Path Details: Data path alu_impl_I/alu_impl/alu_hi/SLICE_12 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C7B.CLK to R3C7B.Q0 alu_impl_I/alu_impl/alu_hi/SLICE_12 (from CLK_c) ROUTE 8 0.397 R3C7B.Q0 to R4C5C.A1 akku_4 ZERO_DEL --- 0.000 R4C5C.A1 to R4C5C.WDO0 sram_impl/mem0/SLICE_4 ROUTE 1 0.000 R4C5C.WDO0 to R4C5A.WD0 sram_impl/mem0/WD0_INT (to WE_mem) -------- 0.528 (24.8% logic, 75.2% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_12: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R3C7B.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.151 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 0.826 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.174 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.249 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.267 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.098 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.729 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 0.358 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.174 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 0.788 R5C4A.F0 to R4C5A.WCK WE_mem -------- 5.611 (26.3% logic, 73.7% route), 7 logic levels. Error: The following path exceeds requirements by 3.533ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i7 (from CLK_c +) Destination: FF Data in sram_impl/mem0/RAM1 (to WE_mem +) FF sram_impl/mem0/RAM1 Delay: 0.584ns (22.4% logic, 77.6% route), 2 logic levels. Constraint Details: 0.584ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_14 to SLICE_6 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.988ns skew requirement (totaling 4.117ns) by 3.533ns Physical Path Details: Data path alu_impl_I/alu_impl/alu_hi/SLICE_14 to SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C6B.CLK to R3C6B.Q0 alu_impl_I/alu_impl/alu_hi/SLICE_14 (from CLK_c) ROUTE 8 0.453 R3C6B.Q0 to R4C5C.D1 akku_7 ZERO_DEL --- 0.000 R4C5C.D1 to R4C5C.WDO3 sram_impl/mem0/SLICE_4 ROUTE 1 0.000 R4C5C.WDO3 to R4C5B.WD1 sram_impl/mem0/WD3_INT (to WE_mem) -------- 0.584 (22.4% logic, 77.6% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_14: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R3C6B.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.151 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 0.826 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.174 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.249 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.267 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.098 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.729 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 0.358 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.174 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 0.788 R5C4A.F0 to R4C5B.WCK WE_mem -------- 5.611 (26.3% logic, 73.7% route), 7 logic levels. Error: The following path exceeds requirements by 3.525ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i6 (from CLK_c +) Destination: FF Data in sram_impl/mem0/RAM1 (to WE_mem +) FF sram_impl/mem0/RAM1 Delay: 0.592ns (22.1% logic, 77.9% route), 2 logic levels. Constraint Details: 0.592ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_13 to SLICE_6 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.988ns skew requirement (totaling 4.117ns) by 3.525ns Physical Path Details: Data path alu_impl_I/alu_impl/alu_hi/SLICE_13 to SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C7C.CLK to R3C7C.Q0 alu_impl_I/alu_impl/alu_hi/SLICE_13 (from CLK_c) ROUTE 7 0.461 R3C7C.Q0 to R4C5C.C1 akku_6 ZERO_DEL --- 0.000 R4C5C.C1 to R4C5C.WDO2 sram_impl/mem0/SLICE_4 ROUTE 1 0.000 R4C5C.WDO2 to R4C5B.WD0 sram_impl/mem0/WD2_INT (to WE_mem) -------- 0.592 (22.1% logic, 77.9% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_13: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R3C7C.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.151 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 0.826 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.174 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.249 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.267 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.098 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.729 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 0.358 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.174 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 0.788 R5C4A.F0 to R4C5B.WCK WE_mem -------- 5.611 (26.3% logic, 73.7% route), 7 logic levels. Error: The following path exceeds requirements by 3.474ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i3 (from CLK_c +) Destination: FF Data in sram_impl/mem1/RAM1 (to WE_mem +) FF sram_impl/mem1/RAM1 Delay: 0.455ns (28.8% logic, 71.2% route), 2 logic levels. Constraint Details: 0.455ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_11 to sram_impl/mem1/SLICE_9 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.800ns skew requirement (totaling 3.929ns) by 3.474ns Physical Path Details: Data path alu_impl_I/alu_impl/alu_lo/SLICE_11 to sram_impl/mem1/SLICE_9: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C7A.CLK to R3C7A.Q1 alu_impl_I/alu_impl/alu_lo/SLICE_11 (from CLK_c) ROUTE 8 0.324 R3C7A.Q1 to R5C6C.D1 akku_3 ZERO_DEL --- 0.000 R5C6C.D1 to R5C6C.WDO3 sram_impl/mem1/SLICE_7 ROUTE 1 0.000 R5C6C.WDO3 to R5C6B.WD1 sram_impl/mem1/WD3_INT (to WE_mem) -------- 0.455 (28.8% logic, 71.2% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/alu_lo/SLICE_11: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R3C7A.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_9: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.151 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 0.826 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.174 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.249 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.267 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.098 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.729 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 0.358 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.174 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 0.600 R5C4A.F0 to R5C6B.WCK WE_mem -------- 5.423 (27.2% logic, 72.8% route), 7 logic levels. Error: The following path exceeds requirements by 3.313ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i2 (from CLK_c +) Destination: FF Data in sram_impl/mem1/RAM1 (to WE_mem +) FF sram_impl/mem1/RAM1 Delay: 0.616ns (21.3% logic, 78.7% route), 2 logic levels. Constraint Details: 0.616ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_11 to sram_impl/mem1/SLICE_9 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.800ns skew requirement (totaling 3.929ns) by 3.313ns Physical Path Details: Data path alu_impl_I/alu_impl/alu_lo/SLICE_11 to sram_impl/mem1/SLICE_9: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C7A.CLK to R3C7A.Q0 alu_impl_I/alu_impl/alu_lo/SLICE_11 (from CLK_c) ROUTE 8 0.485 R3C7A.Q0 to R5C6C.C1 akku_2 ZERO_DEL --- 0.000 R5C6C.C1 to R5C6C.WDO2 sram_impl/mem1/SLICE_7 ROUTE 1 0.000 R5C6C.WDO2 to R5C6B.WD0 sram_impl/mem1/WD2_INT (to WE_mem) -------- 0.616 (21.3% logic, 78.7% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/alu_lo/SLICE_11: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R3C7A.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_9: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.151 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 0.826 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.174 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.249 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.267 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.098 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.729 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 0.358 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.174 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 0.600 R5C4A.F0 to R5C6B.WCK WE_mem -------- 5.423 (27.2% logic, 72.8% route), 7 logic levels. Error: The following path exceeds requirements by 3.287ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i0 (from CLK_c +) Destination: FF Data in sram_impl/mem1/RAM0 (to WE_mem +) FF sram_impl/mem1/RAM0 Delay: 0.642ns (20.4% logic, 79.6% route), 2 logic levels. Constraint Details: 0.642ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_10 to sram_impl/mem1/SLICE_8 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.800ns skew requirement (totaling 3.929ns) by 3.287ns Physical Path Details: Data path alu_impl_I/alu_impl/alu_lo/SLICE_10 to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C8A.CLK to R3C8A.Q0 alu_impl_I/alu_impl/alu_lo/SLICE_10 (from CLK_c) ROUTE 7 0.511 R3C8A.Q0 to R5C6C.A1 akku_0 ZERO_DEL --- 0.000 R5C6C.A1 to R5C6C.WDO0 sram_impl/mem1/SLICE_7 ROUTE 1 0.000 R5C6C.WDO0 to R5C6A.WD0 sram_impl/mem1/WD0_INT (to WE_mem) -------- 0.642 (20.4% logic, 79.6% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/alu_lo/SLICE_10: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R3C8A.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.151 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 0.826 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.174 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.249 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.267 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.098 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.729 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 0.358 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.174 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 0.600 R5C4A.F0 to R5C6A.WCK WE_mem -------- 5.423 (27.2% logic, 72.8% route), 7 logic levels. Error: The following path exceeds requirements by 3.274ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i1 (from CLK_c +) Destination: FF Data in sram_impl/mem1/RAM0 (to WE_mem +) FF sram_impl/mem1/RAM0 Delay: 0.655ns (20.0% logic, 80.0% route), 2 logic levels. Constraint Details: 0.655ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_10 to sram_impl/mem1/SLICE_8 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.800ns skew requirement (totaling 3.929ns) by 3.274ns Physical Path Details: Data path alu_impl_I/alu_impl/alu_lo/SLICE_10 to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C8A.CLK to R3C8A.Q1 alu_impl_I/alu_impl/alu_lo/SLICE_10 (from CLK_c) ROUTE 8 0.524 R3C8A.Q1 to R5C6C.B1 akku_1 ZERO_DEL --- 0.000 R5C6C.B1 to R5C6C.WDO1 sram_impl/mem1/SLICE_7 ROUTE 1 0.000 R5C6C.WDO1 to R5C6A.WD1 sram_impl/mem1/WD1_INT (to WE_mem) -------- 0.655 (20.0% logic, 80.0% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/alu_lo/SLICE_10: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R3C8A.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.151 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 0.826 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.174 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.249 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.267 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.098 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.729 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 0.358 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.174 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 0.600 R5C4A.F0 to R5C6A.WCK WE_mem -------- 5.423 (27.2% logic, 72.8% route), 7 logic levels. Error: The following path exceeds requirements by 3.226ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i1 (from CLK_c +) Destination: FF Data in r_oport_i2 (to O_STB_c +) Delay: 0.492ns (26.6% logic, 73.4% route), 1 logic levels. Constraint Details: 0.492ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_10 to O_PORT_1_MGIOL exceeds -0.036ns DO_HLD and 0.000ns delay constraint less -3.754ns skew requirement (totaling 3.718ns) by 3.226ns Physical Path Details: Data path alu_impl_I/alu_impl/alu_lo/SLICE_10 to O_PORT_1_MGIOL: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C8A.CLK to R3C8A.Q1 alu_impl_I/alu_impl/alu_lo/SLICE_10 (from CLK_c) ROUTE 8 0.361 R3C8A.Q1 to IOL_R5A.OPOS akku_1 (to O_STB_c) -------- 0.492 (26.6% logic, 73.4% route), 1 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/alu_lo/SLICE_10: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R3C8A.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to O_PORT_1_MGIOL: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.151 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 0.826 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.174 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.249 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.267 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.098 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.729 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 0.160 R5C2D.F1 to R5C2D.C0 n9 CTOF_DEL --- 0.174 R5C2D.C0 to R5C2D.F0 SLICE_69 ROUTE 8 0.752 R5C2D.F0 to IOL_R5A.CLK O_STB_c -------- 5.377 (27.5% logic, 72.5% route), 7 logic levels. Error: The following path exceeds requirements by 3.200ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i2 (from CLK_c +) Destination: FF Data in r_oport_i3 (to O_STB_c +) Delay: 0.518ns (25.3% logic, 74.7% route), 1 logic levels. Constraint Details: 0.518ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_11 to O_PORT_2_MGIOL exceeds -0.036ns DO_HLD and 0.000ns delay constraint less -3.754ns skew requirement (totaling 3.718ns) by 3.200ns Physical Path Details: Data path alu_impl_I/alu_impl/alu_lo/SLICE_11 to O_PORT_2_MGIOL: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C7A.CLK to R3C7A.Q0 alu_impl_I/alu_impl/alu_lo/SLICE_11 (from CLK_c) ROUTE 8 0.387 R3C7A.Q0 to IOL_T9D.OPOS akku_2 (to O_STB_c) -------- 0.518 (25.3% logic, 74.7% route), 1 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/alu_lo/SLICE_11: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R3C7A.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to O_PORT_2_MGIOL: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 16 1.184 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.151 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 0.826 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.174 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.249 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.267 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.098 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.729 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 0.160 R5C2D.F1 to R5C2D.C0 n9 CTOF_DEL --- 0.174 R5C2D.C0 to R5C2D.F0 SLICE_69 ROUTE 8 0.752 R5C2D.F0 to IOL_T9D.CLK O_STB_c -------- 5.377 (27.5% logic, 72.5% route), 7 logic levels. ================================================================================ Preference: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.500000 X ; 30 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 14.969ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in flags_i0 (to CLK_c +) Delay: 1.067ns (47.2% logic, 52.8% route), 4 logic levels. Constraint Details: 1.067ns physical path delay SLICE_5 to SLICE_15 meets -0.013ns DIN_HLD and -13.889ns delay constraint less 0.000ns skew requirement (totaling -13.902ns) by 14.969ns Physical Path Details: Data path SLICE_5 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C5A.CLK to R4C5A.Q1 SLICE_5 (from CLK_c) ROUTE 66 0.229 R4C5A.Q1 to R2C4D.D0 r_addr_1 CTOOFX_DEL --- 0.153 R2C4D.D0 to R2C4D.OFX0 alu_impl_I/SLICE_63 ROUTE 1 0.000 R2C4D.OFX0 to R2C4C.FXA alu_impl_I/mux_90_Mux_9_0_f5a FXTOOFX_DE --- 0.067 R2C4C.FXA to R2C4C.OFX1 alu_impl_I/SLICE_64 ROUTE 20 0.334 R2C4C.OFX1 to R3C6D.A0 int_c_adj_26 CTOOFX_DEL --- 0.153 R3C6D.A0 to R3C6D.OFX0 SLICE_15 ROUTE 1 0.000 R3C6D.OFX0 to R3C6D.DI0 n187 (to CLK_c) -------- 1.067 (47.2% logic, 52.8% route), 4 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R4C5A.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R3C6D.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 14.969ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in flags_i0 (to CLK_c +) Delay: 1.067ns (47.2% logic, 52.8% route), 4 logic levels. Constraint Details: 1.067ns physical path delay SLICE_5 to SLICE_15 meets -0.013ns DIN_HLD and -13.889ns delay constraint less 0.000ns skew requirement (totaling -13.902ns) by 14.969ns Physical Path Details: Data path SLICE_5 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C5A.CLK to R4C5A.Q1 SLICE_5 (from CLK_c) ROUTE 66 0.229 R4C5A.Q1 to R2C4D.D1 r_addr_1 CTOOFX_DEL --- 0.153 R2C4D.D1 to R2C4D.OFX0 alu_impl_I/SLICE_63 ROUTE 1 0.000 R2C4D.OFX0 to R2C4C.FXA alu_impl_I/mux_90_Mux_9_0_f5a FXTOOFX_DE --- 0.067 R2C4C.FXA to R2C4C.OFX1 alu_impl_I/SLICE_64 ROUTE 20 0.334 R2C4C.OFX1 to R3C6D.A0 int_c_adj_26 CTOOFX_DEL --- 0.153 R3C6D.A0 to R3C6D.OFX0 SLICE_15 ROUTE 1 0.000 R3C6D.OFX0 to R3C6D.DI0 n187 (to CLK_c) -------- 1.067 (47.2% logic, 52.8% route), 4 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R4C5A.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R3C6D.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 14.973ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i3 (from CLK_c -) Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i7 (to CLK_c +) Delay: 1.071ns (51.3% logic, 48.7% route), 5 logic levels. Constraint Details: 1.071ns physical path delay SLICE_6 to alu_impl_I/alu_impl/alu_hi/SLICE_14 meets -0.013ns DIN_HLD and -13.889ns delay constraint less 0.000ns skew requirement (totaling -13.902ns) by 14.973ns Physical Path Details: Data path SLICE_6 to alu_impl_I/alu_impl/alu_hi/SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C5B.CLK to R4C5B.Q0 SLICE_6 (from CLK_c) ROUTE 67 0.153 R4C5B.Q0 to R2C5A.D1 r_addr_2 CTOOFX_DEL --- 0.153 R2C5A.D1 to R2C5A.OFX0 alu_impl/i2734/SLICE_39 ROUTE 1 0.000 R2C5A.OFX0 to R2C5A.FXB alu_impl/n3439 FXTOOFX_DE --- 0.067 R2C5A.FXB to R2C5A.OFX1 alu_impl/i2734/SLICE_39 ROUTE 17 0.312 R2C5A.OFX1 to R3C6B.B1 code_data_7 CTOF_DEL --- 0.099 R3C6B.B1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 0.057 R3C6B.F1 to R3C6B.C0 F_7 CTOF_DEL --- 0.099 R3C6B.C0 to R3C6B.F0 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 1 0.000 R3C6B.F0 to R3C6B.DI0 alu_impl_I/alu_impl/alu_hi/n1204 (to CLK_c) -------- 1.071 (51.3% logic, 48.7% route), 5 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R4C5B.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R3C6B.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 14.973ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i3 (from CLK_c -) Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i7 (to CLK_c +) Delay: 1.071ns (51.3% logic, 48.7% route), 5 logic levels. Constraint Details: 1.071ns physical path delay SLICE_6 to alu_impl_I/alu_impl/alu_hi/SLICE_14 meets -0.013ns DIN_HLD and -13.889ns delay constraint less 0.000ns skew requirement (totaling -13.902ns) by 14.973ns Physical Path Details: Data path SLICE_6 to alu_impl_I/alu_impl/alu_hi/SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C5B.CLK to R4C5B.Q0 SLICE_6 (from CLK_c) ROUTE 67 0.153 R4C5B.Q0 to R2C5A.D0 r_addr_2 CTOOFX_DEL --- 0.153 R2C5A.D0 to R2C5A.OFX0 alu_impl/i2734/SLICE_39 ROUTE 1 0.000 R2C5A.OFX0 to R2C5A.FXB alu_impl/n3439 FXTOOFX_DE --- 0.067 R2C5A.FXB to R2C5A.OFX1 alu_impl/i2734/SLICE_39 ROUTE 17 0.312 R2C5A.OFX1 to R3C6B.B1 code_data_7 CTOF_DEL --- 0.099 R3C6B.B1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 0.057 R3C6B.F1 to R3C6B.C0 F_7 CTOF_DEL --- 0.099 R3C6B.C0 to R3C6B.F0 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 1 0.000 R3C6B.F0 to R3C6B.DI0 alu_impl_I/alu_impl/alu_hi/n1204 (to CLK_c) -------- 1.071 (51.3% logic, 48.7% route), 5 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R4C5B.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R3C6B.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 14.974ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in flags_i0 (to CLK_c +) Delay: 1.072ns (47.0% logic, 53.0% route), 4 logic levels. Constraint Details: 1.072ns physical path delay SLICE_5 to SLICE_15 meets -0.013ns DIN_HLD and -13.889ns delay constraint less 0.000ns skew requirement (totaling -13.902ns) by 14.974ns Physical Path Details: Data path SLICE_5 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C5A.CLK to R4C5A.Q1 SLICE_5 (from CLK_c) ROUTE 66 0.234 R4C5A.Q1 to R2C4C.C1 r_addr_1 CTOOFX_DEL --- 0.153 R2C4C.C1 to R2C4C.OFX0 alu_impl_I/SLICE_64 ROUTE 1 0.000 R2C4C.OFX0 to R2C4C.FXB alu_impl_I/mux_90_Mux_9_1_f5b FXTOOFX_DE --- 0.067 R2C4C.FXB to R2C4C.OFX1 alu_impl_I/SLICE_64 ROUTE 20 0.334 R2C4C.OFX1 to R3C6D.A0 int_c_adj_26 CTOOFX_DEL --- 0.153 R3C6D.A0 to R3C6D.OFX0 SLICE_15 ROUTE 1 0.000 R3C6D.OFX0 to R3C6D.DI0 n187 (to CLK_c) -------- 1.072 (47.0% logic, 53.0% route), 4 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R4C5A.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R3C6D.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 14.974ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in flags_i0 (to CLK_c +) Delay: 1.072ns (47.0% logic, 53.0% route), 4 logic levels. Constraint Details: 1.072ns physical path delay SLICE_5 to SLICE_15 meets -0.013ns DIN_HLD and -13.889ns delay constraint less 0.000ns skew requirement (totaling -13.902ns) by 14.974ns Physical Path Details: Data path SLICE_5 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C5A.CLK to R4C5A.Q1 SLICE_5 (from CLK_c) ROUTE 66 0.234 R4C5A.Q1 to R2C4C.C0 r_addr_1 CTOOFX_DEL --- 0.153 R2C4C.C0 to R2C4C.OFX0 alu_impl_I/SLICE_64 ROUTE 1 0.000 R2C4C.OFX0 to R2C4C.FXB alu_impl_I/mux_90_Mux_9_1_f5b FXTOOFX_DE --- 0.067 R2C4C.FXB to R2C4C.OFX1 alu_impl_I/SLICE_64 ROUTE 20 0.334 R2C4C.OFX1 to R3C6D.A0 int_c_adj_26 CTOOFX_DEL --- 0.153 R3C6D.A0 to R3C6D.OFX0 SLICE_15 ROUTE 1 0.000 R3C6D.OFX0 to R3C6D.DI0 n187 (to CLK_c) -------- 1.072 (47.0% logic, 53.0% route), 4 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R4C5A.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R3C6D.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 14.976ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i3 (from CLK_c -) Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i7 (to CLK_c +) Delay: 1.074ns (51.1% logic, 48.9% route), 5 logic levels. Constraint Details: 1.074ns physical path delay SLICE_6 to alu_impl_I/alu_impl/alu_hi/SLICE_14 meets -0.013ns DIN_HLD and -13.889ns delay constraint less 0.000ns skew requirement (totaling -13.902ns) by 14.976ns Physical Path Details: Data path SLICE_6 to alu_impl_I/alu_impl/alu_hi/SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C5B.CLK to R4C5B.Q0 SLICE_6 (from CLK_c) ROUTE 67 0.156 R4C5B.Q0 to R2C5B.C0 r_addr_2 CTOOFX_DEL --- 0.153 R2C5B.C0 to R2C5B.OFX0 alu_impl/i2733/SLICE_40 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA alu_impl/n3438 FXTOOFX_DE --- 0.067 R2C5A.FXA to R2C5A.OFX1 alu_impl/i2734/SLICE_39 ROUTE 17 0.312 R2C5A.OFX1 to R3C6B.B1 code_data_7 CTOF_DEL --- 0.099 R3C6B.B1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 0.057 R3C6B.F1 to R3C6B.C0 F_7 CTOF_DEL --- 0.099 R3C6B.C0 to R3C6B.F0 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 1 0.000 R3C6B.F0 to R3C6B.DI0 alu_impl_I/alu_impl/alu_hi/n1204 (to CLK_c) -------- 1.074 (51.1% logic, 48.9% route), 5 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R4C5B.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R3C6B.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 14.976ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i3 (from CLK_c -) Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i7 (to CLK_c +) Delay: 1.074ns (51.1% logic, 48.9% route), 5 logic levels. Constraint Details: 1.074ns physical path delay SLICE_6 to alu_impl_I/alu_impl/alu_hi/SLICE_14 meets -0.013ns DIN_HLD and -13.889ns delay constraint less 0.000ns skew requirement (totaling -13.902ns) by 14.976ns Physical Path Details: Data path SLICE_6 to alu_impl_I/alu_impl/alu_hi/SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C5B.CLK to R4C5B.Q0 SLICE_6 (from CLK_c) ROUTE 67 0.156 R4C5B.Q0 to R2C5B.C1 r_addr_2 CTOOFX_DEL --- 0.153 R2C5B.C1 to R2C5B.OFX0 alu_impl/i2733/SLICE_40 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA alu_impl/n3438 FXTOOFX_DE --- 0.067 R2C5A.FXA to R2C5A.OFX1 alu_impl/i2734/SLICE_39 ROUTE 17 0.312 R2C5A.OFX1 to R3C6B.B1 code_data_7 CTOF_DEL --- 0.099 R3C6B.B1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 0.057 R3C6B.F1 to R3C6B.C0 F_7 CTOF_DEL --- 0.099 R3C6B.C0 to R3C6B.F0 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 1 0.000 R3C6B.F0 to R3C6B.DI0 alu_impl_I/alu_impl/alu_hi/n1204 (to CLK_c) -------- 1.074 (51.1% logic, 48.9% route), 5 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R4C5B.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R3C6B.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 15.018ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i3 (from CLK_c -) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 1.116ns (49.2% logic, 50.8% route), 5 logic levels. Constraint Details: 1.116ns physical path delay SLICE_6 to SLICE_16 meets -0.013ns DIN_HLD and -13.889ns delay constraint less 0.000ns skew requirement (totaling -13.902ns) by 15.018ns Physical Path Details: Data path SLICE_6 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C5B.CLK to R4C5B.Q0 SLICE_6 (from CLK_c) ROUTE 67 0.153 R4C5B.Q0 to R2C5A.D1 r_addr_2 CTOOFX_DEL --- 0.153 R2C5A.D1 to R2C5A.OFX0 alu_impl/i2734/SLICE_39 ROUTE 1 0.000 R2C5A.OFX0 to R2C5A.FXB alu_impl/n3439 FXTOOFX_DE --- 0.067 R2C5A.FXB to R2C5A.OFX1 alu_impl/i2734/SLICE_39 ROUTE 17 0.357 R2C5A.OFX1 to R4C8C.A1 code_data_7 CTOF_DEL --- 0.099 R4C8C.A1 to R4C8C.F1 SLICE_16 ROUTE 2 0.057 R4C8C.F1 to R4C8C.C0 F_0 CTOF_DEL --- 0.099 R4C8C.C0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 1.116 (49.2% logic, 50.8% route), 5 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R4C5B.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R4C8C.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 15.018ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i3 (from CLK_c -) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 1.116ns (49.2% logic, 50.8% route), 5 logic levels. Constraint Details: 1.116ns physical path delay SLICE_6 to SLICE_16 meets -0.013ns DIN_HLD and -13.889ns delay constraint less 0.000ns skew requirement (totaling -13.902ns) by 15.018ns Physical Path Details: Data path SLICE_6 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C5B.CLK to R4C5B.Q0 SLICE_6 (from CLK_c) ROUTE 67 0.153 R4C5B.Q0 to R2C5A.D0 r_addr_2 CTOOFX_DEL --- 0.153 R2C5A.D0 to R2C5A.OFX0 alu_impl/i2734/SLICE_39 ROUTE 1 0.000 R2C5A.OFX0 to R2C5A.FXB alu_impl/n3439 FXTOOFX_DE --- 0.067 R2C5A.FXB to R2C5A.OFX1 alu_impl/i2734/SLICE_39 ROUTE 17 0.357 R2C5A.OFX1 to R4C8C.A1 code_data_7 CTOF_DEL --- 0.099 R4C8C.A1 to R4C8C.F1 SLICE_16 ROUTE 2 0.057 R4C8C.F1 to R4C8C.C0 F_0 CTOF_DEL --- 0.099 R4C8C.C0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 1.116 (49.2% logic, 50.8% route), 5 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R4C5B.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 16 1.184 12.PADDI to R4C8C.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "CLK" 36.000000 MHz ; | -| -| 2 * | | | MULTICYCLE FROM GROUP "code" TO GROUP | | | "akku" 1.500000 X ; | -| -| 4 | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- akku_0 | 7| 2| 13.33% | | | akku_1 | 8| 2| 13.33% | | | akku_2 | 8| 2| 13.33% | | | akku_3 | 8| 2| 13.33% | | | akku_4 | 8| 2| 13.33% | | | akku_5 | 8| 2| 13.33% | | | akku_7 | 8| 2| 13.33% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 3 clocks: Clock Domain: WE_mem Source: SLICE_70.F0 Loads: 4 No transfer within this clock domain is found Data transfers from: Clock Domain: CLK_c Source: CLK.PAD Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ; Transfers: 14 Clock Domain: CLK_c Source: CLK.PAD Loads: 16 Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ; Covered under: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.500000 X ; Data transfers from: Clock Domain: WE_mem Source: SLICE_70.F0 Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ; Transfers: 8 Clock Domain: O_STB_c Source: SLICE_69.F0 Loads: 8 No transfer within this clock domain is found Data transfers from: Clock Domain: CLK_c Source: CLK.PAD Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ; Transfers: 7 Timing summary (Hold): --------------- Timing errors: 15 Score: 49380 Cumulative negative slack: 49380 Constraints cover 31851 paths, 8 nets, and 891 connections (97.4% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 15 (hold) Score: 0 (setup), 49380 (hold) Cumulative negative slack: 49380 (0+49380)