Synthesis and Ngdbuild  Report
#Build: Synplify Pro F-2011.09L, Build 022R, Oct 19 2011
#install: C:\lscc\diamond\1.4\synpbase
#OS: Windows XP 5.1
#Hostname: BANDIT

$ Start of Compile
#Sun Jul 01 23:20:23 2012

Synopsys Verilog Compiler, version comp560rcp1, Build 045R, built Oct 18 2011
@N|Running in 32-bit mode
Copyright (C) 1994-2011 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@I::"C:\lscc\diamond\1.4\synpbase\lib\lucent\machxo2.v"
@I::"C:\lscc\diamond\1.4\synpbase\lib\vlog\scemi_objects.v"
@I::"C:\lscc\diamond\1.4\synpbase\lib\vlog\hypermods.v"
@I::"C:\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo2.v"
@I::"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v"
@W: CG921 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":121:8:121:16|CRC_MATCH is already declared in this scope.
Verilog syntax check successful!
Selecting top level module udrv
@N: CG364 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":372:7:372:17|Synthesizing module udrv_clkgen

@N: CG364 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":696:7:696:15|Synthesizing module udrv_fifo

	DEPTH=32'b00000000000000000000000000000100
	DELAYED_INPUT=32'b00000000000000000000000000000001
   Generated name = udrv_fifo_4s_1s

@N: CL134 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":729:4:729:9|Found RAM mem, depth=16, width=8
@N: CG364 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":403:7:403:19|Synthesizing module udrv_reciever

@W: CL265 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":443:4:443:9|Pruning bit 0 of r_data[7:0] -- not in use ...

@N: CG364 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":519:7:519:17|Synthesizing module udrv_sender

	FS=32'b00000000000000000000000000000001
   Generated name = udrv_sender_1s

@N: CG364 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":774:7:774:14|Synthesizing module udrv_crc

	WIDTH=32'b00000000000000000000000000000101
	SEQUENTIAL_MATCHING=32'b00000000000000000000000000000001
   Generated name = udrv_crc_5s_1s

@N: CG364 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":774:7:774:14|Synthesizing module udrv_crc

	WIDTH=32'b00000000000000000000000000010000
	SEQUENTIAL_MATCHING=32'b00000000000000000000000000000000
   Generated name = udrv_crc_16s_0s

@W: CL169 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":797:4:797:9|Pruning register r_match 

@N: CG364 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":822:7:822:14|Synthesizing module udrv_spi

@A: CL282 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":861:4:861:9|Feedback mux created for signal spi_out[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N: CG364 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":64:7:64:10|Synthesizing module udrv

@W: CG360 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":148:9:148:11|No assignment to wire DPM

@N: CL201 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":574:4:574:9|Trying to extract state machine for register send_stat
Extracted state machine for register send_stat
State machine has 6 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
@W: CL249 :"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\src\udrv.v":574:4:574:9|Initial value is not supported on state machine send_stat
@END
Premap Report (contents appended below)
@N:"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\udrv\synlog\qfn32samples_udrv_premap.srr"
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 239R, Built Oct 19 2011 10:56:21
Copyright (C) 1994-2011, Synopsys Inc.  All Rights Reserved
Product Version F-2011.09L

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled 
@N: MF546 |Generated clock conversion enabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 50MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 50MB)

@W: FX474 |User specified initial value found in some of the sequential elements in the design. Applying an initial value to a register may not deliver the best synthesis results. For example, registers with initial values may be preserved and retiming/pipelining may not be performed. To improve synthesis results you may want to remove the register initialization from the RTL code 
syn_allowed_resources : blockrams=0  set on top level netlist udrv

Finished Pre Mapping Phase. (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 77MB)

Pre Mapping successful!

At Mapper Exit (Time elapsed 0h:00m:02s; Memory used current: 42MB peak: 77MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Sun Jul 01 23:20:29 2012

###########################################################]
Map & Optimize Report (contents appended below)
@N:"C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\udrv\synlog\qfn32samples_udrv_fpga_mapper.srr"
Synopsys Lattice Technology Mapper, Version maplat, Build 239R, Built Oct 19 2011 10:56:21
Copyright (C) 1994-2011, Synopsys Inc.  All Rights Reserved
Product Version F-2011.09L

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled 
@N: MF546 |Generated clock conversion enabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF203 |Set autoconstraint_io 


Starting Optimization and Mapping (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 77MB)


Available hyper_sources - for debug and ip models
	None Found

@N: FX493 |Applying Initial value "00" on instance: sender_impl.crc16_sel[1:0] 
@N: FX493 |Applying Initial value "00" on instance: sender_impl.crc5_sel[1:0] 
@N: FX493 |Applying Initial value "11111" on instance: crc5_impl.r_crc[4:0] 
@N: FX493 |Applying Initial value "1111111111111111" on instance: crc16_impl.r_crc[15:0] 
@N: FX493 |Applying Initial value "00000000" on instance: spi_impl.r_spi[7:0] 
@N: FX493 |Applying Initial value "00000000" on instance: spi_impl.spi_out[7:0] 

Finished RTL optimizations (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 77MB)

@N:"c:\documents and settings\suz\my documents\lattice\qfn32samples-10\src\udrv.v":729:4:729:9|Found counter in view:work.udrv_fifo_4s_1s(verilog) inst o_addr[3:0]
Encoding state machine work.udrv_sender_1s(verilog)-send_stat[5:0]
original code -> new code
   000 -> 000001
   001 -> 000010
   010 -> 000100
   011 -> 001000
   100 -> 010000
   101 -> 100000
@N:"c:\documents and settings\suz\my documents\lattice\qfn32samples-10\src\udrv.v":574:4:574:9|Found counter in view:work.udrv_sender_1s(verilog) inst data_count[3:0]

Finished factoring (Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 78MB)



#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[

======================================================================================
                                Instance:Pin        Generated Clock Optimization Status
======================================================================================
                       spi_impl.r_spi[4]:C              Not Done
                             dummy_i_rdy:C              Done
                             dummy_o_ack:C              Done
                              r_sync_req:C              Done
                               r_send_en:C              Done
                               r_recv_en:C              Done
                              r_recv_en1:C              Done
                                   r_dpr:C              Done
                                   r_se0:C              Done
                              r_recv_req:C              Done
                            r_send_start:C              Done
                    crc16_impl.r_crc[11]:C              Done
                    crc16_impl.r_crc[12]:C              Done
                    crc16_impl.r_crc[13]:C              Done
                    crc16_impl.r_crc[14]:C              Done
                    crc16_impl.r_crc[15]:C              Done
                     crc16_impl.r_crc[4]:C              Done
                     crc16_impl.r_crc[5]:C              Done
                     crc16_impl.r_crc[6]:C              Done
                     crc16_impl.r_crc[7]:C              Done
                     crc16_impl.r_crc[8]:C              Done
                     crc16_impl.r_crc[9]:C              Done
                    crc16_impl.r_crc[10]:C              Done
                     crc16_impl.r_crc[0]:C              Done
                     crc16_impl.r_crc[1]:C              Done
                     crc16_impl.r_crc[2]:C              Done
                     crc16_impl.r_crc[3]:C              Done
                      crc5_impl.r_crc[2]:C              Done
                      crc5_impl.r_crc[3]:C              Done
                      crc5_impl.r_crc[4]:C              Done
                       crc5_impl.r_match:C              Done
                      crc5_impl.r_crc[0]:C              Done
                      crc5_impl.r_crc[1]:C              Done
                sender_impl.crc16_sel[0]:C              Done
                sender_impl.crc16_sel[1]:C              Done
                 sender_impl.crc5_sel[0]:C              Done
                 sender_impl.crc5_sel[1]:C              Done
                    sender_impl.data_ack:C              Done
                      sender_impl.use_i5:C              Done
                     sender_impl.use_i16:C              Done
                        sender_impl.r_oe:C              Done
                     sender_impl.crc_out:C              Done
                sender_impl.send_stat[1]:C              Done
                sender_impl.send_stat[0]:C              Done
                sender_impl.send_stat[5]:C              Done
                sender_impl.send_stat[4]:C              Done
                sender_impl.send_stat[3]:C              Done
                sender_impl.send_stat[2]:C              Done
               sender_impl.data_count[2]:C              Done
               sender_impl.data_count[1]:C              Done
               sender_impl.data_count[0]:C              Done
                sender_impl.one_count[2]:C              Done
                sender_impl.one_count[1]:C              Done
                sender_impl.one_count[0]:C              Done
               sender_impl.data_bytes[2]:C              Done
               sender_impl.data_bytes[1]:C              Done
               sender_impl.data_bytes[0]:C              Done
               sender_impl.data_count[3]:C              Done
                        sender_impl.r_dm:C              Done
                        sender_impl.r_dp:C              Done
                  sender_impl.data_in[6]:C              Done
                  sender_impl.data_in[5]:C              Done
                  sender_impl.data_in[4]:C              Done
                  sender_impl.data_in[3]:C              Done
                  sender_impl.data_in[2]:C              Done
                  sender_impl.data_in[1]:C              Done
                  sender_impl.data_in[0]:C              Done
                       sender_impl.r_out:C              Done
               sender_impl.crc16_extract:C              Done
                sender_impl.crc5_extract:C              Done
                       reciever_impl.r_o:C              Done
                  reciever_impl.data_ack:C              Done
                      reciever_impl.r_dp:C              Done
                  reciever_impl.data_set:C              Done
                  reciever_impl.data_rdy:C              Done
                 reciever_impl.recv_stat:C              Done
             reciever_impl.data_bytes[0]:C              Done
              reciever_impl.one_count[2]:C              Done
              reciever_impl.one_count[1]:C              Done
              reciever_impl.one_count[0]:C              Done
             reciever_impl.data_count[2]:C              Done
             reciever_impl.data_count[1]:C              Done
             reciever_impl.data_count[0]:C              Done
             reciever_impl.data_bytes[1]:C              Done
                 reciever_impl.r_data[7]:C              Done
                 reciever_impl.r_data[6]:C              Done
                 reciever_impl.r_data[5]:C              Done
                 reciever_impl.r_data[4]:C              Done
                 reciever_impl.r_data[3]:C              Done
                 reciever_impl.r_data[2]:C              Done
                 reciever_impl.r_data[1]:C              Done
               reciever_impl.data_out[7]:C              Done
               reciever_impl.data_out[6]:C              Done
               reciever_impl.data_out[5]:C              Done
               reciever_impl.data_out[4]:C              Done
               reciever_impl.data_out[3]:C              Done
               reciever_impl.data_out[2]:C              Done
               reciever_impl.data_out[1]:C              Done
               reciever_impl.data_out[0]:C              Done
              reciever_impl.crc16_sel[1]:C              Done
              reciever_impl.crc16_sel[0]:C              Done
               reciever_impl.r_match_sel:C              Done
               reciever_impl.crc5_sel[1]:C              Done
               reciever_impl.crc5_sel[0]:C              Done
                         fifo_impl.o_ack:C              Done
                         fifo_impl.i_ack:C              Done
                        fifo_impl.r_full:C              Done
                         fifo_impl.o_rdy:C              Done
                         fifo_impl.i_rdy:C              Done
                     fifo_impl.o_addr[0]:C              Done
                     fifo_impl.o_addr[3]:C              Done
                     fifo_impl.o_addr[2]:C              Done
                     fifo_impl.o_addr[1]:C              Done
                     fifo_impl.i_addr[3]:C              Done
                     fifo_impl.i_addr[2]:C              Done
                     fifo_impl.i_addr[1]:C              Done
                     fifo_impl.i_addr[0]:C              Done


##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]


Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:03s; Memory used current: 76MB peak: 78MB)



Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:04s; Memory used current: 76MB peak: 78MB)


Starting Early Timing Optimization (Time elapsed 0h:00m:04s; Memory used current: 77MB peak: 78MB)


Finished Early Timing Optimization (Time elapsed 0h:00m:05s; Memory used current: 77MB peak: 78MB)


Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:05s; Memory used current: 76MB peak: 78MB)


Finished preparing to map (Time elapsed 0h:00m:06s; Memory used current: 77MB peak: 78MB)


Finished technology mapping (Time elapsed 0h:00m:07s; Memory used current: 80MB peak: 82MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:08s; Memory used current: 77MB peak: 82MB)

@N: FX164 |The option to pack flops in the IOB has not been specified 
@N: FO126 :"c:\documents and settings\suz\my documents\lattice\qfn32samples-10\src\udrv.v":729:4:729:9|Generating RAM fifo_impl.mem[7:0]

Finished restoring hierarchy (Time elapsed 0h:00m:09s; Memory used current: 77MB peak: 82MB)

Writing Analyst data base C:\Documents and Settings\suz\My Documents\lattice\qfn32samples-10\udrv\qfn32samples_udrv.srm

Finished Writing Netlist Databases (Time elapsed 0h:00m:10s; Memory used current: 77MB peak: 82MB)

Writing EDIF Netlist and constraint files
F-2011.09L

Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:12s; Memory used current: 81MB peak: 82MB)


Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:13s; Memory used current: 80MB peak: 82MB)

@N: MF276 |Gated clock conversion enabled, but no gated clocks found in design 

Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:13s; Memory used current: 80MB peak: 82MB)


Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:13s; Memory used current: 80MB peak: 82MB)

@N: MF333 |Generated clock conversion enabled, but no generated clocks found in design 

Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:13s; Memory used current: 80MB peak: 82MB)

@W: MT420 |Found inferred clock udrv|CLK_4X with period 1000.00ns. Please declare a user-defined clock on object "p:CLK_4X"

@W: MT420 |Found inferred clock udrv|SCK with period 1000.00ns. Please declare a user-defined clock on object "p:SCK"

Found clock udrv_clkgen|clk_ph_derived_clock[1] with period 1000.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Sun Jul 01 23:20:45 2012
#


Top view:               udrv
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.


Performance Summary 
*******************


Worst slack in design: 495.398

                                        Requested     Estimated     Requested     Estimated                 Clock                          Clock              
Starting Clock                          Frequency     Frequency     Period        Period        Slack       Type                           Group              
--------------------------------------------------------------------------------------------------------------------------------------------------------------
udrv_clkgen|clk_ph_derived_clock[1]     1.0 MHz       108.6 MHz     1000.000      9.205         498.428     derived (from udrv|CLK_4X)     Inferred_clkgroup_0
udrv|CLK_4X                             1.0 MHz       108.6 MHz     1000.000      9.205         495.398     inferred                       Inferred_clkgroup_0
udrv|SCK                                1.0 MHz       183.0 MHz     1000.000      5.465         497.267     inferred                       Inferred_clkgroup_1
System                                  1.0 MHz       122.2 MHz     1000.000      8.182         991.818     system                         system_clkgroup    
==============================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                    |    rise  to  rise     |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                             Ending                               |  constraint  slack    |  constraint  slack    |  constraint  slack    |  constraint  slack  
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                               System                               |  1000.000    991.818  |  No paths    -        |  No paths    -        |  No paths    -      
System                               udrv|CLK_4X                          |  1000.000    990.958  |  No paths    -        |  No paths    -        |  No paths    -      
System                               udrv|SCK                             |  1000.000    997.915  |  No paths    -        |  1000.000    994.923  |  No paths    -      
System                               udrv_clkgen|clk_ph_derived_clock[1]  |  No paths    -        |  No paths    -        |  1000.000    996.724  |  No paths    -      
udrv|CLK_4X                          System                               |  1000.000    989.772  |  No paths    -        |  No paths    -        |  No paths    -      
udrv|CLK_4X                          udrv|CLK_4X                          |  1000.000    991.973  |  No paths    -        |  No paths    -        |  No paths    -      
udrv|CLK_4X                          udrv|SCK                             |  Diff grp    -        |  No paths    -        |  Diff grp    -        |  No paths    -      
udrv|CLK_4X                          udrv_clkgen|clk_ph_derived_clock[1]  |  No paths    -        |  No paths    -        |  500.000     495.398  |  No paths    -      
udrv|SCK                             System                               |  No paths    -        |  No paths    -        |  No paths    -        |  1000.000    992.630
udrv|SCK                             udrv|CLK_4X                          |  Diff grp    -        |  No paths    -        |  No paths    -        |  Diff grp    -      
udrv|SCK                             udrv|SCK                             |  1000.000    998.364  |  1000.000    996.619  |  500.000     498.851  |  500.000     497.267
udrv|SCK                             udrv_clkgen|clk_ph_derived_clock[1]  |  No paths    -        |  Diff grp    -        |  No paths    -        |  No paths    -      
udrv_clkgen|clk_ph_derived_clock[1]  System                               |  No paths    -        |  No paths    -        |  No paths    -        |  1000.000    993.038
udrv_clkgen|clk_ph_derived_clock[1]  udrv|CLK_4X                          |  No paths    -        |  No paths    -        |  No paths    -        |  500.000     498.428
udrv_clkgen|clk_ph_derived_clock[1]  udrv|SCK                             |  No paths    -        |  Diff grp    -        |  No paths    -        |  No paths    -      
========================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port           Starting            User           Arrival     Required          
Name           Reference           Constraint     Time        Time         Slack
               Clock                                                            
--------------------------------------------------------------------------------
CLK_4X         NA                  NA             NA          NA           NA   
CS             System (rising)     NA             0.000       996.000           
DM             System (rising)     NA             0.000       996.972           
DP             System (rising)     NA             0.000       993.646           
MOSI           System (rising)     NA             0.000       997.915           
RECV_MODE      System (rising)     NA             0.000       990.958           
RS             System (rising)     NA             0.000       991.818           
SCK            NA                  NA             NA          NA           NA   
SEND_START     System (rising)     NA             0.000       996.404           
================================================================================


Output Ports: 

Port           Starting                 User           Arrival     Required          
Name           Reference                Constraint     Time        Time         Slack
               Clock                                                                 
-------------------------------------------------------------------------------------
CRC_MATCH      udrv|CLK_4X (rising)     NA             8.195       1000.000          
DATA_EMPTY     udrv|CLK_4X (rising)     NA             7.326       1000.000          
DATA_FULL      udrv|CLK_4X (rising)     NA             5.560       1000.000          
DATA_RDY       System (rising)          NA             7.161       1000.000          
DM             udrv|CLK_4X (rising)     NA             5.623       1000.000          
DP             udrv|CLK_4X (rising)     NA             5.623       1000.000          
MISO           udrv|CLK_4X (rising)     NA             10.228      1000.000          
=====================================================================================


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report
Part: lcmxo2_256hc-4

Register bits: 143 of 256 (56%)
PIC Latch:       0
I/O cells:       14


Details:
BB:             2
DPR16X4C:       2
FD1P3AX:        72
FD1P3AY:        22
FD1P3DX:        1
FD1P3IX:        22
FD1P3JX:        1
FD1S3AX:        8
FD1S3DX:        12
FD1S3IX:        1
FD1S3JX:        1
GSR:            1
IB:             7
IFS1P3DX:       2
INV:            7
OB:             5
OFS1P3IX:       1
ORCALUT4:       240
PFUMX:          1
PUR:            1
VHI:            1
VLO:            1
false:          8
true:           8
Mapper successful!

At Mapper Exit (Time elapsed 0h:00m:14s; Memory used current: 26MB peak: 82MB)

Process took 0h:00m:16s realtime, 0h:00m:14s cputime
# Sun Jul 01 23:20:46 2012

###########################################################]