Place & Route TRACE Report
Loading design for application trce from file qfn32samples_mcpu3_efb.ncd.
Design name: mcpu
NCD version: 3.2
Vendor: LATTICE
Device: LCMXO2-256HC
Package: QFN32
Performance: 4
Loading device for application trce from file 'xo2c256.nph' in environment: Y:/Program_Files/lscc/diamond/1.4/ispfpga.
Package Status: Advanced Version 1.34
Performance Hardware Data Status: Final) Version 22.4
WARNING - trce: Source clock net WE_mem is not directly constrained. For this preference to work properly, please make sure the source of this clock is constrained. It appears in MULTICYCLE FROM CLKNET "WE_mem" 6.000000 X ; . Preserving this preference.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond_1.4_Production (87)
Tue Jun 26 16:39:57 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_mcpu3_efb.twr qfn32samples_mcpu3_efb.ncd qfn32samples_mcpu3_efb.prf
Design file: qfn32samples_mcpu3_efb.ncd
Preference file: qfn32samples_mcpu3_efb.prf
Device,speed: LCMXO2-256HC,4
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY PORT "CLK_2X" 48.000000 MHz (0 errors) 1733 items scored, 0 timing errors detected.
Report: 58.245MHz is the maximum frequency for this preference.
MULTICYCLE FROM GROUP "code" TO GROUP "akku" 4.000000 X (0 errors) 4096 items scored, 0 timing errors detected.
MULTICYCLE FROM GROUP "efb" TO GROUP "akku" 2.000000 X (0 errors) 160 items scored, 0 timing errors detected.
MULTICYCLE FROM CLKNET "WE_mem" 6.000000 X (0 errors) 160 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY PORT "CLK_2X" 48.000000 MHz ;
1733 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.664ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i1 (from master_clk +)
Destination: EFB Port efb_impl/EFBInst_0(ASIC) (to CLK_2X_c +)
Delay: 10.193ns (26.1% logic, 73.9% route), 5 logic levels.
Constraint Details:
10.193ns physical path delay SLICE_20 to efb_impl/EFBInst_0 meets
20.833ns delay constraint less
3.115ns skew and
3.861ns WBSTBI_SET requirement (totaling 13.857ns) by 3.664ns
Physical Path Details:
Data path SLICE_20 to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_20 (from master_clk)
ROUTE 67 1.525 R3C8B.Q1 to R2C9D.B0 pc_1
CTOF_DEL --- 0.495 R2C9D.B0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2B.B0 code_data_6
CTOF_DEL --- 0.495 R2C2B.B0 to R2C2B.F0 SLICE_24
ROUTE 12 1.034 R2C2B.F0 to R3C2D.A1 WB_SEL
CTOF_DEL --- 0.495 R3C2D.A1 to R3C2D.F1 SLICE_18
ROUTE 1 1.948 R3C2D.F1 to EFB.WBSTBI wb_stb (to CLK_2X_c)
--------
10.193 (26.1% logic, 73.9% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_20:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Destination Clock Path CLK_2X to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.935 12.PADDI to EFB.WBCLKI CLK_2X_c
--------
4.307 (31.9% logic, 68.1% route), 1 logic levels.
Passed: The following path meets requirements by 3.672ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: EFB Port efb_impl/EFBInst_0(ASIC) (to CLK_2X_c +)
Delay: 10.185ns (26.1% logic, 73.9% route), 5 logic levels.
Constraint Details:
10.185ns physical path delay SLICE_20 to efb_impl/EFBInst_0 meets
20.833ns delay constraint less
3.115ns skew and
3.861ns WBSTBI_SET requirement (totaling 13.857ns) by 3.672ns
Physical Path Details:
Data path SLICE_20 to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_20 (from master_clk)
ROUTE 29 1.517 R3C8B.Q0 to R2C9D.D0 pc_0
CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2B.B0 code_data_6
CTOF_DEL --- 0.495 R2C2B.B0 to R2C2B.F0 SLICE_24
ROUTE 12 1.034 R2C2B.F0 to R3C2D.A1 WB_SEL
CTOF_DEL --- 0.495 R3C2D.A1 to R3C2D.F1 SLICE_18
ROUTE 1 1.948 R3C2D.F1 to EFB.WBSTBI wb_stb (to CLK_2X_c)
--------
10.185 (26.1% logic, 73.9% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_20:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Destination Clock Path CLK_2X to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.935 12.PADDI to EFB.WBCLKI CLK_2X_c
--------
4.307 (31.9% logic, 68.1% route), 1 logic levels.
Passed: The following path meets requirements by 3.728ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i2 (from master_clk +)
Destination: EFB Port efb_impl/EFBInst_0(ASIC) (to CLK_2X_c +)
Delay: 10.129ns (26.2% logic, 73.8% route), 5 logic levels.
Constraint Details:
10.129ns physical path delay SLICE_21 to efb_impl/EFBInst_0 meets
20.833ns delay constraint less
3.115ns skew and
3.861ns WBSTBI_SET requirement (totaling 13.857ns) by 3.728ns
Physical Path Details:
Data path SLICE_21 to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8C.CLK to R3C8C.Q0 SLICE_21 (from master_clk)
ROUTE 68 1.461 R3C8C.Q0 to R2C9D.A0 pc_2
CTOF_DEL --- 0.495 R2C9D.A0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2B.B0 code_data_6
CTOF_DEL --- 0.495 R2C2B.B0 to R2C2B.F0 SLICE_24
ROUTE 12 1.034 R2C2B.F0 to R3C2D.A1 WB_SEL
CTOF_DEL --- 0.495 R3C2D.A1 to R3C2D.F1 SLICE_18
ROUTE 1 1.948 R3C2D.F1 to EFB.WBSTBI wb_stb (to CLK_2X_c)
--------
10.129 (26.2% logic, 73.8% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_21:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8C.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Destination Clock Path CLK_2X to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.935 12.PADDI to EFB.WBCLKI CLK_2X_c
--------
4.307 (31.9% logic, 68.1% route), 1 logic levels.
Passed: The following path meets requirements by 3.954ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from master_clk +)
Destination: EFB Port efb_impl/EFBInst_0(ASIC) (to CLK_2X_c +)
Delay: 9.903ns (26.8% logic, 73.2% route), 5 logic levels.
Constraint Details:
9.903ns physical path delay SLICE_21 to efb_impl/EFBInst_0 meets
20.833ns delay constraint less
3.115ns skew and
3.861ns WBSTBI_SET requirement (totaling 13.857ns) by 3.954ns
Physical Path Details:
Data path SLICE_21 to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8C.CLK to R3C8C.Q1 SLICE_21 (from master_clk)
ROUTE 68 1.235 R3C8C.Q1 to R2C9D.C0 pc_3
CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2B.B0 code_data_6
CTOF_DEL --- 0.495 R2C2B.B0 to R2C2B.F0 SLICE_24
ROUTE 12 1.034 R2C2B.F0 to R3C2D.A1 WB_SEL
CTOF_DEL --- 0.495 R3C2D.A1 to R3C2D.F1 SLICE_18
ROUTE 1 1.948 R3C2D.F1 to EFB.WBSTBI wb_stb (to CLK_2X_c)
--------
9.903 (26.8% logic, 73.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_21:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8C.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Destination Clock Path CLK_2X to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.935 12.PADDI to EFB.WBCLKI CLK_2X_c
--------
4.307 (31.9% logic, 68.1% route), 1 logic levels.
Passed: The following path meets requirements by 4.271ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: EFB Port efb_impl/EFBInst_0(ASIC) (to CLK_2X_c +)
Delay: 9.586ns (30.2% logic, 69.8% route), 6 logic levels.
Constraint Details:
9.586ns physical path delay SLICE_20 to efb_impl/EFBInst_0 meets
20.833ns delay constraint less
3.115ns skew and
3.861ns WBSTBI_SET requirement (totaling 13.857ns) by 4.271ns
Physical Path Details:
Data path SLICE_20 to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_20 (from master_clk)
ROUTE 29 1.503 R3C8B.Q0 to R2C8A.B1 pc_0
CTOF_DEL --- 0.495 R2C8A.B1 to R2C8A.F1 rom_impl/SLICE_30
ROUTE 1 0.693 R2C8A.F1 to R2C8A.B0 rom_impl/n3094
CTOOFX_DEL --- 0.721 R2C8A.B0 to R2C8A.OFX0 rom_impl/SLICE_30
ROUTE 1 0.000 R2C8A.OFX0 to R2C8A.FXB rom_impl/n3472
FXTOOFX_DE --- 0.241 R2C8A.FXB to R2C8A.OFX1 rom_impl/SLICE_30
ROUTE 5 1.509 R2C8A.OFX1 to R2C2B.D0 code_data_4
CTOF_DEL --- 0.495 R2C2B.D0 to R2C2B.F0 SLICE_24
ROUTE 12 1.034 R2C2B.F0 to R3C2D.A1 WB_SEL
CTOF_DEL --- 0.495 R3C2D.A1 to R3C2D.F1 SLICE_18
ROUTE 1 1.948 R3C2D.F1 to EFB.WBSTBI wb_stb (to CLK_2X_c)
--------
9.586 (30.2% logic, 69.8% route), 6 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_20:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Destination Clock Path CLK_2X to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.935 12.PADDI to EFB.WBCLKI CLK_2X_c
--------
4.307 (31.9% logic, 68.1% route), 1 logic levels.
Passed: The following path meets requirements by 4.297ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i1 (from master_clk +)
Destination: EFB Port efb_impl/EFBInst_0(ASIC) (to CLK_2X_c +)
Delay: 9.560ns (30.3% logic, 69.7% route), 6 logic levels.
Constraint Details:
9.560ns physical path delay SLICE_20 to efb_impl/EFBInst_0 meets
20.833ns delay constraint less
3.115ns skew and
3.861ns WBSTBI_SET requirement (totaling 13.857ns) by 4.297ns
Physical Path Details:
Data path SLICE_20 to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_20 (from master_clk)
ROUTE 67 1.525 R3C8B.Q1 to R2C9D.B1 pc_1
CTOF_DEL --- 0.495 R2C9D.B1 to R2C9D.F1 SLICE_103
ROUTE 1 0.645 R2C9D.F1 to R2C8A.D0 rom_impl/n46_adj_11
CTOOFX_DEL --- 0.721 R2C8A.D0 to R2C8A.OFX0 rom_impl/SLICE_30
ROUTE 1 0.000 R2C8A.OFX0 to R2C8A.FXB rom_impl/n3472
FXTOOFX_DE --- 0.241 R2C8A.FXB to R2C8A.OFX1 rom_impl/SLICE_30
ROUTE 5 1.509 R2C8A.OFX1 to R2C2B.D0 code_data_4
CTOF_DEL --- 0.495 R2C2B.D0 to R2C2B.F0 SLICE_24
ROUTE 12 1.034 R2C2B.F0 to R3C2D.A1 WB_SEL
CTOF_DEL --- 0.495 R3C2D.A1 to R3C2D.F1 SLICE_18
ROUTE 1 1.948 R3C2D.F1 to EFB.WBSTBI wb_stb (to CLK_2X_c)
--------
9.560 (30.3% logic, 69.7% route), 6 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_20:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Destination Clock Path CLK_2X to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.935 12.PADDI to EFB.WBCLKI CLK_2X_c
--------
4.307 (31.9% logic, 68.1% route), 1 logic levels.
Passed: The following path meets requirements by 4.305ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: EFB Port efb_impl/EFBInst_0(ASIC) (to CLK_2X_c +)
Delay: 9.552ns (30.3% logic, 69.7% route), 6 logic levels.
Constraint Details:
9.552ns physical path delay SLICE_20 to efb_impl/EFBInst_0 meets
20.833ns delay constraint less
3.115ns skew and
3.861ns WBSTBI_SET requirement (totaling 13.857ns) by 4.305ns
Physical Path Details:
Data path SLICE_20 to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_20 (from master_clk)
ROUTE 29 1.517 R3C8B.Q0 to R2C9D.D1 pc_0
CTOF_DEL --- 0.495 R2C9D.D1 to R2C9D.F1 SLICE_103
ROUTE 1 0.645 R2C9D.F1 to R2C8A.D0 rom_impl/n46_adj_11
CTOOFX_DEL --- 0.721 R2C8A.D0 to R2C8A.OFX0 rom_impl/SLICE_30
ROUTE 1 0.000 R2C8A.OFX0 to R2C8A.FXB rom_impl/n3472
FXTOOFX_DE --- 0.241 R2C8A.FXB to R2C8A.OFX1 rom_impl/SLICE_30
ROUTE 5 1.509 R2C8A.OFX1 to R2C2B.D0 code_data_4
CTOF_DEL --- 0.495 R2C2B.D0 to R2C2B.F0 SLICE_24
ROUTE 12 1.034 R2C2B.F0 to R3C2D.A1 WB_SEL
CTOF_DEL --- 0.495 R3C2D.A1 to R3C2D.F1 SLICE_18
ROUTE 1 1.948 R3C2D.F1 to EFB.WBSTBI wb_stb (to CLK_2X_c)
--------
9.552 (30.3% logic, 69.7% route), 6 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_20:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Destination Clock Path CLK_2X to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.935 12.PADDI to EFB.WBCLKI CLK_2X_c
--------
4.307 (31.9% logic, 68.1% route), 1 logic levels.
Passed: The following path meets requirements by 4.361ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i2 (from master_clk +)
Destination: EFB Port efb_impl/EFBInst_0(ASIC) (to CLK_2X_c +)
Delay: 9.496ns (30.5% logic, 69.5% route), 6 logic levels.
Constraint Details:
9.496ns physical path delay SLICE_21 to efb_impl/EFBInst_0 meets
20.833ns delay constraint less
3.115ns skew and
3.861ns WBSTBI_SET requirement (totaling 13.857ns) by 4.361ns
Physical Path Details:
Data path SLICE_21 to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8C.CLK to R3C8C.Q0 SLICE_21 (from master_clk)
ROUTE 68 1.461 R3C8C.Q0 to R2C9D.A1 pc_2
CTOF_DEL --- 0.495 R2C9D.A1 to R2C9D.F1 SLICE_103
ROUTE 1 0.645 R2C9D.F1 to R2C8A.D0 rom_impl/n46_adj_11
CTOOFX_DEL --- 0.721 R2C8A.D0 to R2C8A.OFX0 rom_impl/SLICE_30
ROUTE 1 0.000 R2C8A.OFX0 to R2C8A.FXB rom_impl/n3472
FXTOOFX_DE --- 0.241 R2C8A.FXB to R2C8A.OFX1 rom_impl/SLICE_30
ROUTE 5 1.509 R2C8A.OFX1 to R2C2B.D0 code_data_4
CTOF_DEL --- 0.495 R2C2B.D0 to R2C2B.F0 SLICE_24
ROUTE 12 1.034 R2C2B.F0 to R3C2D.A1 WB_SEL
CTOF_DEL --- 0.495 R3C2D.A1 to R3C2D.F1 SLICE_18
ROUTE 1 1.948 R3C2D.F1 to EFB.WBSTBI wb_stb (to CLK_2X_c)
--------
9.496 (30.5% logic, 69.5% route), 6 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_21:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8C.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Destination Clock Path CLK_2X to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.935 12.PADDI to EFB.WBCLKI CLK_2X_c
--------
4.307 (31.9% logic, 68.1% route), 1 logic levels.
Passed: The following path meets requirements by 4.532ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from master_clk +)
Destination: EFB Port efb_impl/EFBInst_0(ASIC) (to CLK_2X_c +)
Delay: 9.325ns (31.1% logic, 68.9% route), 6 logic levels.
Constraint Details:
9.325ns physical path delay SLICE_21 to efb_impl/EFBInst_0 meets
20.833ns delay constraint less
3.115ns skew and
3.861ns WBSTBI_SET requirement (totaling 13.857ns) by 4.532ns
Physical Path Details:
Data path SLICE_21 to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8C.CLK to R3C8C.Q1 SLICE_21 (from master_clk)
ROUTE 68 1.242 R3C8C.Q1 to R2C8A.C1 pc_3
CTOF_DEL --- 0.495 R2C8A.C1 to R2C8A.F1 rom_impl/SLICE_30
ROUTE 1 0.693 R2C8A.F1 to R2C8A.B0 rom_impl/n3094
CTOOFX_DEL --- 0.721 R2C8A.B0 to R2C8A.OFX0 rom_impl/SLICE_30
ROUTE 1 0.000 R2C8A.OFX0 to R2C8A.FXB rom_impl/n3472
FXTOOFX_DE --- 0.241 R2C8A.FXB to R2C8A.OFX1 rom_impl/SLICE_30
ROUTE 5 1.509 R2C8A.OFX1 to R2C2B.D0 code_data_4
CTOF_DEL --- 0.495 R2C2B.D0 to R2C2B.F0 SLICE_24
ROUTE 12 1.034 R2C2B.F0 to R3C2D.A1 WB_SEL
CTOF_DEL --- 0.495 R3C2D.A1 to R3C2D.F1 SLICE_18
ROUTE 1 1.948 R3C2D.F1 to EFB.WBSTBI wb_stb (to CLK_2X_c)
--------
9.325 (31.1% logic, 68.9% route), 6 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_21:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8C.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Destination Clock Path CLK_2X to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.935 12.PADDI to EFB.WBCLKI CLK_2X_c
--------
4.307 (31.9% logic, 68.1% route), 1 logic levels.
Passed: The following path meets requirements by 4.587ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from master_clk +)
Destination: EFB Port efb_impl/EFBInst_0(ASIC) (to CLK_2X_c +)
Delay: 9.270ns (31.3% logic, 68.7% route), 6 logic levels.
Constraint Details:
9.270ns physical path delay SLICE_21 to efb_impl/EFBInst_0 meets
20.833ns delay constraint less
3.115ns skew and
3.861ns WBSTBI_SET requirement (totaling 13.857ns) by 4.587ns
Physical Path Details:
Data path SLICE_21 to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8C.CLK to R3C8C.Q1 SLICE_21 (from master_clk)
ROUTE 68 1.235 R3C8C.Q1 to R2C9D.C1 pc_3
CTOF_DEL --- 0.495 R2C9D.C1 to R2C9D.F1 SLICE_103
ROUTE 1 0.645 R2C9D.F1 to R2C8A.D0 rom_impl/n46_adj_11
CTOOFX_DEL --- 0.721 R2C8A.D0 to R2C8A.OFX0 rom_impl/SLICE_30
ROUTE 1 0.000 R2C8A.OFX0 to R2C8A.FXB rom_impl/n3472
FXTOOFX_DE --- 0.241 R2C8A.FXB to R2C8A.OFX1 rom_impl/SLICE_30
ROUTE 5 1.509 R2C8A.OFX1 to R2C2B.D0 code_data_4
CTOF_DEL --- 0.495 R2C2B.D0 to R2C2B.F0 SLICE_24
ROUTE 12 1.034 R2C2B.F0 to R3C2D.A1 WB_SEL
CTOF_DEL --- 0.495 R3C2D.A1 to R3C2D.F1 SLICE_18
ROUTE 1 1.948 R3C2D.F1 to EFB.WBSTBI wb_stb (to CLK_2X_c)
--------
9.270 (31.3% logic, 68.7% route), 6 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_21:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8C.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Destination Clock Path CLK_2X to efb_impl/EFBInst_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.935 12.PADDI to EFB.WBCLKI CLK_2X_c
--------
4.307 (31.9% logic, 68.1% route), 1 logic levels.
Report: 58.245MHz is the maximum frequency for this preference.
================================================================================
Preference: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 4.000000 X ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 60.030ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i1 (from master_clk +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 23.136ns (30.7% logic, 69.3% route), 14 logic levels.
Constraint Details:
23.136ns physical path delay SLICE_20 to SLICE_16 meets
83.332ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 83.166ns) by 60.030ns
Physical Path Details:
Data path SLICE_20 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_20 (from master_clk)
ROUTE 67 1.525 R3C8B.Q1 to R2C9D.B0 pc_1
CTOF_DEL --- 0.495 R2C9D.B0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2B.B0 code_data_6
CTOF_DEL --- 0.495 R2C2B.B0 to R2C2B.F0 SLICE_24
ROUTE 12 1.517 R2C2B.F0 to R3C4B.B0 WB_SEL
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.635 R4C4A.F1 to R4C4D.D0 F_7
CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
23.136 (30.7% logic, 69.3% route), 14 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 60.038ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 23.128ns (30.8% logic, 69.2% route), 14 logic levels.
Constraint Details:
23.128ns physical path delay SLICE_20 to SLICE_16 meets
83.332ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 83.166ns) by 60.038ns
Physical Path Details:
Data path SLICE_20 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_20 (from master_clk)
ROUTE 29 1.517 R3C8B.Q0 to R2C9D.D0 pc_0
CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2B.B0 code_data_6
CTOF_DEL --- 0.495 R2C2B.B0 to R2C2B.F0 SLICE_24
ROUTE 12 1.517 R2C2B.F0 to R3C4B.B0 WB_SEL
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.635 R4C4A.F1 to R4C4D.D0 F_7
CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
23.128 (30.8% logic, 69.2% route), 14 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 60.094ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i2 (from master_clk +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 23.072ns (30.8% logic, 69.2% route), 14 logic levels.
Constraint Details:
23.072ns physical path delay SLICE_21 to SLICE_16 meets
83.332ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 83.166ns) by 60.094ns
Physical Path Details:
Data path SLICE_21 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8C.CLK to R3C8C.Q0 SLICE_21 (from master_clk)
ROUTE 68 1.461 R3C8C.Q0 to R2C9D.A0 pc_2
CTOF_DEL --- 0.495 R2C9D.A0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2B.B0 code_data_6
CTOF_DEL --- 0.495 R2C2B.B0 to R2C2B.F0 SLICE_24
ROUTE 12 1.517 R2C2B.F0 to R3C4B.B0 WB_SEL
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.635 R4C4A.F1 to R4C4D.D0 F_7
CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
23.072 (30.8% logic, 69.2% route), 14 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R3C8C.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 60.320ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from master_clk +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 22.846ns (31.1% logic, 68.9% route), 14 logic levels.
Constraint Details:
22.846ns physical path delay SLICE_21 to SLICE_16 meets
83.332ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 83.166ns) by 60.320ns
Physical Path Details:
Data path SLICE_21 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8C.CLK to R3C8C.Q1 SLICE_21 (from master_clk)
ROUTE 68 1.235 R3C8C.Q1 to R2C9D.C0 pc_3
CTOF_DEL --- 0.495 R2C9D.C0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2B.B0 code_data_6
CTOF_DEL --- 0.495 R2C2B.B0 to R2C2B.F0 SLICE_24
ROUTE 12 1.517 R2C2B.F0 to R3C4B.B0 WB_SEL
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.635 R4C4A.F1 to R4C4D.D0 F_7
CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
22.846 (31.1% logic, 68.9% route), 14 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R3C8C.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 60.512ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i1 (from master_clk +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 22.654ns (33.6% logic, 66.4% route), 15 logic levels.
Constraint Details:
22.654ns physical path delay SLICE_20 to SLICE_16 meets
83.332ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 83.166ns) by 60.512ns
Physical Path Details:
Data path SLICE_20 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_20 (from master_clk)
ROUTE 67 1.525 R3C8B.Q1 to R2C9D.B0 pc_1
CTOF_DEL --- 0.495 R2C9D.B0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2B.B0 code_data_6
CTOF_DEL --- 0.495 R2C2B.B0 to R2C2B.F0 SLICE_24
ROUTE 12 1.546 R2C2B.F0 to R3C5C.A0 WB_SEL
CTOF_DEL --- 0.495 R3C5C.A0 to R3C5C.F0 alu_impl/SLICE_95
ROUTE 2 0.756 R3C5C.F0 to R3C5D.C0 alu_impl/I_DATA_0
CTOF_DEL --- 0.495 R3C5D.C0 to R3C5D.F0 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 3 0.445 R3C5D.F0 to R3C5D.C1 n52_adj_25
CTOF_DEL --- 0.495 R3C5D.C1 to R3C5D.F1 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 1 1.004 R3C5D.F1 to R3C5B.B1 alu_impl/alu_impl/alu_lo/n2077
CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.635 R4C4A.F1 to R4C4D.D0 F_7
CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
22.654 (33.6% logic, 66.4% route), 15 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 60.514ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 22.652ns (30.3% logic, 69.7% route), 14 logic levels.
Constraint Details:
22.652ns physical path delay SLICE_20 to SLICE_16 meets
83.332ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 83.166ns) by 60.514ns
Physical Path Details:
Data path SLICE_20 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_20 (from master_clk)
ROUTE 29 1.870 R3C8B.Q0 to R5C7C.A1 pc_0
CTOOFX_DEL --- 0.721 R5C7C.A1 to R5C7C.OFX0 rom_impl/i2684/SLICE_32
ROUTE 1 0.000 R5C7C.OFX0 to R5C7C.FXB rom_impl/n3475
FXTOOFX_DE --- 0.241 R5C7C.FXB to R5C7C.OFX1 rom_impl/i2684/SLICE_32
ROUTE 16 2.556 R5C7C.OFX1 to R3C3C.D0 code_data_7
CTOF_DEL --- 0.495 R3C3C.D0 to R3C3C.F0 SLICE_87
ROUTE 8 3.176 R3C3C.F0 to R3C5D.B0 FS_2
CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 3 0.445 R3C5D.F0 to R3C5D.C1 n52_adj_25
CTOF_DEL --- 0.495 R3C5D.C1 to R3C5D.F1 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 1 1.004 R3C5D.F1 to R3C5B.B1 alu_impl/alu_impl/alu_lo/n2077
CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.635 R4C4A.F1 to R4C4D.D0 F_7
CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
22.652 (30.3% logic, 69.7% route), 14 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 60.514ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 22.652ns (30.3% logic, 69.7% route), 14 logic levels.
Constraint Details:
22.652ns physical path delay SLICE_20 to SLICE_16 meets
83.332ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 83.166ns) by 60.514ns
Physical Path Details:
Data path SLICE_20 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_20 (from master_clk)
ROUTE 29 1.870 R3C8B.Q0 to R5C7C.A0 pc_0
CTOOFX_DEL --- 0.721 R5C7C.A0 to R5C7C.OFX0 rom_impl/i2684/SLICE_32
ROUTE 1 0.000 R5C7C.OFX0 to R5C7C.FXB rom_impl/n3475
FXTOOFX_DE --- 0.241 R5C7C.FXB to R5C7C.OFX1 rom_impl/i2684/SLICE_32
ROUTE 16 2.556 R5C7C.OFX1 to R3C3C.D0 code_data_7
CTOF_DEL --- 0.495 R3C3C.D0 to R3C3C.F0 SLICE_87
ROUTE 8 3.176 R3C3C.F0 to R3C5D.B0 FS_2
CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 3 0.445 R3C5D.F0 to R3C5D.C1 n52_adj_25
CTOF_DEL --- 0.495 R3C5D.C1 to R3C5D.F1 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 1 1.004 R3C5D.F1 to R3C5B.B1 alu_impl/alu_impl/alu_lo/n2077
CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.635 R4C4A.F1 to R4C4D.D0 F_7
CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
22.652 (30.3% logic, 69.7% route), 14 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 60.520ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 22.646ns (33.6% logic, 66.4% route), 15 logic levels.
Constraint Details:
22.646ns physical path delay SLICE_20 to SLICE_16 meets
83.332ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 83.166ns) by 60.520ns
Physical Path Details:
Data path SLICE_20 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_20 (from master_clk)
ROUTE 29 1.517 R3C8B.Q0 to R2C9D.D0 pc_0
CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2B.B0 code_data_6
CTOF_DEL --- 0.495 R2C2B.B0 to R2C2B.F0 SLICE_24
ROUTE 12 1.546 R2C2B.F0 to R3C5C.A0 WB_SEL
CTOF_DEL --- 0.495 R3C5C.A0 to R3C5C.F0 alu_impl/SLICE_95
ROUTE 2 0.756 R3C5C.F0 to R3C5D.C0 alu_impl/I_DATA_0
CTOF_DEL --- 0.495 R3C5D.C0 to R3C5D.F0 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 3 0.445 R3C5D.F0 to R3C5D.C1 n52_adj_25
CTOF_DEL --- 0.495 R3C5D.C1 to R3C5D.F1 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 1 1.004 R3C5D.F1 to R3C5B.B1 alu_impl/alu_impl/alu_lo/n2077
CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.635 R4C4A.F1 to R4C4D.D0 F_7
CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
22.646 (33.6% logic, 66.4% route), 15 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 60.522ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i1 (from master_clk +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 22.644ns (27.0% logic, 73.0% route), 12 logic levels.
Constraint Details:
22.644ns physical path delay SLICE_20 to SLICE_16 meets
83.332ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 83.166ns) by 60.522ns
Physical Path Details:
Data path SLICE_20 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_20 (from master_clk)
ROUTE 67 1.525 R3C8B.Q1 to R2C9D.B0 pc_1
CTOF_DEL --- 0.495 R2C9D.B0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2B.B0 code_data_6
CTOF_DEL --- 0.495 R2C2B.B0 to R2C2B.F0 SLICE_24
ROUTE 12 1.517 R2C2B.F0 to R3C4B.B0 WB_SEL
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.710 R4C6A.F0 to R4C6B.B1 n2083
CTOF_DEL --- 0.495 R4C6B.B1 to R4C6B.F1 alu_impl/SLICE_109
ROUTE 2 1.476 R4C6B.F1 to R4C3D.D0 n2143
CTOF_DEL --- 0.495 R4C3D.D0 to R4C3D.F0 SLICE_82
ROUTE 2 1.934 R4C3D.F0 to R4C6B.A0 F_4
CTOF_DEL --- 0.495 R4C6B.A0 to R4C6B.F0 alu_impl/SLICE_109
ROUTE 1 1.812 R4C6B.F0 to R4C5A.D0 alu_impl/n3447
CTOF_DEL --- 0.495 R4C5A.D0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
22.644 (27.0% logic, 73.0% route), 12 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 60.530ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 22.636ns (27.0% logic, 73.0% route), 12 logic levels.
Constraint Details:
22.636ns physical path delay SLICE_20 to SLICE_16 meets
83.332ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 83.166ns) by 60.530ns
Physical Path Details:
Data path SLICE_20 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_20 (from master_clk)
ROUTE 29 1.517 R3C8B.Q0 to R2C9D.D0 pc_0
CTOF_DEL --- 0.495 R2C9D.D0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2B.B0 code_data_6
CTOF_DEL --- 0.495 R2C2B.B0 to R2C2B.F0 SLICE_24
ROUTE 12 1.517 R2C2B.F0 to R3C4B.B0 WB_SEL
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.710 R4C6A.F0 to R4C6B.B1 n2083
CTOF_DEL --- 0.495 R4C6B.B1 to R4C6B.F1 alu_impl/SLICE_109
ROUTE 2 1.476 R4C6B.F1 to R4C3D.D0 n2143
CTOF_DEL --- 0.495 R4C3D.D0 to R4C3D.F0 SLICE_82
ROUTE 2 1.934 R4C3D.F0 to R4C6B.A0 F_4
CTOF_DEL --- 0.495 R4C6B.A0 to R4C6B.F0 alu_impl/SLICE_109
ROUTE 1 1.812 R4C6B.F0 to R4C5A.D0 alu_impl/n3447
CTOF_DEL --- 0.495 R4C5A.D0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
22.636 (27.0% logic, 73.0% route), 12 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: MULTICYCLE FROM GROUP "efb" TO GROUP "akku" 2.000000 X ;
160 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 28.466ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i1 (from CLK_2X_c +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 16.322ns (33.1% logic, 66.9% route), 11 logic levels.
Constraint Details:
16.322ns physical path delay SLICE_90 to SLICE_16 meets
41.666ns delay constraint less
-3.288ns skew and
0.166ns DIN_SET requirement (totaling 44.788ns) by 28.466ns
Physical Path Details:
Data path SLICE_90 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C4A.CLK to R3C4A.Q1 SLICE_90 (from CLK_2X_c)
ROUTE 1 0.967 R3C4A.Q1 to R3C4B.A0 wb_data_l_1
CTOF_DEL --- 0.495 R3C4B.A0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.635 R4C4A.F1 to R4C4D.D0 F_7
CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
16.322 (33.1% logic, 66.9% route), 11 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_90:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R3C4A.CLK CLK_2X_c
--------
4.134 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 28.958ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i1 (from CLK_2X_c +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 15.830ns (27.9% logic, 72.1% route), 9 logic levels.
Constraint Details:
15.830ns physical path delay SLICE_90 to SLICE_16 meets
41.666ns delay constraint less
-3.288ns skew and
0.166ns DIN_SET requirement (totaling 44.788ns) by 28.958ns
Physical Path Details:
Data path SLICE_90 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C4A.CLK to R3C4A.Q1 SLICE_90 (from CLK_2X_c)
ROUTE 1 0.967 R3C4A.Q1 to R3C4B.A0 wb_data_l_1
CTOF_DEL --- 0.495 R3C4B.A0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.710 R4C6A.F0 to R4C6B.B1 n2083
CTOF_DEL --- 0.495 R4C6B.B1 to R4C6B.F1 alu_impl/SLICE_109
ROUTE 2 1.476 R4C6B.F1 to R4C3D.D0 n2143
CTOF_DEL --- 0.495 R4C3D.D0 to R4C3D.F0 SLICE_82
ROUTE 2 1.934 R4C3D.F0 to R4C6B.A0 F_4
CTOF_DEL --- 0.495 R4C6B.A0 to R4C6B.F0 alu_impl/SLICE_109
ROUTE 1 1.812 R4C6B.F0 to R4C5A.D0 alu_impl/n3447
CTOF_DEL --- 0.495 R4C5A.D0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
15.830 (27.9% logic, 72.1% route), 9 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_90:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R3C4A.CLK CLK_2X_c
--------
4.134 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 29.178ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i0 (from CLK_2X_c +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 15.610ns (37.8% logic, 62.2% route), 12 logic levels.
Constraint Details:
15.610ns physical path delay SLICE_90 to SLICE_16 meets
41.666ns delay constraint less
-3.288ns skew and
0.166ns DIN_SET requirement (totaling 44.788ns) by 29.178ns
Physical Path Details:
Data path SLICE_90 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C4A.CLK to R3C4A.Q0 SLICE_90 (from CLK_2X_c)
ROUTE 1 0.766 R3C4A.Q0 to R3C5C.C0 wb_data_l_0
CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 alu_impl/SLICE_95
ROUTE 2 0.756 R3C5C.F0 to R3C5D.C0 alu_impl/I_DATA_0
CTOF_DEL --- 0.495 R3C5D.C0 to R3C5D.F0 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 3 0.445 R3C5D.F0 to R3C5D.C1 n52_adj_25
CTOF_DEL --- 0.495 R3C5D.C1 to R3C5D.F1 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 1 1.004 R3C5D.F1 to R3C5B.B1 alu_impl/alu_impl/alu_lo/n2077
CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.635 R4C4A.F1 to R4C4D.D0 F_7
CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
15.610 (37.8% logic, 62.2% route), 12 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_90:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R3C4A.CLK CLK_2X_c
--------
4.134 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 29.250ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i1 (from CLK_2X_c +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 15.538ns (31.6% logic, 68.4% route), 10 logic levels.
Constraint Details:
15.538ns physical path delay SLICE_90 to SLICE_16 meets
41.666ns delay constraint less
-3.288ns skew and
0.166ns DIN_SET requirement (totaling 44.788ns) by 29.250ns
Physical Path Details:
Data path SLICE_90 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C4A.CLK to R3C4A.Q1 SLICE_90 (from CLK_2X_c)
ROUTE 1 0.967 R3C4A.Q1 to R3C4B.A0 wb_data_l_1
CTOF_DEL --- 0.495 R3C4B.A0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.710 R4C6A.F0 to R4C6B.B1 n2083
CTOF_DEL --- 0.495 R4C6B.B1 to R4C6B.F1 alu_impl/SLICE_109
ROUTE 2 1.457 R4C6B.F1 to R4C3C.B1 n2143
CTOF_DEL --- 0.495 R4C3C.B1 to R4C3C.F1 SLICE_80
ROUTE 1 1.004 R4C3C.F1 to R4C3C.B0 n2185
CTOF_DEL --- 0.495 R4C3C.B0 to R4C3C.F0 SLICE_80
ROUTE 2 0.973 R4C3C.F0 to R4C4D.A0 F_5
CTOF_DEL --- 0.495 R4C4D.A0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
15.538 (31.6% logic, 68.4% route), 10 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_90:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R3C4A.CLK CLK_2X_c
--------
4.134 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 29.670ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i0 (from CLK_2X_c +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 15.118ns (32.5% logic, 67.5% route), 10 logic levels.
Constraint Details:
15.118ns physical path delay SLICE_90 to SLICE_16 meets
41.666ns delay constraint less
-3.288ns skew and
0.166ns DIN_SET requirement (totaling 44.788ns) by 29.670ns
Physical Path Details:
Data path SLICE_90 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C4A.CLK to R3C4A.Q0 SLICE_90 (from CLK_2X_c)
ROUTE 1 0.766 R3C4A.Q0 to R3C5C.C0 wb_data_l_0
CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 alu_impl/SLICE_95
ROUTE 2 0.756 R3C5C.F0 to R3C5D.C0 alu_impl/I_DATA_0
CTOF_DEL --- 0.495 R3C5D.C0 to R3C5D.F0 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 3 0.445 R3C5D.F0 to R3C5D.C1 n52_adj_25
CTOF_DEL --- 0.495 R3C5D.C1 to R3C5D.F1 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 1 1.004 R3C5D.F1 to R3C5B.B1 alu_impl/alu_impl/alu_lo/n2077
CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.710 R4C6A.F0 to R4C6B.B1 n2083
CTOF_DEL --- 0.495 R4C6B.B1 to R4C6B.F1 alu_impl/SLICE_109
ROUTE 2 1.476 R4C6B.F1 to R4C3D.D0 n2143
CTOF_DEL --- 0.495 R4C3D.D0 to R4C3D.F0 SLICE_82
ROUTE 2 1.934 R4C3D.F0 to R4C6B.A0 F_4
CTOF_DEL --- 0.495 R4C6B.A0 to R4C6B.F0 alu_impl/SLICE_109
ROUTE 1 1.812 R4C6B.F0 to R4C5A.D0 alu_impl/n3447
CTOF_DEL --- 0.495 R4C5A.D0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
15.118 (32.5% logic, 67.5% route), 10 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_90:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R3C4A.CLK CLK_2X_c
--------
4.134 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 29.895ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i1 (from CLK_2X_c +)
Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i7 (to master_clk +)
Delay: 14.893ns (32.9% logic, 67.1% route), 10 logic levels.
Constraint Details:
14.893ns physical path delay SLICE_90 to alu_impl_I/alu_impl/alu_hi/SLICE_14 meets
41.666ns delay constraint less
-3.288ns skew and
0.166ns DIN_SET requirement (totaling 44.788ns) by 29.895ns
Physical Path Details:
Data path SLICE_90 to alu_impl_I/alu_impl/alu_hi/SLICE_14:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C4A.CLK to R3C4A.Q1 SLICE_90 (from CLK_2X_c)
ROUTE 1 0.967 R3C4A.Q1 to R3C4B.A0 wb_data_l_1
CTOF_DEL --- 0.495 R3C4B.A0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.702 R4C4A.F1 to R4C4A.B0 F_7
CTOF_DEL --- 0.495 R4C4A.B0 to R4C4A.F0 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 1 0.000 R4C4A.F0 to R4C4A.DI0 alu_impl_I/alu_impl/alu_hi/n1359 (to master_clk)
--------
14.893 (32.9% logic, 67.1% route), 10 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_90:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R3C4A.CLK CLK_2X_c
--------
4.134 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_hi/SLICE_14:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C4A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 29.962ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i0 (from CLK_2X_c +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 14.826ns (36.4% logic, 63.6% route), 11 logic levels.
Constraint Details:
14.826ns physical path delay SLICE_90 to SLICE_16 meets
41.666ns delay constraint less
-3.288ns skew and
0.166ns DIN_SET requirement (totaling 44.788ns) by 29.962ns
Physical Path Details:
Data path SLICE_90 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C4A.CLK to R3C4A.Q0 SLICE_90 (from CLK_2X_c)
ROUTE 1 0.766 R3C4A.Q0 to R3C5C.C0 wb_data_l_0
CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 alu_impl/SLICE_95
ROUTE 2 0.756 R3C5C.F0 to R3C5D.C0 alu_impl/I_DATA_0
CTOF_DEL --- 0.495 R3C5D.C0 to R3C5D.F0 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 3 0.445 R3C5D.F0 to R3C5D.C1 n52_adj_25
CTOF_DEL --- 0.495 R3C5D.C1 to R3C5D.F1 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 1 1.004 R3C5D.F1 to R3C5B.B1 alu_impl/alu_impl/alu_lo/n2077
CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.710 R4C6A.F0 to R4C6B.B1 n2083
CTOF_DEL --- 0.495 R4C6B.B1 to R4C6B.F1 alu_impl/SLICE_109
ROUTE 2 1.457 R4C6B.F1 to R4C3C.B1 n2143
CTOF_DEL --- 0.495 R4C3C.B1 to R4C3C.F1 SLICE_80
ROUTE 1 1.004 R4C3C.F1 to R4C3C.B0 n2185
CTOF_DEL --- 0.495 R4C3C.B0 to R4C3C.F0 SLICE_80
ROUTE 2 0.973 R4C3C.F0 to R4C4D.A0 F_5
CTOF_DEL --- 0.495 R4C4D.A0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
14.826 (36.4% logic, 63.6% route), 11 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_90:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R3C4A.CLK CLK_2X_c
--------
4.134 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 30.254ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i1 (from CLK_2X_c +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 14.534ns (37.2% logic, 62.8% route), 11 logic levels.
Constraint Details:
14.534ns physical path delay SLICE_90 to SLICE_16 meets
41.666ns delay constraint less
-3.288ns skew and
0.166ns DIN_SET requirement (totaling 44.788ns) by 30.254ns
Physical Path Details:
Data path SLICE_90 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C4A.CLK to R3C4A.Q1 SLICE_90 (from CLK_2X_c)
ROUTE 1 0.967 R3C4A.Q1 to R3C4B.A0 wb_data_l_1
CTOF_DEL --- 0.495 R3C4B.A0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 0.445 R3C4B.F0 to R3C4B.C1 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C4B.C1 to R3C4B.F1 alu_impl/SLICE_96
ROUTE 2 0.978 R3C4B.F1 to R3C5B.A1 n1255
CTOF_DEL --- 0.495 R3C5B.A1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.635 R4C4A.F1 to R4C4D.D0 F_7
CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
14.534 (37.2% logic, 62.8% route), 11 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_90:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R3C4A.CLK CLK_2X_c
--------
4.134 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 30.484ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i1 (from CLK_2X_c +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 14.304ns (32.4% logic, 67.6% route), 9 logic levels.
Constraint Details:
14.304ns physical path delay SLICE_90 to SLICE_15 meets
41.666ns delay constraint less
-3.288ns skew and
0.166ns DIN_SET requirement (totaling 44.788ns) by 30.484ns
Physical Path Details:
Data path SLICE_90 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C4A.CLK to R3C4A.Q1 SLICE_90 (from CLK_2X_c)
ROUTE 1 0.967 R3C4A.Q1 to R3C4B.A0 wb_data_l_1
CTOF_DEL --- 0.495 R3C4B.A0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.392 R4C3A.F0 to R4C4C.A0 n2175
CTOOFX_DEL --- 0.721 R4C4C.A0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
14.304 (32.4% logic, 67.6% route), 9 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_90:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R3C4A.CLK CLK_2X_c
--------
4.134 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to SLICE_15:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C4C.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 30.607ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i0 (from CLK_2X_c +)
Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i7 (to master_clk +)
Delay: 14.181ns (38.1% logic, 61.9% route), 11 logic levels.
Constraint Details:
14.181ns physical path delay SLICE_90 to alu_impl_I/alu_impl/alu_hi/SLICE_14 meets
41.666ns delay constraint less
-3.288ns skew and
0.166ns DIN_SET requirement (totaling 44.788ns) by 30.607ns
Physical Path Details:
Data path SLICE_90 to alu_impl_I/alu_impl/alu_hi/SLICE_14:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C4A.CLK to R3C4A.Q0 SLICE_90 (from CLK_2X_c)
ROUTE 1 0.766 R3C4A.Q0 to R3C5C.C0 wb_data_l_0
CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 alu_impl/SLICE_95
ROUTE 2 0.756 R3C5C.F0 to R3C5D.C0 alu_impl/I_DATA_0
CTOF_DEL --- 0.495 R3C5D.C0 to R3C5D.F0 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 3 0.445 R3C5D.F0 to R3C5D.C1 n52_adj_25
CTOF_DEL --- 0.495 R3C5D.C1 to R3C5D.F1 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 1 1.004 R3C5D.F1 to R3C5B.B1 alu_impl/alu_impl/alu_lo/n2077
CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.702 R4C4A.F1 to R4C4A.B0 F_7
CTOF_DEL --- 0.495 R4C4A.B0 to R4C4A.F0 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 1 0.000 R4C4A.F0 to R4C4A.DI0 alu_impl_I/alu_impl/alu_hi/n1359 (to master_clk)
--------
14.181 (38.1% logic, 61.9% route), 11 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_90:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R3C4A.CLK CLK_2X_c
--------
4.134 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_hi/SLICE_14:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C4A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
================================================================================
Preference: MULTICYCLE FROM CLKNET "WE_mem" 6.000000 X ;
160 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 98.046ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 17.464ns (36.3% logic, 63.7% route), 11 logic levels.
Constraint Details:
17.464ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets
124.998ns delay constraint less
9.322ns skew and
0.166ns DIN_SET requirement (totaling 115.510ns) by 98.046ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R2C4A.WCK to R2C4A.F1 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 1 1.163 R2C4A.F1 to R3C4B.C0 mem_data_1
CTOF_DEL --- 0.495 R3C4B.C0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.635 R4C4A.F1 to R4C4D.D0 F_7
CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
17.464 (36.3% logic, 63.7% route), 11 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_20
ROUTE 67 1.525 R3C8B.Q1 to R2C9D.B0 pc_1
CTOF_DEL --- 0.495 R2C9D.B0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.495 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.656 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.495 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.324 R2C2A.F1 to R2C2B.D1 n9
CTOF_DEL --- 0.495 R2C2B.D1 to R2C2B.F1 SLICE_24
ROUTE 4 0.636 R2C2B.F1 to R2C4A.WCK WE_mem
--------
16.744 (29.7% logic, 70.3% route), 8 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 98.365ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 17.145ns (39.9% logic, 60.1% route), 12 logic levels.
Constraint Details:
17.145ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets
124.998ns delay constraint less
9.322ns skew and
0.166ns DIN_SET requirement (totaling 115.510ns) by 98.365ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R2C4A.WCK to R2C4A.F0 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 1 1.355 R2C4A.F0 to R3C5C.D0 mem_data_0
CTOF_DEL --- 0.495 R3C5C.D0 to R3C5C.F0 alu_impl/SLICE_95
ROUTE 2 0.756 R3C5C.F0 to R3C5D.C0 alu_impl/I_DATA_0
CTOF_DEL --- 0.495 R3C5D.C0 to R3C5D.F0 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 3 0.445 R3C5D.F0 to R3C5D.C1 n52_adj_25
CTOF_DEL --- 0.495 R3C5D.C1 to R3C5D.F1 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 1 1.004 R3C5D.F1 to R3C5B.B1 alu_impl/alu_impl/alu_lo/n2077
CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.635 R4C4A.F1 to R4C4D.D0 F_7
CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
17.145 (39.9% logic, 60.1% route), 12 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_20
ROUTE 67 1.525 R3C8B.Q1 to R2C9D.B0 pc_1
CTOF_DEL --- 0.495 R2C9D.B0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.495 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.656 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.495 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.324 R2C2A.F1 to R2C2B.D1 n9
CTOF_DEL --- 0.495 R2C2B.D1 to R2C2B.F1 SLICE_24
ROUTE 4 0.636 R2C2B.F1 to R2C4A.WCK WE_mem
--------
16.744 (29.7% logic, 70.3% route), 8 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 98.538ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 16.972ns (31.6% logic, 68.4% route), 9 logic levels.
Constraint Details:
16.972ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets
124.998ns delay constraint less
9.322ns skew and
0.166ns DIN_SET requirement (totaling 115.510ns) by 98.538ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R2C4A.WCK to R2C4A.F1 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 1 1.163 R2C4A.F1 to R3C4B.C0 mem_data_1
CTOF_DEL --- 0.495 R3C4B.C0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.710 R4C6A.F0 to R4C6B.B1 n2083
CTOF_DEL --- 0.495 R4C6B.B1 to R4C6B.F1 alu_impl/SLICE_109
ROUTE 2 1.476 R4C6B.F1 to R4C3D.D0 n2143
CTOF_DEL --- 0.495 R4C3D.D0 to R4C3D.F0 SLICE_82
ROUTE 2 1.934 R4C3D.F0 to R4C6B.A0 F_4
CTOF_DEL --- 0.495 R4C6B.A0 to R4C6B.F0 alu_impl/SLICE_109
ROUTE 1 1.812 R4C6B.F0 to R4C5A.D0 alu_impl/n3447
CTOF_DEL --- 0.495 R4C5A.D0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
16.972 (31.6% logic, 68.4% route), 9 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_20
ROUTE 67 1.525 R3C8B.Q1 to R2C9D.B0 pc_1
CTOF_DEL --- 0.495 R2C9D.B0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.495 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.656 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.495 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.324 R2C2A.F1 to R2C2B.D1 n9
CTOF_DEL --- 0.495 R2C2B.D1 to R2C2B.F1 SLICE_24
ROUTE 4 0.636 R2C2B.F1 to R2C4A.WCK WE_mem
--------
16.744 (29.7% logic, 70.3% route), 8 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 98.830ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 16.680ns (35.1% logic, 64.9% route), 10 logic levels.
Constraint Details:
16.680ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets
124.998ns delay constraint less
9.322ns skew and
0.166ns DIN_SET requirement (totaling 115.510ns) by 98.830ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R2C4A.WCK to R2C4A.F1 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 1 1.163 R2C4A.F1 to R3C4B.C0 mem_data_1
CTOF_DEL --- 0.495 R3C4B.C0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.710 R4C6A.F0 to R4C6B.B1 n2083
CTOF_DEL --- 0.495 R4C6B.B1 to R4C6B.F1 alu_impl/SLICE_109
ROUTE 2 1.457 R4C6B.F1 to R4C3C.B1 n2143
CTOF_DEL --- 0.495 R4C3C.B1 to R4C3C.F1 SLICE_80
ROUTE 1 1.004 R4C3C.F1 to R4C3C.B0 n2185
CTOF_DEL --- 0.495 R4C3C.B0 to R4C3C.F0 SLICE_80
ROUTE 2 0.973 R4C3C.F0 to R4C4D.A0 F_5
CTOF_DEL --- 0.495 R4C4D.A0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
16.680 (35.1% logic, 64.9% route), 10 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_20
ROUTE 67 1.525 R3C8B.Q1 to R2C9D.B0 pc_1
CTOF_DEL --- 0.495 R2C9D.B0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.495 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.656 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.495 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.324 R2C2A.F1 to R2C2B.D1 n9
CTOF_DEL --- 0.495 R2C2B.D1 to R2C2B.F1 SLICE_24
ROUTE 4 0.636 R2C2B.F1 to R2C4A.WCK WE_mem
--------
16.744 (29.7% logic, 70.3% route), 8 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 98.857ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 16.653ns (35.1% logic, 64.9% route), 10 logic levels.
Constraint Details:
16.653ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets
124.998ns delay constraint less
9.322ns skew and
0.166ns DIN_SET requirement (totaling 115.510ns) by 98.857ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R2C4A.WCK to R2C4A.F0 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 1 1.355 R2C4A.F0 to R3C5C.D0 mem_data_0
CTOF_DEL --- 0.495 R3C5C.D0 to R3C5C.F0 alu_impl/SLICE_95
ROUTE 2 0.756 R3C5C.F0 to R3C5D.C0 alu_impl/I_DATA_0
CTOF_DEL --- 0.495 R3C5D.C0 to R3C5D.F0 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 3 0.445 R3C5D.F0 to R3C5D.C1 n52_adj_25
CTOF_DEL --- 0.495 R3C5D.C1 to R3C5D.F1 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 1 1.004 R3C5D.F1 to R3C5B.B1 alu_impl/alu_impl/alu_lo/n2077
CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.710 R4C6A.F0 to R4C6B.B1 n2083
CTOF_DEL --- 0.495 R4C6B.B1 to R4C6B.F1 alu_impl/SLICE_109
ROUTE 2 1.476 R4C6B.F1 to R4C3D.D0 n2143
CTOF_DEL --- 0.495 R4C3D.D0 to R4C3D.F0 SLICE_82
ROUTE 2 1.934 R4C3D.F0 to R4C6B.A0 F_4
CTOF_DEL --- 0.495 R4C6B.A0 to R4C6B.F0 alu_impl/SLICE_109
ROUTE 1 1.812 R4C6B.F0 to R4C5A.D0 alu_impl/n3447
CTOF_DEL --- 0.495 R4C5A.D0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
16.653 (35.1% logic, 64.9% route), 10 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_20
ROUTE 67 1.525 R3C8B.Q1 to R2C9D.B0 pc_1
CTOF_DEL --- 0.495 R2C9D.B0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.495 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.656 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.495 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.324 R2C2A.F1 to R2C2B.D1 n9
CTOF_DEL --- 0.495 R2C2B.D1 to R2C2B.F1 SLICE_24
ROUTE 4 0.636 R2C2B.F1 to R2C4A.WCK WE_mem
--------
16.744 (29.7% logic, 70.3% route), 8 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 99.149ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 16.361ns (38.8% logic, 61.2% route), 11 logic levels.
Constraint Details:
16.361ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets
124.998ns delay constraint less
9.322ns skew and
0.166ns DIN_SET requirement (totaling 115.510ns) by 99.149ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R2C4A.WCK to R2C4A.F0 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 1 1.355 R2C4A.F0 to R3C5C.D0 mem_data_0
CTOF_DEL --- 0.495 R3C5C.D0 to R3C5C.F0 alu_impl/SLICE_95
ROUTE 2 0.756 R3C5C.F0 to R3C5D.C0 alu_impl/I_DATA_0
CTOF_DEL --- 0.495 R3C5D.C0 to R3C5D.F0 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 3 0.445 R3C5D.F0 to R3C5D.C1 n52_adj_25
CTOF_DEL --- 0.495 R3C5D.C1 to R3C5D.F1 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 1 1.004 R3C5D.F1 to R3C5B.B1 alu_impl/alu_impl/alu_lo/n2077
CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.710 R4C6A.F0 to R4C6B.B1 n2083
CTOF_DEL --- 0.495 R4C6B.B1 to R4C6B.F1 alu_impl/SLICE_109
ROUTE 2 1.457 R4C6B.F1 to R4C3C.B1 n2143
CTOF_DEL --- 0.495 R4C3C.B1 to R4C3C.F1 SLICE_80
ROUTE 1 1.004 R4C3C.F1 to R4C3C.B0 n2185
CTOF_DEL --- 0.495 R4C3C.B0 to R4C3C.F0 SLICE_80
ROUTE 2 0.973 R4C3C.F0 to R4C4D.A0 F_5
CTOF_DEL --- 0.495 R4C4D.A0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
16.361 (38.8% logic, 61.2% route), 11 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_20
ROUTE 67 1.525 R3C8B.Q1 to R2C9D.B0 pc_1
CTOF_DEL --- 0.495 R2C9D.B0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.495 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.656 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.495 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.324 R2C2A.F1 to R2C2B.D1 n9
CTOF_DEL --- 0.495 R2C2B.D1 to R2C2B.F1 SLICE_24
ROUTE 4 0.636 R2C2B.F1 to R2C4A.WCK WE_mem
--------
16.744 (29.7% logic, 70.3% route), 8 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 99.475ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i7 (to master_clk +)
Delay: 16.035ns (36.5% logic, 63.5% route), 10 logic levels.
Constraint Details:
16.035ns physical path delay sram_impl/mem1/SLICE_8 to alu_impl_I/alu_impl/alu_hi/SLICE_14 meets
124.998ns delay constraint less
9.322ns skew and
0.166ns DIN_SET requirement (totaling 115.510ns) by 99.475ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to alu_impl_I/alu_impl/alu_hi/SLICE_14:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R2C4A.WCK to R2C4A.F1 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 1 1.163 R2C4A.F1 to R3C4B.C0 mem_data_1
CTOF_DEL --- 0.495 R3C4B.C0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.702 R4C4A.F1 to R4C4A.B0 F_7
CTOF_DEL --- 0.495 R4C4A.B0 to R4C4A.F0 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 1 0.000 R4C4A.F0 to R4C4A.DI0 alu_impl_I/alu_impl/alu_hi/n1359 (to master_clk)
--------
16.035 (36.5% logic, 63.5% route), 10 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_20
ROUTE 67 1.525 R3C8B.Q1 to R2C9D.B0 pc_1
CTOF_DEL --- 0.495 R2C9D.B0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.495 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.656 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.495 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.324 R2C2A.F1 to R2C2B.D1 n9
CTOF_DEL --- 0.495 R2C2B.D1 to R2C2B.F1 SLICE_24
ROUTE 4 0.636 R2C2B.F1 to R2C4A.WCK WE_mem
--------
16.744 (29.7% logic, 70.3% route), 8 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_hi/SLICE_14:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C4A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 99.794ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i7 (to master_clk +)
Delay: 15.716ns (40.4% logic, 59.6% route), 11 logic levels.
Constraint Details:
15.716ns physical path delay sram_impl/mem1/SLICE_8 to alu_impl_I/alu_impl/alu_hi/SLICE_14 meets
124.998ns delay constraint less
9.322ns skew and
0.166ns DIN_SET requirement (totaling 115.510ns) by 99.794ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to alu_impl_I/alu_impl/alu_hi/SLICE_14:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R2C4A.WCK to R2C4A.F0 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 1 1.355 R2C4A.F0 to R3C5C.D0 mem_data_0
CTOF_DEL --- 0.495 R3C5C.D0 to R3C5C.F0 alu_impl/SLICE_95
ROUTE 2 0.756 R3C5C.F0 to R3C5D.C0 alu_impl/I_DATA_0
CTOF_DEL --- 0.495 R3C5D.C0 to R3C5D.F0 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 3 0.445 R3C5D.F0 to R3C5D.C1 n52_adj_25
CTOF_DEL --- 0.495 R3C5D.C1 to R3C5D.F1 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 1 1.004 R3C5D.F1 to R3C5B.B1 alu_impl/alu_impl/alu_lo/n2077
CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.702 R4C4A.F1 to R4C4A.B0 F_7
CTOF_DEL --- 0.495 R4C4A.B0 to R4C4A.F0 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 1 0.000 R4C4A.F0 to R4C4A.DI0 alu_impl_I/alu_impl/alu_hi/n1359 (to master_clk)
--------
15.716 (40.4% logic, 59.6% route), 11 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_20
ROUTE 67 1.525 R3C8B.Q1 to R2C9D.B0 pc_1
CTOF_DEL --- 0.495 R2C9D.B0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.495 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.656 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.495 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.324 R2C2A.F1 to R2C2B.D1 n9
CTOF_DEL --- 0.495 R2C2B.D1 to R2C2B.F1 SLICE_24
ROUTE 4 0.636 R2C2B.F1 to R2C4A.WCK WE_mem
--------
16.744 (29.7% logic, 70.3% route), 8 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_hi/SLICE_14:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C4A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 99.834ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 15.676ns (40.5% logic, 59.5% route), 11 logic levels.
Constraint Details:
15.676ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets
124.998ns delay constraint less
9.322ns skew and
0.166ns DIN_SET requirement (totaling 115.510ns) by 99.834ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R2C4A.WCK to R2C4A.F1 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 1 1.163 R2C4A.F1 to R3C4B.C0 mem_data_1
CTOF_DEL --- 0.495 R3C4B.C0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 0.445 R3C4B.F0 to R3C4B.C1 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C4B.C1 to R3C4B.F1 alu_impl/SLICE_96
ROUTE 2 0.978 R3C4B.F1 to R3C5B.A1 n1255
CTOF_DEL --- 0.495 R3C5B.A1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.010 R4C3A.F0 to R4C4A.B1 n2175
CTOF_DEL --- 0.495 R4C4A.B1 to R4C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.635 R4C4A.F1 to R4C4D.D0 F_7
CTOF_DEL --- 0.495 R4C4D.D0 to R4C4D.F0 alu_impl/SLICE_110
ROUTE 1 1.001 R4C4D.F0 to R4C5A.B0 alu_impl/n3465
CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
15.676 (40.5% logic, 59.5% route), 11 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_20
ROUTE 67 1.525 R3C8B.Q1 to R2C9D.B0 pc_1
CTOF_DEL --- 0.495 R2C9D.B0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.495 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.656 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.495 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.324 R2C2A.F1 to R2C2B.D1 n9
CTOF_DEL --- 0.495 R2C2B.D1 to R2C2B.F1 SLICE_24
ROUTE 4 0.636 R2C2B.F1 to R2C4A.WCK WE_mem
--------
16.744 (29.7% logic, 70.3% route), 8 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C5A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 100.064ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 15.446ns (36.2% logic, 63.8% route), 9 logic levels.
Constraint Details:
15.446ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_15 meets
124.998ns delay constraint less
9.322ns skew and
0.166ns DIN_SET requirement (totaling 115.510ns) by 100.064ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to SLICE_15:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R2C4A.WCK to R2C4A.F1 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 1 1.163 R2C4A.F1 to R3C4B.C0 mem_data_1
CTOF_DEL --- 0.495 R3C4B.C0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 2.766 R3C4B.F0 to R3C5B.C0 alu_impl/I_DATA_1
CTOF_DEL --- 0.495 R3C5B.C0 to R3C5B.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 0.445 R3C5B.F0 to R3C5B.C1 n62_adj_26
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.308 R3C5B.F1 to R4C6A.A0 n2147
CTOF_DEL --- 0.495 R4C6A.A0 to R4C6A.F0 alu_impl/alu_impl/SLICE_101
ROUTE 3 0.673 R4C6A.F0 to R4C6A.A1 n2083
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 alu_impl/alu_impl/SLICE_101
ROUTE 1 1.413 R4C6A.F1 to R4C3A.A1 alu_impl/alu_impl/alu_hi/n2169
CTOF_DEL --- 0.495 R4C3A.A1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.702 R4C3A.F1 to R4C3A.B0 n2187
CTOF_DEL --- 0.495 R4C3A.B0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 1.392 R4C3A.F0 to R4C4C.A0 n2175
CTOOFX_DEL --- 0.721 R4C4C.A0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
15.446 (36.2% logic, 63.8% route), 9 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R3C8B.CLK master_clk
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_20
ROUTE 67 1.525 R3C8B.Q1 to R2C9D.B0 pc_1
CTOF_DEL --- 0.495 R2C9D.B0 to R2C9D.F0 SLICE_103
ROUTE 1 1.450 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.721 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 1.578 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.495 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.656 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.495 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.324 R2C2A.F1 to R2C2B.D1 n9
CTOF_DEL --- 0.495 R2C2B.D1 to R2C2B.F1 SLICE_24
ROUTE 4 0.636 R2C2B.F1 to R2C4A.WCK WE_mem
--------
16.744 (29.7% logic, 70.3% route), 8 logic levels.
Destination Clock Path CLK_2X to SLICE_15:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_2X
ROUTE 8 2.762 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.452 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 2.836 R2C5A.Q0 to R4C4C.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "CLK_2X" 48.000000 MHz ; | 48.000 MHz| 58.245 MHz| 5
| | |
MULTICYCLE FROM GROUP "code" TO GROUP | | |
"akku" 4.000000 X ; | 83.332 ns| 23.302 ns| 14
| | |
MULTICYCLE FROM GROUP "efb" TO GROUP | | |
"akku" 2.000000 X ; | 41.666 ns| 13.200 ns| 11
| | |
MULTICYCLE FROM CLKNET "WE_mem" | | |
6.000000 X ; | 124.998 ns| 26.952 ns| 11
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 6 clocks:
Clock Domain: CLK_2X_c Source: CLK_2X.PAD Loads: 8
Covered under: FREQUENCY PORT "CLK_2X" 48.000000 MHz ;
Data transfers from:
Clock Domain: master_clk Source: SLICE_19.Q0
Covered under: FREQUENCY PORT "CLK_2X" 48.000000 MHz ; Transfers: 14
Clock Domain: i2c1_sclo Source: efb_impl/EFBInst_0.I2C1SCLO Loads: 1
No transfer within this clock domain is found
Clock Domain: i2c1_scli Source: SCL.PAD Loads: 1
No transfer within this clock domain is found
Clock Domain: master_clk Source: SLICE_19.Q0 Loads: 14
Covered under: FREQUENCY PORT "CLK_2X" 48.000000 MHz ;
Covered under: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 4.000000 X ;
Data transfers from:
Clock Domain: CLK_2X_c Source: CLK_2X.PAD
Covered under: MULTICYCLE FROM GROUP "efb" TO GROUP "akku" 2.000000 X ; Transfers: 8
Clock Domain: WE_mem Source: SLICE_24.F1
Covered under: MULTICYCLE FROM CLKNET "WE_mem" 6.000000 X ; Transfers: 8
Clock Domain: O_STB_c Source: SLICE_88.F0 Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: master_clk Source: SLICE_19.Q0
Covered under: FREQUENCY PORT "CLK_2X" 48.000000 MHz ; Transfers: 8
Clock Domain: WE_mem Source: SLICE_24.F1 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: master_clk Source: SLICE_19.Q0
Covered under: FREQUENCY PORT "CLK_2X" 48.000000 MHz ; Transfers: 14
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 41516 paths, 9 nets, and 965 connections (96.9% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond_1.4_Production (87)
Tue Jun 26 16:40:01 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_mcpu3_efb.twr qfn32samples_mcpu3_efb.ncd qfn32samples_mcpu3_efb.prf
Design file: qfn32samples_mcpu3_efb.ncd
Preference file: qfn32samples_mcpu3_efb.prf
Device,speed: LCMXO2-256HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY PORT "CLK_2X" 48.000000 MHz (320 errors)
1733 items scored, 320 timing errors detected.
MULTICYCLE FROM GROUP "code" TO GROUP "akku" 4.000000 X (0 errors) 4096 items scored, 0 timing errors detected.
MULTICYCLE FROM GROUP "efb" TO GROUP "akku" 2.000000 X (1 errors)
160 items scored, 1 timing error detected.
MULTICYCLE FROM CLKNET "WE_mem" 6.000000 X (0 errors) 160 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "CLK_2X" 48.000000 MHz ;
1733 items scored, 320 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 3.719ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i4 (from master_clk +)
Destination: FF Data in r_oport_i4 (to O_STB_c +)
Delay: 0.383ns (34.2% logic, 65.8% route), 1 logic levels.
Constraint Details:
0.383ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_12 to O_PORT_4_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.138ns skew requirement (totaling 4.102ns) by 3.719ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_hi/SLICE_12 to O_PORT_4_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R5C3A.CLK to R5C3A.Q0 alu_impl_I/alu_impl/alu_hi/SLICE_12 (from master_clk)
ROUTE 9 0.252 R5C3A.Q0 to IOL_B2D.OPOS akku_4 (to O_STB_c)
--------
0.383 (34.2% logic, 65.8% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to alu_impl_I/alu_impl/alu_hi/SLICE_12:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R5C3A.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_2X to O_PORT_4_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C8C.CLK master_clk
REG_DEL --- 0.151 R3C8C.CLK to R3C8C.Q0 SLICE_21
ROUTE 68 0.576 R3C8C.Q0 to R2C9D.A0 pc_2
CTOF_DEL --- 0.174 R2C9D.A0 to R2C9D.F0 SLICE_103
ROUTE 1 0.468 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.267 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 0.501 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.174 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.216 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.174 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.355 R2C2A.F1 to R5C2D.D0 n9
CTOF_DEL --- 0.174 R5C2D.D0 to R5C2D.F0 SLICE_88
ROUTE 9 0.908 R5C2D.F0 to IOL_B2D.CLK O_STB_c
--------
6.604 (25.8% logic, 74.2% route), 8 logic levels.
Error: The following path exceeds requirements by 3.664ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i3 (from master_clk +)
Destination: FF Data in r_oport_i3 (to O_STB_c +)
Delay: 0.438ns (29.9% logic, 70.1% route), 1 logic levels.
Constraint Details:
0.438ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_11 to O_PORT_3_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.138ns skew requirement (totaling 4.102ns) by 3.664ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_lo/SLICE_11 to O_PORT_3_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C5D.CLK to R4C5D.Q1 alu_impl_I/alu_impl/alu_lo/SLICE_11 (from master_clk)
ROUTE 9 0.307 R4C5D.Q1 to IOL_R5B.OPOS akku_3 (to O_STB_c)
--------
0.438 (29.9% logic, 70.1% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to alu_impl_I/alu_impl/alu_lo/SLICE_11:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C5D.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_2X to O_PORT_3_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C8C.CLK master_clk
REG_DEL --- 0.151 R3C8C.CLK to R3C8C.Q0 SLICE_21
ROUTE 68 0.576 R3C8C.Q0 to R2C9D.A0 pc_2
CTOF_DEL --- 0.174 R2C9D.A0 to R2C9D.F0 SLICE_103
ROUTE 1 0.468 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.267 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 0.501 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.174 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.216 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.174 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.355 R2C2A.F1 to R5C2D.D0 n9
CTOF_DEL --- 0.174 R5C2D.D0 to R5C2D.F0 SLICE_88
ROUTE 9 0.908 R5C2D.F0 to IOL_R5B.CLK O_STB_c
--------
6.604 (25.8% logic, 74.2% route), 8 logic levels.
Error: The following path exceeds requirements by 3.609ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i5 (from master_clk +)
Destination: FF Data in r_oport_i5 (to O_STB_c +)
Delay: 0.493ns (26.6% logic, 73.4% route), 1 logic levels.
Constraint Details:
0.493ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_12 to O_PORT_5_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.138ns skew requirement (totaling 4.102ns) by 3.609ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_hi/SLICE_12 to O_PORT_5_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R5C3A.CLK to R5C3A.Q1 alu_impl_I/alu_impl/alu_hi/SLICE_12 (from master_clk)
ROUTE 9 0.362 R5C3A.Q1 to IOL_B2C.OPOS akku_5 (to O_STB_c)
--------
0.493 (26.6% logic, 73.4% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to alu_impl_I/alu_impl/alu_hi/SLICE_12:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R5C3A.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_2X to O_PORT_5_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C8C.CLK master_clk
REG_DEL --- 0.151 R3C8C.CLK to R3C8C.Q0 SLICE_21
ROUTE 68 0.576 R3C8C.Q0 to R2C9D.A0 pc_2
CTOF_DEL --- 0.174 R2C9D.A0 to R2C9D.F0 SLICE_103
ROUTE 1 0.468 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.267 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 0.501 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.174 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.216 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.174 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.355 R2C2A.F1 to R5C2D.D0 n9
CTOF_DEL --- 0.174 R5C2D.D0 to R5C2D.F0 SLICE_88
ROUTE 9 0.908 R5C2D.F0 to IOL_B2C.CLK O_STB_c
--------
6.604 (25.8% logic, 74.2% route), 8 logic levels.
Error: The following path exceeds requirements by 3.503ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i7 (from master_clk +)
Destination: FF Data in r_oport_i7 (to O_STB_c +)
Delay: 0.599ns (21.9% logic, 78.1% route), 1 logic levels.
Constraint Details:
0.599ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_14 to O_PORT_7_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.138ns skew requirement (totaling 4.102ns) by 3.503ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_hi/SLICE_14 to O_PORT_7_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C4A.CLK to R4C4A.Q0 alu_impl_I/alu_impl/alu_hi/SLICE_14 (from master_clk)
ROUTE 9 0.468 R4C4A.Q0 to IOL_L5D.OPOS akku_7 (to O_STB_c)
--------
0.599 (21.9% logic, 78.1% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to alu_impl_I/alu_impl/alu_hi/SLICE_14:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C4A.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_2X to O_PORT_7_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C8C.CLK master_clk
REG_DEL --- 0.151 R3C8C.CLK to R3C8C.Q0 SLICE_21
ROUTE 68 0.576 R3C8C.Q0 to R2C9D.A0 pc_2
CTOF_DEL --- 0.174 R2C9D.A0 to R2C9D.F0 SLICE_103
ROUTE 1 0.468 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.267 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 0.501 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.174 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.216 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.174 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.355 R2C2A.F1 to R5C2D.D0 n9
CTOF_DEL --- 0.174 R5C2D.D0 to R5C2D.F0 SLICE_88
ROUTE 9 0.908 R5C2D.F0 to IOL_L5D.CLK O_STB_c
--------
6.604 (25.8% logic, 74.2% route), 8 logic levels.
Error: The following path exceeds requirements by 3.376ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i2 (from master_clk +)
Destination: FF Data in r_oport_i2 (to O_STB_c +)
Delay: 0.726ns (18.0% logic, 82.0% route), 1 logic levels.
Constraint Details:
0.726ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_11 to O_PORT_2_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.138ns skew requirement (totaling 4.102ns) by 3.376ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_lo/SLICE_11 to O_PORT_2_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C5D.CLK to R4C5D.Q0 alu_impl_I/alu_impl/alu_lo/SLICE_11 (from master_clk)
ROUTE 9 0.595 R4C5D.Q0 to IOL_R5A.OPOS akku_2 (to O_STB_c)
--------
0.726 (18.0% logic, 82.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to alu_impl_I/alu_impl/alu_lo/SLICE_11:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C5D.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_2X to O_PORT_2_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C8C.CLK master_clk
REG_DEL --- 0.151 R3C8C.CLK to R3C8C.Q0 SLICE_21
ROUTE 68 0.576 R3C8C.Q0 to R2C9D.A0 pc_2
CTOF_DEL --- 0.174 R2C9D.A0 to R2C9D.F0 SLICE_103
ROUTE 1 0.468 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.267 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 0.501 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.174 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.216 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.174 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.355 R2C2A.F1 to R5C2D.D0 n9
CTOF_DEL --- 0.174 R5C2D.D0 to R5C2D.F0 SLICE_88
ROUTE 9 0.908 R5C2D.F0 to IOL_R5A.CLK O_STB_c
--------
6.604 (25.8% logic, 74.2% route), 8 logic levels.
Error: The following path exceeds requirements by 3.338ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i6 (from master_clk +)
Destination: FF Data in r_oport_i6 (to O_STB_c +)
Delay: 0.764ns (17.1% logic, 82.9% route), 1 logic levels.
Constraint Details:
0.764ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_13 to O_PORT_6_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.138ns skew requirement (totaling 4.102ns) by 3.338ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_hi/SLICE_13 to O_PORT_6_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C3B.CLK to R4C3B.Q0 alu_impl_I/alu_impl/alu_hi/SLICE_13 (from master_clk)
ROUTE 9 0.633 R4C3B.Q0 to IOL_B2A.OPOS akku_6 (to O_STB_c)
--------
0.764 (17.1% logic, 82.9% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to alu_impl_I/alu_impl/alu_hi/SLICE_13:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C3B.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_2X to O_PORT_6_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C8C.CLK master_clk
REG_DEL --- 0.151 R3C8C.CLK to R3C8C.Q0 SLICE_21
ROUTE 68 0.576 R3C8C.Q0 to R2C9D.A0 pc_2
CTOF_DEL --- 0.174 R2C9D.A0 to R2C9D.F0 SLICE_103
ROUTE 1 0.468 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.267 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 0.501 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.174 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.216 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.174 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.355 R2C2A.F1 to R5C2D.D0 n9
CTOF_DEL --- 0.174 R5C2D.D0 to R5C2D.F0 SLICE_88
ROUTE 9 0.908 R5C2D.F0 to IOL_B2A.CLK O_STB_c
--------
6.604 (25.8% logic, 74.2% route), 8 logic levels.
Error: The following path exceeds requirements by 3.292ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i0 (from master_clk +)
Destination: FF Data in r_oport_i0 (to O_STB_c +)
Delay: 0.810ns (16.2% logic, 83.8% route), 1 logic levels.
Constraint Details:
0.810ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_10 to O_PORT_0_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.138ns skew requirement (totaling 4.102ns) by 3.292ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_lo/SLICE_10 to O_PORT_0_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R5C5C.CLK to R5C5C.Q0 alu_impl_I/alu_impl/alu_lo/SLICE_10 (from master_clk)
ROUTE 8 0.679 R5C5C.Q0 to IOL_T9B.OPOS akku_0 (to O_STB_c)
--------
0.810 (16.2% logic, 83.8% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R5C5C.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_2X to O_PORT_0_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C8C.CLK master_clk
REG_DEL --- 0.151 R3C8C.CLK to R3C8C.Q0 SLICE_21
ROUTE 68 0.576 R3C8C.Q0 to R2C9D.A0 pc_2
CTOF_DEL --- 0.174 R2C9D.A0 to R2C9D.F0 SLICE_103
ROUTE 1 0.468 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.267 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 0.501 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.174 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.216 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.174 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.355 R2C2A.F1 to R5C2D.D0 n9
CTOF_DEL --- 0.174 R5C2D.D0 to R5C2D.F0 SLICE_88
ROUTE 9 0.908 R5C2D.F0 to IOL_T9B.CLK O_STB_c
--------
6.604 (25.8% logic, 74.2% route), 8 logic levels.
Error: The following path exceeds requirements by 3.268ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i1 (from master_clk +)
Destination: FF Data in r_oport_i1 (to O_STB_c +)
Delay: 0.834ns (15.7% logic, 84.3% route), 1 logic levels.
Constraint Details:
0.834ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_10 to O_PORT_1_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.138ns skew requirement (totaling 4.102ns) by 3.268ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_lo/SLICE_10 to O_PORT_1_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R5C5C.CLK to R5C5C.Q1 alu_impl_I/alu_impl/alu_lo/SLICE_10 (from master_clk)
ROUTE 9 0.703 R5C5C.Q1 to IOL_T9D.OPOS akku_1 (to O_STB_c)
--------
0.834 (15.7% logic, 84.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R5C5C.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_2X to O_PORT_1_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C8C.CLK master_clk
REG_DEL --- 0.151 R3C8C.CLK to R3C8C.Q0 SLICE_21
ROUTE 68 0.576 R3C8C.Q0 to R2C9D.A0 pc_2
CTOF_DEL --- 0.174 R2C9D.A0 to R2C9D.F0 SLICE_103
ROUTE 1 0.468 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.267 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 0.501 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.174 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.216 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.174 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.355 R2C2A.F1 to R5C2D.D0 n9
CTOF_DEL --- 0.174 R5C2D.D0 to R5C2D.F0 SLICE_88
ROUTE 9 0.908 R5C2D.F0 to IOL_T9D.CLK O_STB_c
--------
6.604 (25.8% logic, 74.2% route), 8 logic levels.
Error: The following path exceeds requirements by 2.954ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i6 (from master_clk +)
Destination: FF Data in sram_impl/mem0/RAM1 (to WE_mem +)
FF sram_impl/mem0/RAM1
Delay: 0.354ns (37.0% logic, 63.0% route), 2 logic levels.
Constraint Details:
0.354ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_13 to sram_impl/mem0/SLICE_6 exceeds
0.129ns WD_HLD and
0.000ns delay constraint less
-3.179ns skew requirement (totaling 3.308ns) by 2.954ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_hi/SLICE_13 to sram_impl/mem0/SLICE_6:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C3B.CLK to R4C3B.Q0 alu_impl_I/alu_impl/alu_hi/SLICE_13 (from master_clk)
ROUTE 9 0.223 R4C3B.Q0 to R2C3C.C1 akku_6
ZERO_DEL --- 0.000 R2C3C.C1 to R2C3C.WDO2 sram_impl/mem0/SLICE_4
ROUTE 1 0.000 R2C3C.WDO2 to R2C3B.WD0 sram_impl/mem0/WD2_INT (to WE_mem)
--------
0.354 (37.0% logic, 63.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to alu_impl_I/alu_impl/alu_hi/SLICE_13:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C3B.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_2X to sram_impl/mem0/SLICE_6:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C8C.CLK master_clk
REG_DEL --- 0.151 R3C8C.CLK to R3C8C.Q0 SLICE_21
ROUTE 68 0.576 R3C8C.Q0 to R2C9D.A0 pc_2
CTOF_DEL --- 0.174 R2C9D.A0 to R2C9D.F0 SLICE_103
ROUTE 1 0.468 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.267 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 0.501 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.174 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.216 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.174 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.108 R2C2A.F1 to R2C2B.D1 n9
CTOF_DEL --- 0.174 R2C2B.D1 to R2C2B.F1 SLICE_24
ROUTE 4 0.196 R2C2B.F1 to R2C3B.WCK WE_mem
--------
5.645 (30.2% logic, 69.8% route), 8 logic levels.
Error: The following path exceeds requirements by 2.932ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i3 (from master_clk +)
Destination: FF Data in sram_impl/mem1/RAM1 (to WE_mem +)
FF sram_impl/mem1/RAM1
Delay: 0.376ns (34.8% logic, 65.2% route), 2 logic levels.
Constraint Details:
0.376ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_11 to sram_impl/mem1/SLICE_9 exceeds
0.129ns WD_HLD and
0.000ns delay constraint less
-3.179ns skew requirement (totaling 3.308ns) by 2.932ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_lo/SLICE_11 to sram_impl/mem1/SLICE_9:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C5D.CLK to R4C5D.Q1 alu_impl_I/alu_impl/alu_lo/SLICE_11 (from master_clk)
ROUTE 9 0.245 R4C5D.Q1 to R2C4C.D1 akku_3
ZERO_DEL --- 0.000 R2C4C.D1 to R2C4C.WDO3 sram_impl/mem1/SLICE_7
ROUTE 1 0.000 R2C4C.WDO3 to R2C4B.WD1 sram_impl/mem1/WD3_INT (to WE_mem)
--------
0.376 (34.8% logic, 65.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to alu_impl_I/alu_impl/alu_lo/SLICE_11:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C5D.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_2X to sram_impl/mem1/SLICE_9:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C8C.CLK master_clk
REG_DEL --- 0.151 R3C8C.CLK to R3C8C.Q0 SLICE_21
ROUTE 68 0.576 R3C8C.Q0 to R2C9D.A0 pc_2
CTOF_DEL --- 0.174 R2C9D.A0 to R2C9D.F0 SLICE_103
ROUTE 1 0.468 R2C9D.F0 to R2C9B.B0 n3653
CTOOFX_DEL --- 0.267 R2C9B.B0 to R2C9B.OFX0 mux_123_Mux_6_i63/SLICE_44
ROUTE 4 0.501 R2C9B.OFX0 to R2C2A.B0 code_data_6
CTOF_DEL --- 0.174 R2C2A.B0 to R2C2A.F0 SLICE_89
ROUTE 1 0.216 R2C2A.F0 to R2C2A.A1 n6
CTOF_DEL --- 0.174 R2C2A.A1 to R2C2A.F1 SLICE_89
ROUTE 2 0.108 R2C2A.F1 to R2C2B.D1 n9
CTOF_DEL --- 0.174 R2C2B.D1 to R2C2B.F1 SLICE_24
ROUTE 4 0.196 R2C2B.F1 to R2C4B.WCK WE_mem
--------
5.645 (30.2% logic, 69.8% route), 8 logic levels.
================================================================================
Preference: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 4.000000 X ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.156ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 1.143ns (33.0% logic, 67.0% route), 3 logic levels.
Constraint Details:
1.143ns physical path delay SLICE_20 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.156ns
Physical Path Details:
Data path SLICE_20 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8B.CLK to R3C8B.Q0 SLICE_20 (from master_clk)
ROUTE 29 0.378 R3C8B.Q0 to R4C7C.M1 pc_0
MTOOFX_DEL --- 0.093 R4C7C.M1 to R4C7C.OFX1 rom_impl/SLICE_58
ROUTE 19 0.388 R4C7C.OFX1 to R4C4C.D0 int_c_adj_24
CTOOFX_DEL --- 0.153 R4C4C.D0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
1.143 (33.0% logic, 67.0% route), 3 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R3C8B.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R4C4C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.156ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from master_clk +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 1.143ns (44.1% logic, 55.9% route), 4 logic levels.
Constraint Details:
1.143ns physical path delay SLICE_21 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.156ns
Physical Path Details:
Data path SLICE_21 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8C.CLK to R3C8C.Q1 SLICE_21 (from master_clk)
ROUTE 68 0.251 R3C8C.Q1 to R4C7C.D1 pc_3
CTOOFX_DEL --- 0.153 R4C7C.D1 to R4C7C.OFX0 rom_impl/SLICE_58
ROUTE 1 0.000 R4C7C.OFX0 to R4C7C.FXB rom_impl/mux_126_Mux_9_1_f5b
FXTOOFX_DE --- 0.067 R4C7C.FXB to R4C7C.OFX1 rom_impl/SLICE_58
ROUTE 19 0.388 R4C7C.OFX1 to R4C4C.D0 int_c_adj_24
CTOOFX_DEL --- 0.153 R4C4C.D0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
1.143 (44.1% logic, 55.9% route), 4 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R3C8C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R4C4C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.156ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from master_clk +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 1.143ns (44.1% logic, 55.9% route), 4 logic levels.
Constraint Details:
1.143ns physical path delay SLICE_21 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.156ns
Physical Path Details:
Data path SLICE_21 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8C.CLK to R3C8C.Q1 SLICE_21 (from master_clk)
ROUTE 68 0.251 R3C8C.Q1 to R4C7C.D0 pc_3
CTOOFX_DEL --- 0.153 R4C7C.D0 to R4C7C.OFX0 rom_impl/SLICE_58
ROUTE 1 0.000 R4C7C.OFX0 to R4C7C.FXB rom_impl/mux_126_Mux_9_1_f5b
FXTOOFX_DE --- 0.067 R4C7C.FXB to R4C7C.OFX1 rom_impl/SLICE_58
ROUTE 19 0.388 R4C7C.OFX1 to R4C4C.D0 int_c_adj_24
CTOOFX_DEL --- 0.153 R4C4C.D0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
1.143 (44.1% logic, 55.9% route), 4 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R3C8C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R4C4C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.159ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from master_clk +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 1.146ns (44.0% logic, 56.0% route), 4 logic levels.
Constraint Details:
1.146ns physical path delay SLICE_21 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.159ns
Physical Path Details:
Data path SLICE_21 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8C.CLK to R3C8C.Q1 SLICE_21 (from master_clk)
ROUTE 68 0.254 R3C8C.Q1 to R4C7D.C1 pc_3
CTOOFX_DEL --- 0.153 R4C7D.C1 to R4C7D.OFX0 rom_impl/SLICE_57
ROUTE 1 0.000 R4C7D.OFX0 to R4C7C.FXA rom_impl/mux_126_Mux_9_0_f5a
FXTOOFX_DE --- 0.067 R4C7C.FXA to R4C7C.OFX1 rom_impl/SLICE_58
ROUTE 19 0.388 R4C7C.OFX1 to R4C4C.D0 int_c_adj_24
CTOOFX_DEL --- 0.153 R4C4C.D0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
1.146 (44.0% logic, 56.0% route), 4 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R3C8C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R4C4C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.159ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from master_clk +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 1.146ns (44.0% logic, 56.0% route), 4 logic levels.
Constraint Details:
1.146ns physical path delay SLICE_21 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.159ns
Physical Path Details:
Data path SLICE_21 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8C.CLK to R3C8C.Q1 SLICE_21 (from master_clk)
ROUTE 68 0.254 R3C8C.Q1 to R4C7D.C0 pc_3
CTOOFX_DEL --- 0.153 R4C7D.C0 to R4C7D.OFX0 rom_impl/SLICE_57
ROUTE 1 0.000 R4C7D.OFX0 to R4C7C.FXA rom_impl/mux_126_Mux_9_0_f5a
FXTOOFX_DE --- 0.067 R4C7C.FXA to R4C7C.OFX1 rom_impl/SLICE_58
ROUTE 19 0.388 R4C7C.OFX1 to R4C4C.D0 int_c_adj_24
CTOOFX_DEL --- 0.153 R4C4C.D0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
1.146 (44.0% logic, 56.0% route), 4 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R3C8C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R4C4C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.164ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i4 (from master_clk +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 1.151ns (43.8% logic, 56.2% route), 4 logic levels.
Constraint Details:
1.151ns physical path delay SLICE_22 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.164ns
Physical Path Details:
Data path SLICE_22 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8A.CLK to R3C8A.Q0 SLICE_22 (from master_clk)
ROUTE 61 0.259 R3C8A.Q0 to R4C7D.D1 pc_4
CTOOFX_DEL --- 0.153 R4C7D.D1 to R4C7D.OFX0 rom_impl/SLICE_57
ROUTE 1 0.000 R4C7D.OFX0 to R4C7C.FXA rom_impl/mux_126_Mux_9_0_f5a
FXTOOFX_DE --- 0.067 R4C7C.FXA to R4C7C.OFX1 rom_impl/SLICE_58
ROUTE 19 0.388 R4C7C.OFX1 to R4C4C.D0 int_c_adj_24
CTOOFX_DEL --- 0.153 R4C4C.D0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
1.151 (43.8% logic, 56.2% route), 4 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R3C8A.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R4C4C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.164ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i4 (from master_clk +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 1.151ns (43.8% logic, 56.2% route), 4 logic levels.
Constraint Details:
1.151ns physical path delay SLICE_22 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.164ns
Physical Path Details:
Data path SLICE_22 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8A.CLK to R3C8A.Q0 SLICE_22 (from master_clk)
ROUTE 61 0.259 R3C8A.Q0 to R4C7D.D0 pc_4
CTOOFX_DEL --- 0.153 R4C7D.D0 to R4C7D.OFX0 rom_impl/SLICE_57
ROUTE 1 0.000 R4C7D.OFX0 to R4C7C.FXA rom_impl/mux_126_Mux_9_0_f5a
FXTOOFX_DE --- 0.067 R4C7C.FXA to R4C7C.OFX1 rom_impl/SLICE_58
ROUTE 19 0.388 R4C7C.OFX1 to R4C4C.D0 int_c_adj_24
CTOOFX_DEL --- 0.153 R4C4C.D0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
1.151 (43.8% logic, 56.2% route), 4 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R3C8A.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R4C4C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.229ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i5 (from master_clk +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 1.216ns (36.5% logic, 63.5% route), 4 logic levels.
Constraint Details:
1.216ns physical path delay SLICE_22 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.229ns
Physical Path Details:
Data path SLICE_22 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8A.CLK to R3C8A.Q1 SLICE_22 (from master_clk)
ROUTE 31 0.384 R3C8A.Q1 to R4C7D.M0 pc_5
MTOOFX_DEL --- 0.093 R4C7D.M0 to R4C7D.OFX0 rom_impl/SLICE_57
ROUTE 1 0.000 R4C7D.OFX0 to R4C7C.FXA rom_impl/mux_126_Mux_9_0_f5a
FXTOOFX_DE --- 0.067 R4C7C.FXA to R4C7C.OFX1 rom_impl/SLICE_58
ROUTE 19 0.388 R4C7C.OFX1 to R4C4C.D0 int_c_adj_24
CTOOFX_DEL --- 0.153 R4C4C.D0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
1.216 (36.5% logic, 63.5% route), 4 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R3C8A.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R4C4C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.229ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i5 (from master_clk +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 1.216ns (36.5% logic, 63.5% route), 4 logic levels.
Constraint Details:
1.216ns physical path delay SLICE_22 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.229ns
Physical Path Details:
Data path SLICE_22 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8A.CLK to R3C8A.Q1 SLICE_22 (from master_clk)
ROUTE 31 0.384 R3C8A.Q1 to R4C7C.M0 pc_5
MTOOFX_DEL --- 0.093 R4C7C.M0 to R4C7C.OFX0 rom_impl/SLICE_58
ROUTE 1 0.000 R4C7C.OFX0 to R4C7C.FXB rom_impl/mux_126_Mux_9_1_f5b
FXTOOFX_DE --- 0.067 R4C7C.FXB to R4C7C.OFX1 rom_impl/SLICE_58
ROUTE 19 0.388 R4C7C.OFX1 to R4C4C.D0 int_c_adj_24
CTOOFX_DEL --- 0.153 R4C4C.D0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
1.216 (36.5% logic, 63.5% route), 4 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R3C8A.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R4C4C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.231ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i2 (from master_clk +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 1.218ns (41.4% logic, 58.6% route), 4 logic levels.
Constraint Details:
1.218ns physical path delay SLICE_21 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.231ns
Physical Path Details:
Data path SLICE_21 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8C.CLK to R3C8C.Q0 SLICE_21 (from master_clk)
ROUTE 68 0.326 R3C8C.Q0 to R4C7D.A1 pc_2
CTOOFX_DEL --- 0.153 R4C7D.A1 to R4C7D.OFX0 rom_impl/SLICE_57
ROUTE 1 0.000 R4C7D.OFX0 to R4C7C.FXA rom_impl/mux_126_Mux_9_0_f5a
FXTOOFX_DE --- 0.067 R4C7C.FXA to R4C7C.OFX1 rom_impl/SLICE_58
ROUTE 19 0.388 R4C7C.OFX1 to R4C4C.D0 int_c_adj_24
CTOOFX_DEL --- 0.153 R4C4C.D0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
1.218 (41.4% logic, 58.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path SLICE_19 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R3C8C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_19 to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 14 0.993 R2C5A.Q0 to R4C4C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: MULTICYCLE FROM GROUP "efb" TO GROUP "akku" 2.000000 X ;
160 items scored, 1 timing error detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 0.023ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i6 (from CLK_2X_c +)
Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i6 (to master_clk +)
Delay: 1.108ns (47.6% logic, 52.4% route), 5 logic levels.
Constraint Details:
1.108ns physical path delay SLICE_28 to alu_impl_I/alu_impl/alu_hi/SLICE_13 exceeds
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.144ns skew requirement (totaling 1.131ns) by 0.023ns
Physical Path Details:
Data path SLICE_28 to alu_impl_I/alu_impl/alu_hi/SLICE_13:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R2C3D.CLK to R2C3D.Q0 SLICE_28 (from CLK_2X_c)
ROUTE 1 0.134 R2C3D.Q0 to R3C3D.C0 wb_data_l_6
CTOF_DEL --- 0.099 R3C3D.C0 to R3C3D.F0 alu_impl/SLICE_93
ROUTE 2 0.057 R3C3D.F0 to R3C3D.C1 alu_impl/I_DATA_6
CTOF_DEL --- 0.099 R3C3D.C1 to R3C3D.F1 alu_impl/SLICE_93
ROUTE 2 0.333 R3C3D.F1 to R4C3B.B1 n6_adj_30
CTOF_DEL --- 0.099 R4C3B.B1 to R4C3B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_13
ROUTE 2 0.057 R4C3B.F1 to R4C3B.C0 F_6
CTOF_DEL --- 0.099 R4C3B.C0 to R4C3B.F0 alu_impl_I/alu_impl/alu_hi/SLICE_13
ROUTE 1 0.000 R4C3B.F0 to R4C3B.DI0 alu_impl_I/alu_impl/alu_hi/n3842 (to master_clk)
--------
1.108 (47.6% logic, 52.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_28:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C3D.CLK CLK_2X_c
--------
1.322 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_hi/SLICE_13:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C3B.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 0.040ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i2 (from CLK_2X_c +)
Destination: FF Data in alu_impl_I/alu_impl/alu_lo/akku_i2 (to master_clk +)
Delay: 1.171ns (45.0% logic, 55.0% route), 5 logic levels.
Constraint Details:
1.171ns physical path delay SLICE_1 to alu_impl_I/alu_impl/alu_lo/SLICE_11 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.144ns skew requirement (totaling 1.131ns) by 0.040ns
Physical Path Details:
Data path SLICE_1 to alu_impl_I/alu_impl/alu_lo/SLICE_11:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C7A.CLK to R3C7A.Q0 SLICE_1 (from CLK_2X_c)
ROUTE 1 0.241 R3C7A.Q0 to R3C6A.D0 wb_data_l_2
CTOF_DEL --- 0.099 R3C6A.D0 to R3C6A.F0 alu_impl/SLICE_94
ROUTE 2 0.135 R3C6A.F0 to R3C6A.C1 alu_impl/I_DATA_2
CTOF_DEL --- 0.099 R3C6A.C1 to R3C6A.F1 alu_impl/SLICE_94
ROUTE 2 0.135 R3C6A.F1 to R4C6D.D0 n72_adj_27
CTOF_DEL --- 0.099 R4C6D.D0 to R4C6D.F0 SLICE_76
ROUTE 2 0.133 R4C6D.F0 to R4C5D.D0 F_2
CTOF_DEL --- 0.099 R4C5D.D0 to R4C5D.F0 alu_impl_I/alu_impl/alu_lo/SLICE_11
ROUTE 1 0.000 R4C5D.F0 to R4C5D.DI0 alu_impl_I/alu_impl/alu_lo/n1384 (to master_clk)
--------
1.171 (45.0% logic, 55.0% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_1:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R3C7A.CLK CLK_2X_c
--------
1.322 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_lo/SLICE_11:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C5D.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 0.087ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i7 (from CLK_2X_c +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 1.218ns (39.6% logic, 60.4% route), 4 logic levels.
Constraint Details:
1.218ns physical path delay SLICE_28 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.144ns skew requirement (totaling 1.131ns) by 0.087ns
Physical Path Details:
Data path SLICE_28 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R2C3D.CLK to R2C3D.Q1 SLICE_28 (from CLK_2X_c)
ROUTE 1 0.391 R2C3D.Q1 to R3C4C.A0 wb_data_l_7
CTOF_DEL --- 0.099 R3C4C.A0 to R3C4C.F0 alu_impl/SLICE_92
ROUTE 2 0.207 R3C4C.F0 to R3C4C.A1 alu_impl/I_DATA_7
CTOF_DEL --- 0.099 R3C4C.A1 to R3C4C.F1 alu_impl/SLICE_92
ROUTE 2 0.138 R3C4C.F1 to R4C4C.C0 n1245
CTOOFX_DEL --- 0.153 R4C4C.C0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
1.218 (39.6% logic, 60.4% route), 4 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_28:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C3D.CLK CLK_2X_c
--------
1.322 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to SLICE_15:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C4C.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 0.122ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i0 (from CLK_2X_c +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 1.253ns (42.1% logic, 57.9% route), 5 logic levels.
Constraint Details:
1.253ns physical path delay SLICE_90 to SLICE_16 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.144ns skew requirement (totaling 1.131ns) by 0.122ns
Physical Path Details:
Data path SLICE_90 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C4A.CLK to R3C4A.Q0 SLICE_90 (from CLK_2X_c)
ROUTE 1 0.135 R3C4A.Q0 to R3C5C.C0 wb_data_l_0
CTOF_DEL --- 0.099 R3C5C.C0 to R3C5C.F0 alu_impl/SLICE_95
ROUTE 2 0.135 R3C5C.F0 to R3C5D.C0 alu_impl/I_DATA_0
CTOF_DEL --- 0.099 R3C5D.C0 to R3C5D.F0 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 3 0.249 R3C5D.F0 to R4C5A.C1 n52_adj_25
CTOF_DEL --- 0.099 R4C5A.C1 to R4C5A.F1 SLICE_16
ROUTE 2 0.207 R4C5A.F1 to R4C5A.A0 F_0
CTOF_DEL --- 0.099 R4C5A.A0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
1.253 (42.1% logic, 57.9% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_90:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R3C4A.CLK CLK_2X_c
--------
1.322 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C5A.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 0.124ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i0 (from CLK_2X_c +)
Destination: FF Data in alu_impl_I/alu_impl/alu_lo/akku_i0 (to master_clk +)
Delay: 1.255ns (42.0% logic, 58.0% route), 5 logic levels.
Constraint Details:
1.255ns physical path delay SLICE_90 to alu_impl_I/alu_impl/alu_lo/SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.144ns skew requirement (totaling 1.131ns) by 0.124ns
Physical Path Details:
Data path SLICE_90 to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C4A.CLK to R3C4A.Q0 SLICE_90 (from CLK_2X_c)
ROUTE 1 0.135 R3C4A.Q0 to R3C5C.C0 wb_data_l_0
CTOF_DEL --- 0.099 R3C5C.C0 to R3C5C.F0 alu_impl/SLICE_95
ROUTE 2 0.135 R3C5C.F0 to R3C5D.C0 alu_impl/I_DATA_0
CTOF_DEL --- 0.099 R3C5D.C0 to R3C5D.F0 alu_impl/alu_impl/alu_lo/SLICE_99
ROUTE 3 0.249 R3C5D.F0 to R4C5A.C1 n52_adj_25
CTOF_DEL --- 0.099 R4C5A.C1 to R4C5A.F1 SLICE_16
ROUTE 2 0.209 R4C5A.F1 to R5C5C.A0 F_0
CTOF_DEL --- 0.099 R5C5C.A0 to R5C5C.F0 alu_impl_I/alu_impl/alu_lo/SLICE_10
ROUTE 1 0.000 R5C5C.F0 to R5C5C.DI0 alu_impl_I/alu_impl/alu_lo/n1350 (to master_clk)
--------
1.255 (42.0% logic, 58.0% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_90:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R3C4A.CLK CLK_2X_c
--------
1.322 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R5C5C.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 0.166ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i6 (from CLK_2X_c +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 1.297ns (40.6% logic, 59.4% route), 5 logic levels.
Constraint Details:
1.297ns physical path delay SLICE_28 to SLICE_16 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.144ns skew requirement (totaling 1.131ns) by 0.166ns
Physical Path Details:
Data path SLICE_28 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R2C3D.CLK to R2C3D.Q0 SLICE_28 (from CLK_2X_c)
ROUTE 1 0.134 R2C3D.Q0 to R3C3D.C0 wb_data_l_6
CTOF_DEL --- 0.099 R3C3D.C0 to R3C3D.F0 alu_impl/SLICE_93
ROUTE 2 0.057 R3C3D.F0 to R3C3D.C1 alu_impl/I_DATA_6
CTOF_DEL --- 0.099 R3C3D.C1 to R3C3D.F1 alu_impl/SLICE_93
ROUTE 2 0.333 R3C3D.F1 to R4C3B.B1 n6_adj_30
CTOF_DEL --- 0.099 R4C3B.B1 to R4C3B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_13
ROUTE 2 0.246 R4C3B.F1 to R4C5A.C0 F_6
CTOF_DEL --- 0.099 R4C5A.C0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
1.297 (40.6% logic, 59.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_28:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C3D.CLK CLK_2X_c
--------
1.322 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C5A.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 0.181ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i1 (from CLK_2X_c +)
Destination: FF Data in alu_impl_I/alu_impl/alu_lo/akku_i1 (to master_clk +)
Delay: 1.312ns (40.2% logic, 59.8% route), 5 logic levels.
Constraint Details:
1.312ns physical path delay SLICE_90 to alu_impl_I/alu_impl/alu_lo/SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.144ns skew requirement (totaling 1.131ns) by 0.181ns
Physical Path Details:
Data path SLICE_90 to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C4A.CLK to R3C4A.Q1 SLICE_90 (from CLK_2X_c)
ROUTE 1 0.205 R3C4A.Q1 to R3C4B.A0 wb_data_l_1
CTOF_DEL --- 0.099 R3C4B.A0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 0.057 R3C4B.F0 to R3C4B.C1 alu_impl/I_DATA_1
CTOF_DEL --- 0.099 R3C4B.C1 to R3C4B.F1 alu_impl/SLICE_96
ROUTE 2 0.302 R3C4B.F1 to R4C5B.B0 n1255
CTOF_DEL --- 0.099 R4C5B.B0 to R4C5B.F0 SLICE_74
ROUTE 2 0.221 R4C5B.F0 to R5C5C.B1 F_1
CTOF_DEL --- 0.099 R5C5C.B1 to R5C5C.F1 alu_impl_I/alu_impl/alu_lo/SLICE_10
ROUTE 1 0.000 R5C5C.F1 to R5C5C.DI1 alu_impl_I/alu_impl/alu_lo/n1389 (to master_clk)
--------
1.312 (40.2% logic, 59.8% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_90:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R3C4A.CLK CLK_2X_c
--------
1.322 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R5C5C.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 0.203ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i0 (from CLK_2X_c +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 1.334ns (39.5% logic, 60.5% route), 5 logic levels.
Constraint Details:
1.334ns physical path delay SLICE_90 to SLICE_16 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.144ns skew requirement (totaling 1.131ns) by 0.203ns
Physical Path Details:
Data path SLICE_90 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C4A.CLK to R3C4A.Q0 SLICE_90 (from CLK_2X_c)
ROUTE 1 0.135 R3C4A.Q0 to R3C5C.C0 wb_data_l_0
CTOF_DEL --- 0.099 R3C5C.C0 to R3C5C.F0 alu_impl/SLICE_95
ROUTE 2 0.132 R3C5C.F0 to R3C5C.D1 alu_impl/I_DATA_0
CTOF_DEL --- 0.099 R3C5C.D1 to R3C5C.F1 alu_impl/SLICE_95
ROUTE 3 0.333 R3C5C.F1 to R4C5A.B1 n1254
CTOF_DEL --- 0.099 R4C5A.B1 to R4C5A.F1 SLICE_16
ROUTE 2 0.207 R4C5A.F1 to R4C5A.A0 F_0
CTOF_DEL --- 0.099 R4C5A.A0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
1.334 (39.5% logic, 60.5% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_90:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R3C4A.CLK CLK_2X_c
--------
1.322 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C5A.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 0.205ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i0 (from CLK_2X_c +)
Destination: FF Data in alu_impl_I/alu_impl/alu_lo/akku_i0 (to master_clk +)
Delay: 1.336ns (39.4% logic, 60.6% route), 5 logic levels.
Constraint Details:
1.336ns physical path delay SLICE_90 to alu_impl_I/alu_impl/alu_lo/SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.144ns skew requirement (totaling 1.131ns) by 0.205ns
Physical Path Details:
Data path SLICE_90 to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C4A.CLK to R3C4A.Q0 SLICE_90 (from CLK_2X_c)
ROUTE 1 0.135 R3C4A.Q0 to R3C5C.C0 wb_data_l_0
CTOF_DEL --- 0.099 R3C5C.C0 to R3C5C.F0 alu_impl/SLICE_95
ROUTE 2 0.132 R3C5C.F0 to R3C5C.D1 alu_impl/I_DATA_0
CTOF_DEL --- 0.099 R3C5C.D1 to R3C5C.F1 alu_impl/SLICE_95
ROUTE 3 0.333 R3C5C.F1 to R4C5A.B1 n1254
CTOF_DEL --- 0.099 R4C5A.B1 to R4C5A.F1 SLICE_16
ROUTE 2 0.209 R4C5A.F1 to R5C5C.A0 F_0
CTOF_DEL --- 0.099 R5C5C.A0 to R5C5C.F0 alu_impl_I/alu_impl/alu_lo/SLICE_10
ROUTE 1 0.000 R5C5C.F0 to R5C5C.DI0 alu_impl_I/alu_impl/alu_lo/n1350 (to master_clk)
--------
1.336 (39.4% logic, 60.6% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_90:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R3C4A.CLK CLK_2X_c
--------
1.322 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R5C5C.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 0.208ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_data_l_i0_i6 (from CLK_2X_c +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 1.339ns (43.4% logic, 56.6% route), 5 logic levels.
Constraint Details:
1.339ns physical path delay SLICE_28 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
-1.144ns skew requirement (totaling 1.131ns) by 0.208ns
Physical Path Details:
Data path SLICE_28 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R2C3D.CLK to R2C3D.Q0 SLICE_28 (from CLK_2X_c)
ROUTE 1 0.134 R2C3D.Q0 to R3C3D.C0 wb_data_l_6
CTOF_DEL --- 0.099 R3C3D.C0 to R3C3D.F0 alu_impl/SLICE_93
ROUTE 2 0.057 R3C3D.F0 to R3C3D.C1 alu_impl/I_DATA_6
CTOF_DEL --- 0.099 R3C3D.C1 to R3C3D.F1 alu_impl/SLICE_93
ROUTE 2 0.249 R3C3D.F1 to R4C3A.C0 n6_adj_30
CTOF_DEL --- 0.099 R4C3A.C0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.318 R4C3A.F0 to R4C4C.A0 n2175
CTOOFX_DEL --- 0.153 R4C4C.A0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
1.339 (43.4% logic, 56.6% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to SLICE_28:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C3D.CLK CLK_2X_c
--------
1.322 (33.2% logic, 66.8% route), 1 logic levels.
Destination Clock Path CLK_2X to SLICE_15:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C4C.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
================================================================================
Preference: MULTICYCLE FROM CLKNET "WE_mem" 6.000000 X ;
160 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.655ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem0/RAM1 (from WE_mem +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 1.311ns (47.4% logic, 52.6% route), 4 logic levels.
Constraint Details:
1.311ns physical path delay sram_impl/mem0/SLICE_6 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
1.331ns skew requirement (totaling -1.344ns) by 2.655ns
Physical Path Details:
Data path sram_impl/mem0/SLICE_6 to SLICE_15:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R2C3B.WCK to R2C3B.F1 sram_impl/mem0/SLICE_6 (from WE_mem)
ROUTE 1 0.344 R2C3B.F1 to R3C4C.D0 mem_data_7
CTOF_DEL --- 0.099 R3C4C.D0 to R3C4C.F0 alu_impl/SLICE_92
ROUTE 2 0.207 R3C4C.F0 to R3C4C.A1 alu_impl/I_DATA_7
CTOF_DEL --- 0.099 R3C4C.A1 to R3C4C.F1 alu_impl/SLICE_92
ROUTE 2 0.138 R3C4C.F1 to R4C4C.C0 n1245
CTOOFX_DEL --- 0.153 R4C4C.C0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
1.311 (47.4% logic, 52.6% route), 4 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem0/SLICE_6:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C2A.CLK master_clk
REG_DEL --- 0.151 R3C2A.CLK to R3C2A.Q1 SLICE_17
ROUTE 19 0.229 R3C2A.Q1 to R5C2D.D1 inst_1
CTOF_DEL --- 0.174 R5C2D.D1 to R5C2D.F1 SLICE_88
ROUTE 2 0.407 R5C2D.F1 to R2C2B.C1 WE
CTOF_DEL --- 0.174 R2C2B.C1 to R2C2B.F1 SLICE_24
ROUTE 4 0.196 R2C2B.F1 to R2C3B.WCK WE_mem
--------
3.797 (28.7% logic, 71.3% route), 5 logic levels.
Destination Clock Path CLK_2X to SLICE_15:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C4C.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 2.665ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem0/RAM1 (from WE_mem +)
Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i6 (to master_clk +)
Delay: 1.321ns (50.5% logic, 49.5% route), 5 logic levels.
Constraint Details:
1.321ns physical path delay sram_impl/mem0/SLICE_6 to alu_impl_I/alu_impl/alu_hi/SLICE_13 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
1.331ns skew requirement (totaling -1.344ns) by 2.665ns
Physical Path Details:
Data path sram_impl/mem0/SLICE_6 to alu_impl_I/alu_impl/alu_hi/SLICE_13:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R2C3B.WCK to R2C3B.F0 sram_impl/mem0/SLICE_6 (from WE_mem)
ROUTE 1 0.207 R2C3B.F0 to R3C3D.A0 mem_data_6
CTOF_DEL --- 0.099 R3C3D.A0 to R3C3D.F0 alu_impl/SLICE_93
ROUTE 2 0.057 R3C3D.F0 to R3C3D.C1 alu_impl/I_DATA_6
CTOF_DEL --- 0.099 R3C3D.C1 to R3C3D.F1 alu_impl/SLICE_93
ROUTE 2 0.333 R3C3D.F1 to R4C3B.B1 n6_adj_30
CTOF_DEL --- 0.099 R4C3B.B1 to R4C3B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_13
ROUTE 2 0.057 R4C3B.F1 to R4C3B.C0 F_6
CTOF_DEL --- 0.099 R4C3B.C0 to R4C3B.F0 alu_impl_I/alu_impl/alu_hi/SLICE_13
ROUTE 1 0.000 R4C3B.F0 to R4C3B.DI0 alu_impl_I/alu_impl/alu_hi/n3842 (to master_clk)
--------
1.321 (50.5% logic, 49.5% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem0/SLICE_6:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C2A.CLK master_clk
REG_DEL --- 0.151 R3C2A.CLK to R3C2A.Q1 SLICE_17
ROUTE 19 0.229 R3C2A.Q1 to R5C2D.D1 inst_1
CTOF_DEL --- 0.174 R5C2D.D1 to R5C2D.F1 SLICE_88
ROUTE 2 0.407 R5C2D.F1 to R2C2B.C1 WE
CTOF_DEL --- 0.174 R2C2B.C1 to R2C2B.F1 SLICE_24
ROUTE 4 0.196 R2C2B.F1 to R2C3B.WCK WE_mem
--------
3.797 (28.7% logic, 71.3% route), 5 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_hi/SLICE_13:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C3B.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 2.714ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM1 (from WE_mem +)
Destination: FF Data in alu_impl_I/alu_impl/alu_lo/akku_i2 (to master_clk +)
Delay: 1.370ns (48.7% logic, 51.3% route), 5 logic levels.
Constraint Details:
1.370ns physical path delay sram_impl/mem1/SLICE_9 to alu_impl_I/alu_impl/alu_lo/SLICE_11 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
1.331ns skew requirement (totaling -1.344ns) by 2.714ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_9 to alu_impl_I/alu_impl/alu_lo/SLICE_11:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R2C4B.WCK to R2C4B.F0 sram_impl/mem1/SLICE_9 (from WE_mem)
ROUTE 1 0.300 R2C4B.F0 to R3C6A.B0 mem_data_2
CTOF_DEL --- 0.099 R3C6A.B0 to R3C6A.F0 alu_impl/SLICE_94
ROUTE 2 0.135 R3C6A.F0 to R3C6A.C1 alu_impl/I_DATA_2
CTOF_DEL --- 0.099 R3C6A.C1 to R3C6A.F1 alu_impl/SLICE_94
ROUTE 2 0.135 R3C6A.F1 to R4C6D.D0 n72_adj_27
CTOF_DEL --- 0.099 R4C6D.D0 to R4C6D.F0 SLICE_76
ROUTE 2 0.133 R4C6D.F0 to R4C5D.D0 F_2
CTOF_DEL --- 0.099 R4C5D.D0 to R4C5D.F0 alu_impl_I/alu_impl/alu_lo/SLICE_11
ROUTE 1 0.000 R4C5D.F0 to R4C5D.DI0 alu_impl_I/alu_impl/alu_lo/n1384 (to master_clk)
--------
1.370 (48.7% logic, 51.3% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem1/SLICE_9:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C2A.CLK master_clk
REG_DEL --- 0.151 R3C2A.CLK to R3C2A.Q1 SLICE_17
ROUTE 19 0.229 R3C2A.Q1 to R5C2D.D1 inst_1
CTOF_DEL --- 0.174 R5C2D.D1 to R5C2D.F1 SLICE_88
ROUTE 2 0.407 R5C2D.F1 to R2C2B.C1 WE
CTOF_DEL --- 0.174 R2C2B.C1 to R2C2B.F1 SLICE_24
ROUTE 4 0.196 R2C2B.F1 to R2C4B.WCK WE_mem
--------
3.797 (28.7% logic, 71.3% route), 5 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_lo/SLICE_11:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C5D.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 2.818ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem0/RAM0 (from WE_mem +)
Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i5 (to master_clk +)
Delay: 1.474ns (45.3% logic, 54.7% route), 5 logic levels.
Constraint Details:
1.474ns physical path delay sram_impl/mem0/SLICE_5 to alu_impl_I/alu_impl/alu_hi/SLICE_12 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
1.331ns skew requirement (totaling -1.344ns) by 2.818ns
Physical Path Details:
Data path sram_impl/mem0/SLICE_5 to alu_impl_I/alu_impl/alu_hi/SLICE_12:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R2C3A.WCK to R2C3A.F1 sram_impl/mem0/SLICE_5 (from WE_mem)
ROUTE 1 0.217 R2C3A.F1 to R2C3D.B0 mem_data_5
CTOF_DEL --- 0.099 R2C3D.B0 to R2C3D.F0 SLICE_28
ROUTE 2 0.135 R2C3D.F0 to R3C3C.D1 alu_impl/I_DATA_5
CTOF_DEL --- 0.099 R3C3C.D1 to R3C3C.F1 SLICE_87
ROUTE 2 0.246 R3C3C.F1 to R4C3C.D0 n62
CTOF_DEL --- 0.099 R4C3C.D0 to R4C3C.F0 SLICE_80
ROUTE 2 0.209 R4C3C.F0 to R5C3A.A1 F_5
CTOF_DEL --- 0.099 R5C3A.A1 to R5C3A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_12
ROUTE 1 0.000 R5C3A.F1 to R5C3A.DI1 alu_impl_I/alu_impl/alu_hi/n1369 (to master_clk)
--------
1.474 (45.3% logic, 54.7% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem0/SLICE_5:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C2A.CLK master_clk
REG_DEL --- 0.151 R3C2A.CLK to R3C2A.Q1 SLICE_17
ROUTE 19 0.229 R3C2A.Q1 to R5C2D.D1 inst_1
CTOF_DEL --- 0.174 R5C2D.D1 to R5C2D.F1 SLICE_88
ROUTE 2 0.407 R5C2D.F1 to R2C2B.C1 WE
CTOF_DEL --- 0.174 R2C2B.C1 to R2C2B.F1 SLICE_24
ROUTE 4 0.196 R2C2B.F1 to R2C3A.WCK WE_mem
--------
3.797 (28.7% logic, 71.3% route), 5 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_hi/SLICE_12:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R5C3A.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 2.835ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in alu_impl_I/alu_impl/alu_lo/akku_i1 (to master_clk +)
Delay: 1.491ns (44.7% logic, 55.3% route), 5 logic levels.
Constraint Details:
1.491ns physical path delay sram_impl/mem1/SLICE_8 to alu_impl_I/alu_impl/alu_lo/SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
1.331ns skew requirement (totaling -1.344ns) by 2.835ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R2C4A.WCK to R2C4A.F1 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 1 0.244 R2C4A.F1 to R3C4B.C0 mem_data_1
CTOF_DEL --- 0.099 R3C4B.C0 to R3C4B.F0 alu_impl/SLICE_96
ROUTE 2 0.057 R3C4B.F0 to R3C4B.C1 alu_impl/I_DATA_1
CTOF_DEL --- 0.099 R3C4B.C1 to R3C4B.F1 alu_impl/SLICE_96
ROUTE 2 0.302 R3C4B.F1 to R4C5B.B0 n1255
CTOF_DEL --- 0.099 R4C5B.B0 to R4C5B.F0 SLICE_74
ROUTE 2 0.221 R4C5B.F0 to R5C5C.B1 F_1
CTOF_DEL --- 0.099 R5C5C.B1 to R5C5C.F1 alu_impl_I/alu_impl/alu_lo/SLICE_10
ROUTE 1 0.000 R5C5C.F1 to R5C5C.DI1 alu_impl_I/alu_impl/alu_lo/n1389 (to master_clk)
--------
1.491 (44.7% logic, 55.3% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C2A.CLK master_clk
REG_DEL --- 0.151 R3C2A.CLK to R3C2A.Q1 SLICE_17
ROUTE 19 0.229 R3C2A.Q1 to R5C2D.D1 inst_1
CTOF_DEL --- 0.174 R5C2D.D1 to R5C2D.F1 SLICE_88
ROUTE 2 0.407 R5C2D.F1 to R2C2B.C1 WE
CTOF_DEL --- 0.174 R2C2B.C1 to R2C2B.F1 SLICE_24
ROUTE 4 0.196 R2C2B.F1 to R2C4A.WCK WE_mem
--------
3.797 (28.7% logic, 71.3% route), 5 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R5C5C.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 2.854ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem0/RAM1 (from WE_mem +)
Destination: FF Data in flags_i1 (to master_clk +)
Delay: 1.510ns (44.2% logic, 55.8% route), 5 logic levels.
Constraint Details:
1.510ns physical path delay sram_impl/mem0/SLICE_6 to SLICE_16 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
1.331ns skew requirement (totaling -1.344ns) by 2.854ns
Physical Path Details:
Data path sram_impl/mem0/SLICE_6 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R2C3B.WCK to R2C3B.F0 sram_impl/mem0/SLICE_6 (from WE_mem)
ROUTE 1 0.207 R2C3B.F0 to R3C3D.A0 mem_data_6
CTOF_DEL --- 0.099 R3C3D.A0 to R3C3D.F0 alu_impl/SLICE_93
ROUTE 2 0.057 R3C3D.F0 to R3C3D.C1 alu_impl/I_DATA_6
CTOF_DEL --- 0.099 R3C3D.C1 to R3C3D.F1 alu_impl/SLICE_93
ROUTE 2 0.333 R3C3D.F1 to R4C3B.B1 n6_adj_30
CTOF_DEL --- 0.099 R4C3B.B1 to R4C3B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_13
ROUTE 2 0.246 R4C3B.F1 to R4C5A.C0 F_6
CTOF_DEL --- 0.099 R4C5A.C0 to R4C5A.F0 SLICE_16
ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 Z_out (to master_clk)
--------
1.510 (44.2% logic, 55.8% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem0/SLICE_6:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C2A.CLK master_clk
REG_DEL --- 0.151 R3C2A.CLK to R3C2A.Q1 SLICE_17
ROUTE 19 0.229 R3C2A.Q1 to R5C2D.D1 inst_1
CTOF_DEL --- 0.174 R5C2D.D1 to R5C2D.F1 SLICE_88
ROUTE 2 0.407 R5C2D.F1 to R2C2B.C1 WE
CTOF_DEL --- 0.174 R2C2B.C1 to R2C2B.F1 SLICE_24
ROUTE 4 0.196 R2C2B.F1 to R2C3B.WCK WE_mem
--------
3.797 (28.7% logic, 71.3% route), 5 logic levels.
Destination Clock Path CLK_2X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C5A.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 2.891ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem0/RAM0 (from WE_mem +)
Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i5 (to master_clk +)
Delay: 1.547ns (43.1% logic, 56.9% route), 5 logic levels.
Constraint Details:
1.547ns physical path delay sram_impl/mem0/SLICE_5 to alu_impl_I/alu_impl/alu_hi/SLICE_12 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
1.331ns skew requirement (totaling -1.344ns) by 2.891ns
Physical Path Details:
Data path sram_impl/mem0/SLICE_5 to alu_impl_I/alu_impl/alu_hi/SLICE_12:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R2C3A.WCK to R2C3A.F1 sram_impl/mem0/SLICE_5 (from WE_mem)
ROUTE 1 0.217 R2C3A.F1 to R2C3D.B0 mem_data_5
CTOF_DEL --- 0.099 R2C3D.B0 to R2C3D.F0 SLICE_28
ROUTE 2 0.244 R2C3D.F0 to R3C3A.D1 alu_impl/I_DATA_5
CTOF_DEL --- 0.099 R3C3A.D1 to R3C3A.F1 SLICE_86
ROUTE 2 0.210 R3C3A.F1 to R4C3C.A0 n1243
CTOF_DEL --- 0.099 R4C3C.A0 to R4C3C.F0 SLICE_80
ROUTE 2 0.209 R4C3C.F0 to R5C3A.A1 F_5
CTOF_DEL --- 0.099 R5C3A.A1 to R5C3A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_12
ROUTE 1 0.000 R5C3A.F1 to R5C3A.DI1 alu_impl_I/alu_impl/alu_hi/n1369 (to master_clk)
--------
1.547 (43.1% logic, 56.9% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem0/SLICE_5:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C2A.CLK master_clk
REG_DEL --- 0.151 R3C2A.CLK to R3C2A.Q1 SLICE_17
ROUTE 19 0.229 R3C2A.Q1 to R5C2D.D1 inst_1
CTOF_DEL --- 0.174 R5C2D.D1 to R5C2D.F1 SLICE_88
ROUTE 2 0.407 R5C2D.F1 to R2C2B.C1 WE
CTOF_DEL --- 0.174 R2C2B.C1 to R2C2B.F1 SLICE_24
ROUTE 4 0.196 R2C2B.F1 to R2C3A.WCK WE_mem
--------
3.797 (28.7% logic, 71.3% route), 5 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_hi/SLICE_12:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R5C3A.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 2.896ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem0/RAM1 (from WE_mem +)
Destination: FF Data in flags_i0 (to master_clk +)
Delay: 1.552ns (46.5% logic, 53.5% route), 5 logic levels.
Constraint Details:
1.552ns physical path delay sram_impl/mem0/SLICE_6 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
1.331ns skew requirement (totaling -1.344ns) by 2.896ns
Physical Path Details:
Data path sram_impl/mem0/SLICE_6 to SLICE_15:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R2C3B.WCK to R2C3B.F0 sram_impl/mem0/SLICE_6 (from WE_mem)
ROUTE 1 0.207 R2C3B.F0 to R3C3D.A0 mem_data_6
CTOF_DEL --- 0.099 R3C3D.A0 to R3C3D.F0 alu_impl/SLICE_93
ROUTE 2 0.057 R3C3D.F0 to R3C3D.C1 alu_impl/I_DATA_6
CTOF_DEL --- 0.099 R3C3D.C1 to R3C3D.F1 alu_impl/SLICE_93
ROUTE 2 0.249 R3C3D.F1 to R4C3A.C0 n6_adj_30
CTOF_DEL --- 0.099 R4C3A.C0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.318 R4C3A.F0 to R4C4C.A0 n2175
CTOOFX_DEL --- 0.153 R4C4C.A0 to R4C4C.OFX0 SLICE_15
ROUTE 1 0.000 R4C4C.OFX0 to R4C4C.DI0 n302 (to master_clk)
--------
1.552 (46.5% logic, 53.5% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem0/SLICE_6:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C2A.CLK master_clk
REG_DEL --- 0.151 R3C2A.CLK to R3C2A.Q1 SLICE_17
ROUTE 19 0.229 R3C2A.Q1 to R5C2D.D1 inst_1
CTOF_DEL --- 0.174 R5C2D.D1 to R5C2D.F1 SLICE_88
ROUTE 2 0.407 R5C2D.F1 to R2C2B.C1 WE
CTOF_DEL --- 0.174 R2C2B.C1 to R2C2B.F1 SLICE_24
ROUTE 4 0.196 R2C2B.F1 to R2C3B.WCK WE_mem
--------
3.797 (28.7% logic, 71.3% route), 5 logic levels.
Destination Clock Path CLK_2X to SLICE_15:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C4C.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 2.906ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem0/RAM0 (from WE_mem +)
Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i6 (to master_clk +)
Delay: 1.562ns (49.0% logic, 51.0% route), 6 logic levels.
Constraint Details:
1.562ns physical path delay sram_impl/mem0/SLICE_5 to alu_impl_I/alu_impl/alu_hi/SLICE_13 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
1.331ns skew requirement (totaling -1.344ns) by 2.906ns
Physical Path Details:
Data path sram_impl/mem0/SLICE_5 to alu_impl_I/alu_impl/alu_hi/SLICE_13:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R2C3A.WCK to R2C3A.F1 sram_impl/mem0/SLICE_5 (from WE_mem)
ROUTE 1 0.217 R2C3A.F1 to R2C3D.B0 mem_data_5
CTOF_DEL --- 0.099 R2C3D.B0 to R2C3D.F0 SLICE_28
ROUTE 2 0.135 R2C3D.F0 to R3C3C.D1 alu_impl/I_DATA_5
CTOF_DEL --- 0.099 R3C3C.D1 to R3C3C.F1 SLICE_87
ROUTE 2 0.333 R3C3C.F1 to R4C3A.B1 n62
CTOF_DEL --- 0.099 R4C3A.B1 to R4C3A.F1 alu_impl/alu_impl/alu_hi/SLICE_102
ROUTE 2 0.054 R4C3A.F1 to R4C3B.D1 n2187
CTOF_DEL --- 0.099 R4C3B.D1 to R4C3B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_13
ROUTE 2 0.057 R4C3B.F1 to R4C3B.C0 F_6
CTOF_DEL --- 0.099 R4C3B.C0 to R4C3B.F0 alu_impl_I/alu_impl/alu_hi/SLICE_13
ROUTE 1 0.000 R4C3B.F0 to R4C3B.DI0 alu_impl_I/alu_impl/alu_hi/n3842 (to master_clk)
--------
1.562 (49.0% logic, 51.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem0/SLICE_5:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C2A.CLK master_clk
REG_DEL --- 0.151 R3C2A.CLK to R3C2A.Q1 SLICE_17
ROUTE 19 0.229 R3C2A.Q1 to R5C2D.D1 inst_1
CTOF_DEL --- 0.174 R5C2D.D1 to R5C2D.F1 SLICE_88
ROUTE 2 0.407 R5C2D.F1 to R2C2B.C1 WE
CTOF_DEL --- 0.174 R2C2B.C1 to R2C2B.F1 SLICE_24
ROUTE 4 0.196 R2C2B.F1 to R2C3A.WCK WE_mem
--------
3.797 (28.7% logic, 71.3% route), 5 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_hi/SLICE_13:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C3B.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Passed: The following path meets requirements by 2.918ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM1 (from WE_mem +)
Destination: FF Data in alu_impl_I/alu_impl/alu_lo/akku_i3 (to master_clk +)
Delay: 1.574ns (42.4% logic, 57.6% route), 5 logic levels.
Constraint Details:
1.574ns physical path delay sram_impl/mem1/SLICE_9 to alu_impl_I/alu_impl/alu_lo/SLICE_11 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
1.331ns skew requirement (totaling -1.344ns) by 2.918ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_9 to alu_impl_I/alu_impl/alu_lo/SLICE_11:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R2C4B.WCK to R2C4B.F1 sram_impl/mem1/SLICE_9 (from WE_mem)
ROUTE 1 0.345 R2C4B.F1 to R3C6D.D0 mem_data_3
CTOF_DEL --- 0.099 R3C6D.D0 to R3C6D.F0 alu_impl/SLICE_97
ROUTE 2 0.134 R3C6D.F0 to R4C6C.D1 alu_impl/I_DATA_3
CTOF_DEL --- 0.099 R4C6C.D1 to R4C6C.F1 SLICE_75
ROUTE 3 0.220 R4C6C.F1 to R4C6C.B0 n1257
CTOF_DEL --- 0.099 R4C6C.B0 to R4C6C.F0 SLICE_75
ROUTE 2 0.208 R4C6C.F0 to R4C5D.A1 F_3
CTOF_DEL --- 0.099 R4C5D.A1 to R4C5D.F1 alu_impl_I/alu_impl/alu_lo/SLICE_11
ROUTE 1 0.000 R4C5D.F1 to R4C5D.DI1 alu_impl_I/alu_impl/alu_lo/n1379 (to master_clk)
--------
1.574 (42.4% logic, 57.6% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_2X to sram_impl/mem1/SLICE_9:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R3C2A.CLK master_clk
REG_DEL --- 0.151 R3C2A.CLK to R3C2A.Q1 SLICE_17
ROUTE 19 0.229 R3C2A.Q1 to R5C2D.D1 inst_1
CTOF_DEL --- 0.174 R5C2D.D1 to R5C2D.F1 SLICE_88
ROUTE 2 0.407 R5C2D.F1 to R2C2B.C1 WE
CTOF_DEL --- 0.174 R2C2B.C1 to R2C2B.F1 SLICE_24
ROUTE 4 0.196 R2C2B.F1 to R2C4B.WCK WE_mem
--------
3.797 (28.7% logic, 71.3% route), 5 logic levels.
Destination Clock Path CLK_2X to alu_impl_I/alu_impl/alu_lo/SLICE_11:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_2X
ROUTE 8 0.883 12.PADDI to R2C5A.CLK CLK_2X_c
REG_DEL --- 0.151 R2C5A.CLK to R2C5A.Q0 SLICE_19
ROUTE 14 0.993 R2C5A.Q0 to R4C5D.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "CLK_2X" 48.000000 MHz ; | -| -| 1 *
| | |
MULTICYCLE FROM GROUP "code" TO GROUP | | |
"akku" 4.000000 X ; | -| -| 3
| | |
MULTICYCLE FROM GROUP "efb" TO GROUP | | |
"akku" 2.000000 X ; | -| -| 5 *
| | |
MULTICYCLE FROM CLKNET "WE_mem" | | |
6.000000 X ; | -| -| 4
| | |
----------------------------------------------------------------------------
2 preferences(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
code_data_3 | 13| 76| 23.68%
| | |
code_data_2 | 13| 76| 23.68%
| | |
code_data_0 | 13| 76| 23.68%
| | |
code_data_1 | 13| 76| 23.68%
| | |
pc_4 | 61| 64| 19.94%
| | |
pc_3 | 68| 64| 19.94%
| | |
pc_2 | 68| 64| 19.94%
| | |
pc_1 | 67| 64| 19.94%
| | |
sram_impl/mem1/AD3_INT | 2| 38| 11.84%
| | |
sram_impl/mem1/AD2_INT | 2| 38| 11.84%
| | |
sram_impl/mem1/AD1_INT | 2| 38| 11.84%
| | |
sram_impl/mem1/AD0_INT | 2| 38| 11.84%
| | |
sram_impl/mem0/AD3_INT | 2| 38| 11.84%
| | |
sram_impl/mem0/AD2_INT | 2| 38| 11.84%
| | |
sram_impl/mem0/AD1_INT | 2| 38| 11.84%
| | |
sram_impl/mem0/AD0_INT | 2| 38| 11.84%
| | |
mux_126_Mux_0_1_f5b | 1| 36| 11.21%
| | |
mux_126_Mux_0_0_f5a | 1| 36| 11.21%
| | |
mux_126_Mux_3_1_f5b | 1| 36| 11.21%
| | |
mux_126_Mux_3_0_f5a | 1| 36| 11.21%
| | |
mux_126_Mux_2_1_f5b | 1| 36| 11.21%
| | |
mux_126_Mux_2_0_f5a | 1| 36| 11.21%
| | |
mux_126_Mux_1_1_f5b | 1| 36| 11.21%
| | |
mux_126_Mux_1_0_f5a | 1| 36| 11.21%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 6 clocks:
Clock Domain: CLK_2X_c Source: CLK_2X.PAD Loads: 8
Covered under: FREQUENCY PORT "CLK_2X" 48.000000 MHz ;
Data transfers from:
Clock Domain: master_clk Source: SLICE_19.Q0
Covered under: FREQUENCY PORT "CLK_2X" 48.000000 MHz ; Transfers: 14
Clock Domain: i2c1_sclo Source: efb_impl/EFBInst_0.I2C1SCLO Loads: 1
No transfer within this clock domain is found
Clock Domain: i2c1_scli Source: SCL.PAD Loads: 1
No transfer within this clock domain is found
Clock Domain: master_clk Source: SLICE_19.Q0 Loads: 14
Covered under: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 4.000000 X ;
Covered under: FREQUENCY PORT "CLK_2X" 48.000000 MHz ;
Data transfers from:
Clock Domain: CLK_2X_c Source: CLK_2X.PAD
Covered under: MULTICYCLE FROM GROUP "efb" TO GROUP "akku" 2.000000 X ; Transfers: 8
Clock Domain: WE_mem Source: SLICE_24.F1
Covered under: MULTICYCLE FROM CLKNET "WE_mem" 6.000000 X ; Transfers: 8
Clock Domain: O_STB_c Source: SLICE_88.F0 Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: master_clk Source: SLICE_19.Q0
Covered under: FREQUENCY PORT "CLK_2X" 48.000000 MHz ; Transfers: 8
Clock Domain: WE_mem Source: SLICE_24.F1 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: master_clk Source: SLICE_19.Q0
Covered under: FREQUENCY PORT "CLK_2X" 48.000000 MHz ; Transfers: 14
Timing summary (Hold):
---------------
Timing errors: 321 Score: 689883
Cumulative negative slack: 689883
Constraints cover 41516 paths, 9 nets, and 965 connections (96.9% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 321 (hold)
Score: 0 (setup), 689883 (hold)
Cumulative negative slack: 689883 (0+689883)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------