Synthesis and Ngdbuild  Report
synthesis:  version Diamond_1.4_Production (87) 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp.   All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved. Copyright (c) 2001 Agere Systems   All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.
Fri Jun 22 16:24:01 2012 

Command Line:  synthesis -f qfn32samples_dac_lattice.synproj 

-- all messages logged in file synthesis.log

Synthesis Options

INFO: Synthesis Options: (LSE-1022)
INFO: -a option is = MachXO2
INFO: -s option is = 4
INFO: -t option is = TQFP100
INFO: -d option is = LCMXO2-256HC
INFO: Using package TQFP100
INFO: Using performance grade 4
INFO:                                                           
INFO: ##########################################################
INFO: ### Lattice Family : MachXO2
INFO: ### Device  : LCMXO2-256HC
INFO: ### Package : TQFP100
INFO: ### Speed   : 4
INFO: ##########################################################
INFO:                                                           
INFO: Optimization Goal = Area
INFO: -top option is not used
WARNING: Ignoring Frequency option in Area Mode, Setting to default frequency of 1.0 MHz
INFO: Target Frequency = 1.000000 MHz
INFO: Max Fanout = 1000
INFO: Timing Path count = 3
INFO: bram Utilization = 100.000000 %
INFO: dsp usage = TRUE (default)
INFO: dsp utilization = 100 (default)
INFO: fsm_encoding_style = auto
INFO: Mux style = Auto
INFO: Use Carry Chain = TRUE
INFO: carry_chain_length = 0
INFO: Use IO Insertion = TRUE
INFO: Use IO Reg = TRUE
INFO: Resource Sharing = TRUE
INFO: Propagate Constants = TRUE
INFO: Remove Duplicate Registers = TRUE
INFO: force_gsr = auto
INFO: ROM style = auto
INFO: RAM style = auto
INFO: -comp option is FALSE
INFO: -syn option is FALSE
INFO: -p Z:/XC2C/qfn32samples-06 (searchpath added)
INFO: -p Y:/Program_Files/lscc/diamond/1.4/ispfpga/xo2c00/data (searchpath added)
INFO: -p Z:/XC2C/qfn32samples-06/dac (searchpath added)
INFO: -p Z:/XC2C/qfn32samples-06 (searchpath added)
INFO: Verilog design file = Z:/XC2C/qfn32samples-06/src/dac_pwm3.v
INFO: Ngd file = qfn32samples_dac.ngd
INFO: -sdc option: sdc file input not used
INFO: -lpf option: output file option is OFF
INFO: hardtimer checking is enabled (default); -dt option not used
INFO: -r option is OFF [ Remove LOC Properties is OFF ]
-- Technology check ok...MachXO, MachXO2...
INFO: The default vhdl library search path is now "y:/program_files/lscc/diamond/1.4/cae_library/vhdl_packages/vdbs" (VHDL-1504)
INFO: * compile design *

Compile Design

INFO: Compile Design Begin
z:/xc2c/qfn32samples-06/src/dac_pwm3.v(16): INFO: compiling module dac3 (VERI-1018)
INFO: ######## Missing driver on net : n286, patching with GND... (LSE-1017)


INFO: GSR Instance connected to net: n1 (LSE-1148)
INFO: GSR will not be inferred since no asynchronous signal was found in netlist (LSE-1147)
INFO: Duplicate Register/Latch removal : r_data2_i0_i0 is one to one match with r_data2_i0_i2
WARNING: No lpf file will be written because -lpf option is not used or set to 0
INFO: Applying 1.000000 MHz constraint to all clocks (LSE-5000)
INFO: Results of ngd drc checks are available in dac3_drc.log
INFO: All blocks are expanded and NGD expansion is successful
INFO: Writing ngd file qfn32samples_dac.ngd

################### Begin Area Report (dac3)######################
Number of register bits => 37 of 1192 (3 % )
CCU2D => 8
FD1P3AX => 3
FD1P3JX => 15
FD1S3AX => 2
FD1S3IX => 14
GSR => 1
IB => 18
INV => 2
LUT4 => 27
OB => 3
OBZ => 1
OFS1P3DX => 3
PFUMX => 1
################### End Area Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 1
  Net : CLK_c, loads : 37
Clock Enable Nets
Number of Clock Enables: 2
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : n39, loads : 33
  Net : count_13, loads : 17
  Net : n359, loads : 15
  Net : I_DATA_c_14, loads : 3
  Net : r_data_14, loads : 3
  Net : r_data_13, loads : 3
  Net : count_12, loads : 3
  Net : count_11, loads : 3
  Net : count_10, loads : 3
  Net : count_9, loads : 3
################### End Clock Report ##################

Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk0 [get_nets CLK_c]                   |    1.000 MHz|   43.461 MHz|    16  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.


Peak Memory Usage: 39.871  MB

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Elapsed CPU time for LSE flow : 2.891  secs
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