Synthesis and Ngdbuild Report synthesis: version Diamond_1.4_Production (87) Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Tue Jun 26 09:44:56 2012 Command Line: synthesis -f qfn32samples_mcpu3_lattice.synproj -- all messages logged in file synthesis.log Synthesis Options INFO: Synthesis Options: (LSE-1022) INFO: -a option is = MachXO2 INFO: -s option is = 4 INFO: -t option is = QFN32 INFO: -d option is = LCMXO2-256HC INFO: Using package QFN32 INFO: Using performance grade 4 INFO: INFO: ########################################################## INFO: ### Lattice Family : MachXO2 INFO: ### Device : LCMXO2-256HC INFO: ### Package : QFN32 INFO: ### Speed : 4 INFO: ########################################################## INFO: INFO: Optimization Goal = Area INFO: -top option is not used WARNING: Ignoring Frequency option in Area Mode, Setting to default frequency of 1.0 MHz INFO: Target Frequency = 1.000000 MHz INFO: Max Fanout = 1000 INFO: Timing Path count = 3 INFO: bram Utilization = 100.000000 % INFO: dsp usage = TRUE (default) INFO: dsp utilization = 100 (default) INFO: fsm_encoding_style = auto INFO: Mux style = Auto INFO: Use Carry Chain = TRUE INFO: carry_chain_length = 0 INFO: Use IO Insertion = TRUE INFO: Use IO Reg = TRUE INFO: Resource Sharing = TRUE INFO: Propagate Constants = TRUE INFO: Remove Duplicate Registers = TRUE INFO: force_gsr = auto INFO: ROM style = auto INFO: RAM style = auto INFO: -comp option is FALSE INFO: -syn option is FALSE INFO: -p Z:/XC2C/xo2qfn-w08 (searchpath added) INFO: -p Y:/Program_Files/lscc/diamond/1.4/ispfpga/xo2c00/data (searchpath added) INFO: -p Z:/XC2C/xo2qfn-w08/mcpu3 (searchpath added) INFO: -p Z:/XC2C/xo2qfn-w08 (searchpath added) INFO: Verilog design file = Z:/XC2C/xo2qfn-w08/src/alu4.v INFO: Verilog design file = Z:/XC2C/xo2qfn-w08/src/alu8.v INFO: Verilog design file = Z:/XC2C/xo2qfn-w08/src/rtavr_alu2.v INFO: Verilog design file = Z:/XC2C/xo2qfn-w08/src/mcpu3.v INFO: Ngd file = qfn32samples_mcpu3.ngd INFO: -sdc option: sdc file input not used INFO: -lpf option: output file option is OFF INFO: hardtimer checking is enabled (default); -dt option not used INFO: -r option is OFF [ Remove LOC Properties is OFF ] -- Technology check ok...MachXO, MachXO2... INFO: The default vhdl library search path is now "y:/program_files/lscc/diamond/1.4/cae_library/vhdl_packages/vdbs" (VHDL-1504) INFO: * compile design * Compile Design INFO: Compile Design Begin z:/xc2c/xo2qfn-w08/src/mcpu3.v(76): INFO: compiling module mcpu (VERI-1018) z:/xc2c/xo2qfn-w08/src/mcpu3.v(305): INFO: compiling module sram (VERI-1018) z:/xc2c/xo2qfn-w08/src/mcpu3.v(352): INFO: compiling module rom (VERI-1018) z:/xc2c/xo2qfn-w08/src/rtavr_alu2.v(41): INFO: compiling module rtavr_alu (VERI-1018) z:/xc2c/xo2qfn-w08/src/alu8.v(54): INFO: compiling module alu8 (VERI-1018) z:/xc2c/xo2qfn-w08/src/alu4.v(54): INFO: compiling module alu4 (VERI-1018) z:/xc2c/xo2qfn-w08/src/mcpu3.v(362): WARNING: ram mem_original_ramnet has no write-port on it (VDB-1038) INFO: ######## Converting i/o port : SCL to INPUT ... (LSE-1068) INFO: ######## Converting i/o port : SDA to INPUT ... (LSE-1068) INFO: ######## Found 1 RAM Nets in design (LSE-1115) INFO: ######## Mapping RAM Net \sram_impl/mem to 2 Distributed blocks in SINGLE_PORT Mode INFO: GSR Instance connected to net: n1 (LSE-1148) INFO: GSR will not be inferred since no asynchronous signal was found in netlist (LSE-1147) WARNING: No lpf file will be written because -lpf option is not used or set to 0 INFO: Applying 1.000000 MHz constraint to all clocks (LSE-5000) INFO: Results of ngd drc checks are available in mcpu_drc.log INFO: All blocks are expanded and NGD expansion is successful INFO: Writing ngd file qfn32samples_mcpu3.ngd ################### Begin Area Report (mcpu)###################### Number of register bits => 28 of 1090 (2 % ) CCU2D => 4 FD1P3IX => 10 FD1S3IX => 10 GSR => 1 IB => 2 L6MUX21 => 3 LUT4 => 124 OB => 9 OFS1P3DX => 8 PFUMX => 25 ROM64X1A => 13 SPR16X4C => 2 ################### End Area Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 3 Net : CLK_c, loads : 19 Net : O_STB_c, loads : 9 Net : WE_mem, loads : 2 Clock Enable Nets Number of Clock Enables: 5 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : pc_2, loads : 30 Net : pc_1, loads : 30 Net : pc_0, loads : 30 Net : pc_3, loads : 28 Net : RST_c, loads : 22 Net : pc_4, loads : 21 Net : inst_2, loads : 19 Net : inst_1, loads : 19 Net : inst_0, loads : 18 Net : int_c, loads : 18 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 1000.000000 -name | | | clk1 [get_nets CLK_c] | 1.000 MHz| 42.510 MHz| 15 | | | create_clock -period 1000.000000 -name | | | clk0 [get_nets O_STB_c] | -| -| 0 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 44.324 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 7.016 secs --------------------------------------------------------------