Lattice Mapping Report File for Design Module 'udrv' Design Information Command line: map -a MachXO2 -p LCMXO2-256HC -t QFN32 -s 4 -oc Commercial qfn32samples_udrv.ngd -o qfn32samples_udrv_map.ncd -pr qfn32samples_udrv.prf -mp qfn32samples_udrv.mrp Z:/XC2C/xo2qfn-w11/src/udrv_spi.lpf -c 0 Target Vendor: LATTICE Target Device: LCMXO2-256HCQFN32 Target Performance: 4 Mapper: xo2c00, version: Diamond_1.4_Production (87) Mapped on: 07/06/12 15:59:32 Design Summary Number of registers: 141 PFU registers: 138 PIO registers: 3 Number of SLICEs: 121 out of 128 (95%) SLICEs(logic/ROM): 32 out of 32 (100%) SLICEs(logic/ROM/RAM): 89 out of 96 (93%) As RAM: 12 out of 96 (13%) As Logic/ROM: 77 out of 96 (80%) Number of logic LUT4s: 214 Number of distributed RAM: 12 (24 LUT4s) Number of ripple logic: 0 (0 LUT4s) Number of shift registers: 0 Total number of LUT4s: 238 Number of PIO sites used: 14 out of 22 (64%) Number of block RAMs: 0 out of 0 Number of GSRs: 1 out of 1 (100%) EFB used : No JTAG used : No Readback used : No Oscillator used : No Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 1 out of 2 (50%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 4 Net CLK: 78 loads, 48 rising, 30 falling (Driver: clkgen_impl/clk_ph_333__i1 ) Net i_clk4x: 4 loads, 4 rising, 0 falling (Driver: clk_selector ) Net SCK_c: 15 loads, 2 rising, 13 falling (Driver: PIO SCK ) Net MOSI_c: 1 loads, 1 rising, 0 falling (Driver: PIO MOSI ) Number of Clock Enables: 35 Net n114: 1 loads, 1 LSLICEs Net SYNC_ACK: 1 loads, 1 LSLICEs Net n935: 1 loads, 1 LSLICEs Net DOE: 1 loads, 1 LSLICEs Net dummy_i_rdy: 1 loads, 1 LSLICEs Net S_DATA_RDY: 1 loads, 1 LSLICEs Net recv_stat: 2 loads, 2 LSLICEs Net n425: 2 loads, 2 LSLICEs Net spi_impl/n311: 4 loads, 4 LSLICEs Net spi_impl/n956: 1 loads, 1 LSLICEs Net sender_impl/n965: 1 loads, 1 LSLICEs Net sender_impl/n185: 1 loads, 1 LSLICEs Net sender_impl/n286: 2 loads, 2 LSLICEs Net sender_impl/n949: 3 loads, 3 LSLICEs Net sender_impl/n2853: 1 loads, 1 LSLICEs Net sender_impl/n357: 1 loads, 1 LSLICEs Net sender_impl/n288: 4 loads, 4 LSLICEs Net sender_impl/n2847: 1 loads, 1 LSLICEs Net sender_impl/n2641: 1 loads, 1 LSLICEs Net crc16_impl/n954: 3 loads, 3 LSLICEs Net crc16_impl/n1043: 7 loads, 7 LSLICEs Net clkgen_impl/n21: 1 loads, 1 LSLICEs Net reciever_impl/n249: 4 loads, 4 LSLICEs Net reciever_impl/n42: 1 loads, 1 LSLICEs Net reciever_impl/n244: 4 loads, 4 LSLICEs Net reciever_impl/n194: 1 loads, 1 LSLICEs Net reciever_impl/n56: 1 loads, 1 LSLICEs Net reciever_impl/n2859: 1 loads, 1 LSLICEs Net n937: 2 loads, 2 LSLICEs Net n4_adj_15: 1 loads, 1 LSLICEs Net crc5r_impl/n984: 2 loads, 2 LSLICEs Net crc5r_impl/n1025: 2 loads, 2 LSLICEs Net fifo_impl/n994: 3 loads, 3 LSLICEs Net fifo_impl/n416: 2 loads, 2 LSLICEs Net fifo_impl/n787: 1 loads, 1 LSLICEs Number of LSRs: 27 Net n113: 1 loads, 1 LSLICEs Net n1717: 1 loads, 1 LSLICEs Net FIFO_RST: 4 loads, 4 LSLICEs Net n1015: 1 loads, 1 LSLICEs Net recv_stat: 1 loads, 1 LSLICEs Net n3105: 9 loads, 9 LSLICEs Net n425: 1 loads, 1 LSLICEs Net n2682: 1 loads, 1 LSLICEs Net spi_impl/r_count_0: 1 loads, 1 LSLICEs Net spi_impl/n5: 1 loads, 1 LSLICEs Net sender_impl/n185: 9 loads, 9 LSLICEs Net sender_impl/n1038: 3 loads, 3 LSLICEs Net sender_impl/n5: 1 loads, 1 LSLICEs Net sender_impl/n691: 1 loads, 1 LSLICEs Net sender_impl/n1787: 1 loads, 1 LSLICEs Net sender_impl/n2639: 1 loads, 1 LSLICEs Net sender_impl/n298: 2 loads, 2 LSLICEs Net sender_impl/n5_adj_4: 1 loads, 1 LSLICEs Net sender_impl/n1033: 1 loads, 1 LSLICEs Net crc16_impl/n953: 10 loads, 10 LSLICEs Net clkgen_impl/SYNC_REQ: 1 loads, 1 LSLICEs Net reciever_impl/n1771: 2 loads, 2 LSLICEs Net reciever_impl/data_set: 1 loads, 1 LSLICEs Net reciever_impl/n1609: 1 loads, 1 LSLICEs Net crc5r_impl/n13: 5 loads, 5 LSLICEs Net fifo_impl/n660: 1 loads, 1 LSLICEs Net fifo_impl/n1569: 3 loads, 3 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net i_recv_mode: 32 loads Net fifo_impl/o_addr_0: 22 loads Net fifo_impl/o_addr_1: 22 loads Net fifo_impl/o_addr_2: 21 loads Net fifo_impl/o_addr_3: 19 loads Net r_send_en: 17 loads Net recv_stat: 16 loads Net n3105: 15 loads Net fifo_impl/i_addr_0: 13 loads Net RS_c: 13 loads Number of warnings: 2 Number of errors: 0 Tristate register sender_impl/r_oe_133$r0 is replicated for DM_pad Design Errors/Warnings WARNING: The JTAG port has been disabled in this project and JTAG pins will be configured as General Purpose IO. You have to use JTAGENB pin in hardware to change the personality of the port from JTAG pins to general purpose IO. Reference MACHXO2 Handbook for details on dual function JTAG port. WARNING: All configuration ports of the design have been disabled. Reference MachXO2 Handbook for information on the Configuration Ports of MachXO2 IO (PIO) Attributes +---------------------+-----------+-----------+------------+ | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | +---------------------+-----------+-----------+------------+ | RS | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | CLK_OUT | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | nCS | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | SCK | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | nBUSY | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | MOSI | INPUT | LVCMOS25 | IN | +---------------------+-----------+-----------+------------+ | CLK_4X | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | nCRC_ERROR | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | MISO | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | nDATA_RDY | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | nDATA_EMPTY | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | nDATA_FULL | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | DM | BIDIR | LVCMOS25 | TRI | +---------------------+-----------+-----------+------------+ | DP | BIDIR | LVCMOS25 | TRI | +---------------------+-----------+-----------+------------+ Removed logic Signal n1028 was merged into signal dummy_i_rdy Signal reciever_impl/n8 was merged into signal recv_stat Signal n3104 was merged into signal CLK Signal spi_impl/n12 was merged into signal SCK_c Signal n310 was merged into signal nCS_c Signal VCC_net undriven or does not drive anything - clipped. Block i950 was optimized away. Block reciever_impl/equal_111_i2 was optimized away. Block crc16_impl/i7 was optimized away. Block spi_impl/i12 was optimized away. Block spi_impl/i227 was optimized away. Block i2 was optimized away. Memory Usage /: EBRs: 0 RAM SLICEs: 6 Logic SLICEs: 59 PFU Registers: 70 /fifo_impl/mem0: EBRs: 0 RAM SLICEs: 1 Logic SLICEs: 0 PFU Registers: 0 /fifo_impl/mem1: EBRs: 0 RAM SLICEs: 1 Logic SLICEs: 0 PFU Registers: 0 /fifo_impl/mem2: EBRs: 0 RAM SLICEs: 1 Logic SLICEs: 0 PFU Registers: 0 /fifo_impl/mem3: EBRs: 0 RAM SLICEs: 3 Logic SLICEs: 0 PFU Registers: 0 DCMA Summary ------------ DCMA 1: Pin/Node Value DCMA Instance Name: clk_selector DCMA Type: DCMA CLK0 Input: PIN CLK_4X_c CLK1 Input: NODE GND_net SEL Input: NONE DCMOUT Output: NODE i_clk4x ASIC Components --------------- Instance Name: clk_selector Type: DCMA GSR Usage --------- GSR Component: The Global Set Reset (GSR) resource has been used to implement a global reset of the design. The reset signal used for GSR control is 'nCS_c'. GSR Property: The design components with GSR property set to ENABLED will respond to global set reset while the components with GSR property set to DISABLED will not. Components with disabled GSR Property ------------------------------------- These components have the GSR property set to DISABLED. The components will not respond to the reset signal 'nCS_c' via the GSR component. Type and number of components of the type: Register = 128 Type and instance name of component: Register : r_se0_91 Register : r_recv_mode1_92 Register : dummy_o_ack_93 Register : r_sync_req1_97 Register : r_recv_en1_98 Register : r_sync_req_99 Register : r_recv_en_100 Register : r_dpr_90 Register : r_start_96 Register : r_recv_mode_95 Register : dummy_i_rdy_94 Register : spi_impl/spi_out_i0_i0 Register : spi_impl/spi_out_i0_i7 Register : spi_impl/spi_out_i0_i6 Register : spi_impl/spi_out_i0_i5 Register : spi_impl/spi_out_i0_i4 Register : spi_impl/spi_out_i0_i3 Register : spi_impl/spi_out_i0_i2 Register : spi_impl/spi_out_i0_i1 Register : spi_impl/i_data_ack_36 Register : spi_impl/r_mosi_35 Register : sender_impl/r_send_en_101 Register : sender_impl/r_out_140 Register : sender_impl/data_bytes_i0_i2 Register : sender_impl/data_bytes_i0_i1 Register : sender_impl/data_count_i3 Register : sender_impl/data_bytes_i0_i0 Register : sender_impl/data_count_i2 Register : sender_impl/crc16_sel_i0 Register : sender_impl/crc_out_134 Register : sender_impl/r_dm_146 Register : sender_impl/data_in_i0 Register : sender_impl/r_dp_145 Register : sender_impl/data_count_i0 Register : sender_impl/data_ack_147 Register : sender_impl/send_stat_i0 Register : sender_impl/data_count_i1 Register : sender_impl/r_oe_133 Register : sender_impl/one_count_338__i0 Register : sender_impl/send_stat_i2 Register : sender_impl/send_stat_i1 Register : sender_impl/crc16_extract_142 Register : sender_impl/crc16_sel_i1 Register : sender_impl/data_in_i1 Register : sender_impl/data_in_i2 Register : sender_impl/data_in_i3 Register : sender_impl/data_in_i4 Register : sender_impl/data_in_i5 Register : sender_impl/data_in_i6 Register : sender_impl/one_count_338__i1 Register : sender_impl/one_count_338__i2 Register : sender_impl/use_crc16_143 Register : crc16_impl/r_crc_i0 Register : crc16_impl/r_crc_i1 Register : crc16_impl/r_crc_i15 Register : crc16_impl/r_crc_i2 Register : crc16_impl/r_crc_i3 Register : crc16_impl/r_crc_i4 Register : crc16_impl/r_crc_i5 Register : crc16_impl/r_crc_i6 Register : crc16_impl/r_crc_i7 Register : crc16_impl/r_crc_i8 Register : crc16_impl/r_crc_i9 Register : crc16_impl/r_crc_i10 Register : crc16_impl/r_crc_i11 Register : crc16_impl/r_crc_i12 Register : crc16_impl/r_crc_i14 Register : crc16_impl/r_crc_i13 Register : clkgen_impl/r_done_24 Register : clkgen_impl/r_dp_22 Register : clkgen_impl/clk_ph_333__i0 Register : clkgen_impl/clk_ph_333__i1 Register : reciever_impl/data_out_i0_i3 Register : reciever_impl/data_out_i0_i2 Register : reciever_impl/data_out_i0_i1 Register : reciever_impl/one_count_i0_i2 Register : reciever_impl/crc16_sel_i1 Register : reciever_impl/r_data__i7 Register : reciever_impl/r_data__i1 Register : reciever_impl/r_dp_97 Register : reciever_impl/r_o_98 Register : reciever_impl/data_set_108 Register : reciever_impl/data_rdy_109 Register : reciever_impl/data_ack_96 Register : reciever_impl/r_data__i6 Register : reciever_impl/r_data__i5 Register : reciever_impl/r_data__i4 Register : reciever_impl/r_data__i3 Register : reciever_impl/r_data__i2 Register : reciever_impl/data_out_i0_i0 Register : reciever_impl/data_count_i0_i0 Register : reciever_impl/data_out_i0_i4 Register : reciever_impl/data_bytes_337__i1 Register : reciever_impl/one_count_i0_i1 Register : reciever_impl/crc16_sel_i0 Register : reciever_impl/data_bytes_337__i0 Register : reciever_impl/r_match_sel_106 Register : reciever_impl/data_out_i0_i7 Register : reciever_impl/data_out_i0_i6 Register : reciever_impl/recv_stat_99 Register : reciever_impl/data_out_i0_i5 Register : reciever_impl/data_count_i0_i1 Register : reciever_impl/data_count_i0_i2 Register : reciever_impl/one_count_i0_i0 Register : crc5r_impl/r_crc_i4 Register : crc5r_impl/r_crc_i0 Register : crc5r_impl/crc5_sel_i0 Register : crc5r_impl/crc5_sel_i1 Register : crc5r_impl/r_match_22 Register : crc5r_impl/r_crc_i1 Register : crc5r_impl/r_crc_i3 Register : crc5r_impl/r_crc_i2 Register : fifo_impl/i_addr_i0_i0 Register : fifo_impl/o_ack_42 Register : fifo_impl/i_ack_45 Register : fifo_impl/o_rdy_46 Register : fifo_impl/i_rdy_41 Register : fifo_impl/o_addr_335__i0 Register : fifo_impl/o_addr_335__i4 Register : fifo_impl/i_addr_i0_i4 Register : fifo_impl/i_addr_i0_i3 Register : fifo_impl/i_addr_i0_i2 Register : fifo_impl/o_addr_335__i3 Register : fifo_impl/i_addr_i0_i1 Register : fifo_impl/r_full_47 Register : fifo_impl/o_addr_335__i2 Register : fifo_impl/o_addr_335__i1 Register : sender_impl/r_oe_133$r0 Components with synchronous local reset also reset by asynchronous GSR ---------------------------------------------------------------------- These components have the GSR property set to ENABLED and the local reset is synchronous. The components will respond to the synchronous local reset and to the unrelated asynchronous reset signal 'nCS_c' via the GSR component. Type and number of components of the type: Register = 1 Type and instance name of component: Register : spi_impl/r_count_339__i0 Run Time and Memory Usage ------------------------- Total CPU Time: 1 secs Total REAL Time: 11 secs Peak Memory Usage: 26 MB Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.