Place & Route TRACE Report

Loading design for application trce from file qfn32samples_mcpu2.ncd.
Design name: mcpu
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-256HC
Package:     QFN32
Performance: 4
Loading device for application trce from file 'xo2c256.nph' in environment: Y:/Program_Files/lscc/diamond/1.4/ispfpga.
Package Status:                     Advanced       Version 1.34
Performance Hardware Data Status:   Final)         Version 22.4
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond_1.4_Production (87)
Mon Jun 25 10:57:43 2012

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_mcpu2.twr qfn32samples_mcpu2.ncd qfn32samples_mcpu2.prf 
Design file:     qfn32samples_mcpu2.ncd
Preference file: qfn32samples_mcpu2.prf
Device,speed:    LCMXO2-256HC,4
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY PORT "CLK" 60.000000 MHz (18 errors)
  • 745 items scored, 18 timing errors detected. Warning: 56.411MHz is the maximum frequency for this preference.
  • MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.500000 X (0 errors)
  • 3927 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "CLK" 60.000000 MHz ; 745 items scored, 18 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 1.061ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem0/RAM0 (from WE_mem +) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 6.151ns (57.9% logic, 42.1% route), 4 logic levels. Constraint Details: 6.151ns physical path delay SLICE_13 to SLICE_18 exceeds 16.666ns delay constraint less 11.410ns skew and 0.166ns DIN_SET requirement (totaling 5.090ns) by 1.061ns Physical Path Details: Data path SLICE_13 to SLICE_18: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R4C4A.WCK to R4C4A.F0 SLICE_13 (from WE_mem) ROUTE 2 1.429 R4C4A.F0 to R5C4C.B0 mem_data_4 C0TOFCO_DE --- 1.023 R5C4C.B0 to R5C4C.FCO SLICE_5 ROUTE 1 0.000 R5C4C.FCO to R5C4D.FCI n1332 FCITOF1_DE --- 0.643 R5C4D.FCI to R5C4D.F1 SLICE_4 ROUTE 1 1.163 R5C4D.F1 to R5C3D.C1 n765 CTOF_DEL --- 0.495 R5C3D.C1 to R5C3D.F1 SLICE_18 ROUTE 1 0.000 R5C3D.F1 to R5C3D.DI1 n130 (to CLK_c) -------- 6.151 (57.9% logic, 42.1% route), 4 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.452 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 1.802 R4C4A.Q0 to R2C6D.B1 r_addr_0 CTOOFX_DEL --- 0.721 R2C6D.B1 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.241 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.623 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.721 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.241 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 1.364 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 1.862 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.495 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.445 R5C6D.F0 to R5C6D.C1 n9 CTOF_DEL --- 0.495 R5C6D.C1 to R5C6D.F1 SLICE_52 ROUTE 4 1.453 R5C6D.F1 to R4C4A.WCK WE_mem -------- 16.220 (32.3% logic, 67.7% route), 9 logic levels. Destination Clock Path CLK to SLICE_18: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R5C3D.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Error: The following path exceeds requirements by 0.927ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem0/RAM0 (from WE_mem +) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 6.017ns (56.9% logic, 43.1% route), 4 logic levels. Constraint Details: 6.017ns physical path delay SLICE_13 to SLICE_18 exceeds 16.666ns delay constraint less 11.410ns skew and 0.166ns DIN_SET requirement (totaling 5.090ns) by 0.927ns Physical Path Details: Data path SLICE_13 to SLICE_18: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R4C4A.WCK to R4C4A.F1 SLICE_13 (from WE_mem) ROUTE 2 1.429 R4C4A.F1 to R5C4C.B1 mem_data_5 C1TOFCO_DE --- 0.889 R5C4C.B1 to R5C4C.FCO SLICE_5 ROUTE 1 0.000 R5C4C.FCO to R5C4D.FCI n1332 FCITOF1_DE --- 0.643 R5C4D.FCI to R5C4D.F1 SLICE_4 ROUTE 1 1.163 R5C4D.F1 to R5C3D.C1 n765 CTOF_DEL --- 0.495 R5C3D.C1 to R5C3D.F1 SLICE_18 ROUTE 1 0.000 R5C3D.F1 to R5C3D.DI1 n130 (to CLK_c) -------- 6.017 (56.9% logic, 43.1% route), 4 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.452 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 1.802 R4C4A.Q0 to R2C6D.B1 r_addr_0 CTOOFX_DEL --- 0.721 R2C6D.B1 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.241 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.623 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.721 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.241 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 1.364 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 1.862 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.495 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.445 R5C6D.F0 to R5C6D.C1 n9 CTOF_DEL --- 0.495 R5C6D.C1 to R5C6D.F1 SLICE_52 ROUTE 4 1.453 R5C6D.F1 to R4C4A.WCK WE_mem -------- 16.220 (32.3% logic, 67.7% route), 9 logic levels. Destination Clock Path CLK to SLICE_18: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R5C3D.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Error: The following path exceeds requirements by 0.857ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 6.781ns (57.3% logic, 42.7% route), 6 logic levels. Constraint Details: 6.781ns physical path delay sram_impl/mem1/SLICE_10 to SLICE_18 exceeds 16.666ns delay constraint less 10.576ns skew and 0.166ns DIN_SET requirement (totaling 5.924ns) by 0.857ns Physical Path Details: Data path sram_impl/mem1/SLICE_10 to SLICE_18: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6A.WCK to R5C6A.F0 sram_impl/mem1/SLICE_10 (from WE_mem) ROUTE 2 1.735 R5C6A.F0 to R5C4A.A0 mem_data_0 C0TOFCO_DE --- 1.023 R5C4A.A0 to R5C4A.FCO SLICE_8 ROUTE 1 0.000 R5C4A.FCO to R5C4B.FCI n1330 FCITOFCO_D --- 0.162 R5C4B.FCI to R5C4B.FCO SLICE_7 ROUTE 1 0.000 R5C4B.FCO to R5C4C.FCI n1331 FCITOFCO_D --- 0.162 R5C4C.FCI to R5C4C.FCO SLICE_5 ROUTE 1 0.000 R5C4C.FCO to R5C4D.FCI n1332 FCITOF1_DE --- 0.643 R5C4D.FCI to R5C4D.F1 SLICE_4 ROUTE 1 1.163 R5C4D.F1 to R5C3D.C1 n765 CTOF_DEL --- 0.495 R5C3D.C1 to R5C3D.F1 SLICE_18 ROUTE 1 0.000 R5C3D.F1 to R5C3D.DI1 n130 (to CLK_c) -------- 6.781 (57.3% logic, 42.7% route), 6 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_10: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.452 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 1.802 R4C4A.Q0 to R2C6D.B1 r_addr_0 CTOOFX_DEL --- 0.721 R2C6D.B1 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.241 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.623 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.721 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.241 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 1.364 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 1.862 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.495 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.445 R5C6D.F0 to R5C6D.C1 n9 CTOF_DEL --- 0.495 R5C6D.C1 to R5C6D.F1 SLICE_52 ROUTE 4 0.619 R5C6D.F1 to R5C6A.WCK WE_mem -------- 15.386 (34.0% logic, 66.0% route), 9 logic levels. Destination Clock Path CLK to SLICE_18: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R5C3D.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Error: The following path exceeds requirements by 0.807ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM1 (from WE_mem +) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 6.731ns (55.3% logic, 44.7% route), 5 logic levels. Constraint Details: 6.731ns physical path delay sram_impl/mem1/SLICE_11 to SLICE_18 exceeds 16.666ns delay constraint less 10.576ns skew and 0.166ns DIN_SET requirement (totaling 5.924ns) by 0.807ns Physical Path Details: Data path sram_impl/mem1/SLICE_11 to SLICE_18: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6B.WCK to R5C6B.F0 sram_impl/mem1/SLICE_11 (from WE_mem) ROUTE 2 1.847 R5C6B.F0 to R5C4B.A0 mem_data_2 C0TOFCO_DE --- 1.023 R5C4B.A0 to R5C4B.FCO SLICE_7 ROUTE 1 0.000 R5C4B.FCO to R5C4C.FCI n1331 FCITOFCO_D --- 0.162 R5C4C.FCI to R5C4C.FCO SLICE_5 ROUTE 1 0.000 R5C4C.FCO to R5C4D.FCI n1332 FCITOF1_DE --- 0.643 R5C4D.FCI to R5C4D.F1 SLICE_4 ROUTE 1 1.163 R5C4D.F1 to R5C3D.C1 n765 CTOF_DEL --- 0.495 R5C3D.C1 to R5C3D.F1 SLICE_18 ROUTE 1 0.000 R5C3D.F1 to R5C3D.DI1 n130 (to CLK_c) -------- 6.731 (55.3% logic, 44.7% route), 5 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_11: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.452 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 1.802 R4C4A.Q0 to R2C6D.B1 r_addr_0 CTOOFX_DEL --- 0.721 R2C6D.B1 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.241 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.623 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.721 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.241 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 1.364 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 1.862 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.495 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.445 R5C6D.F0 to R5C6D.C1 n9 CTOF_DEL --- 0.495 R5C6D.C1 to R5C6D.F1 SLICE_52 ROUTE 4 0.619 R5C6D.F1 to R5C6B.WCK WE_mem -------- 15.386 (34.0% logic, 66.0% route), 9 logic levels. Destination Clock Path CLK to SLICE_18: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R5C3D.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Error: The following path exceeds requirements by 0.697ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +) Destination: FF Data in akku_i2 (to CLK_c +) Delay: 6.621ns (52.9% logic, 47.1% route), 4 logic levels. Constraint Details: 6.621ns physical path delay sram_impl/mem1/SLICE_10 to SLICE_16 exceeds 16.666ns delay constraint less 10.576ns skew and 0.166ns DIN_SET requirement (totaling 5.924ns) by 0.697ns Physical Path Details: Data path sram_impl/mem1/SLICE_10 to SLICE_16: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6A.WCK to R5C6A.F0 sram_impl/mem1/SLICE_10 (from WE_mem) ROUTE 2 1.735 R5C6A.F0 to R5C4A.A0 mem_data_0 C0TOFCO_DE --- 1.023 R5C4A.A0 to R5C4A.FCO SLICE_8 ROUTE 1 0.000 R5C4A.FCO to R5C4B.FCI n1330 FCITOF0_DE --- 0.585 R5C4B.FCI to R5C4B.F0 SLICE_7 ROUTE 1 1.385 R5C4B.F0 to R5C5D.D0 n770 CTOF_DEL --- 0.495 R5C5D.D0 to R5C5D.F0 SLICE_16 ROUTE 1 0.000 R5C5D.F0 to R5C5D.DI0 n135 (to CLK_c) -------- 6.621 (52.9% logic, 47.1% route), 4 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_10: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.452 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 1.802 R4C4A.Q0 to R2C6D.B1 r_addr_0 CTOOFX_DEL --- 0.721 R2C6D.B1 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.241 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.623 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.721 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.241 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 1.364 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 1.862 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.495 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.445 R5C6D.F0 to R5C6D.C1 n9 CTOF_DEL --- 0.495 R5C6D.C1 to R5C6D.F1 SLICE_52 ROUTE 4 0.619 R5C6D.F1 to R5C6A.WCK WE_mem -------- 15.386 (34.0% logic, 66.0% route), 9 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R5C5D.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Error: The following path exceeds requirements by 0.604ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +) Destination: FF Data in akku_i5 (to CLK_c +) Delay: 6.528ns (57.0% logic, 43.0% route), 5 logic levels. Constraint Details: 6.528ns physical path delay sram_impl/mem1/SLICE_10 to SLICE_17 exceeds 16.666ns delay constraint less 10.576ns skew and 0.166ns DIN_SET requirement (totaling 5.924ns) by 0.604ns Physical Path Details: Data path sram_impl/mem1/SLICE_10 to SLICE_17: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6A.WCK to R5C6A.F0 sram_impl/mem1/SLICE_10 (from WE_mem) ROUTE 2 1.735 R5C6A.F0 to R5C4A.A0 mem_data_0 C0TOFCO_DE --- 1.023 R5C4A.A0 to R5C4A.FCO SLICE_8 ROUTE 1 0.000 R5C4A.FCO to R5C4B.FCI n1330 FCITOFCO_D --- 0.162 R5C4B.FCI to R5C4B.FCO SLICE_7 ROUTE 1 0.000 R5C4B.FCO to R5C4C.FCI n1331 FCITOF1_DE --- 0.643 R5C4C.FCI to R5C4C.F1 SLICE_5 ROUTE 1 1.072 R5C4C.F1 to R4C4D.D1 n767 CTOF_DEL --- 0.495 R4C4D.D1 to R4C4D.F1 SLICE_17 ROUTE 1 0.000 R4C4D.F1 to R4C4D.DI1 n132 (to CLK_c) -------- 6.528 (57.0% logic, 43.0% route), 5 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_10: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.452 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 1.802 R4C4A.Q0 to R2C6D.B1 r_addr_0 CTOOFX_DEL --- 0.721 R2C6D.B1 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.241 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.623 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.721 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.241 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 1.364 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 1.862 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.495 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.445 R5C6D.F0 to R5C6D.C1 n9 CTOF_DEL --- 0.495 R5C6D.C1 to R5C6D.F1 SLICE_52 ROUTE 4 0.619 R5C6D.F1 to R5C6A.WCK WE_mem -------- 15.386 (34.0% logic, 66.0% route), 9 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R4C4D.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Error: The following path exceeds requirements by 0.554ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM1 (from WE_mem +) Destination: FF Data in akku_i5 (to CLK_c +) Delay: 6.478ns (54.9% logic, 45.1% route), 4 logic levels. Constraint Details: 6.478ns physical path delay sram_impl/mem1/SLICE_11 to SLICE_17 exceeds 16.666ns delay constraint less 10.576ns skew and 0.166ns DIN_SET requirement (totaling 5.924ns) by 0.554ns Physical Path Details: Data path sram_impl/mem1/SLICE_11 to SLICE_17: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6B.WCK to R5C6B.F0 sram_impl/mem1/SLICE_11 (from WE_mem) ROUTE 2 1.847 R5C6B.F0 to R5C4B.A0 mem_data_2 C0TOFCO_DE --- 1.023 R5C4B.A0 to R5C4B.FCO SLICE_7 ROUTE 1 0.000 R5C4B.FCO to R5C4C.FCI n1331 FCITOF1_DE --- 0.643 R5C4C.FCI to R5C4C.F1 SLICE_5 ROUTE 1 1.072 R5C4C.F1 to R4C4D.D1 n767 CTOF_DEL --- 0.495 R4C4D.D1 to R4C4D.F1 SLICE_17 ROUTE 1 0.000 R4C4D.F1 to R4C4D.DI1 n132 (to CLK_c) -------- 6.478 (54.9% logic, 45.1% route), 4 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_11: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.452 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 1.802 R4C4A.Q0 to R2C6D.B1 r_addr_0 CTOOFX_DEL --- 0.721 R2C6D.B1 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.241 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.623 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.721 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.241 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 1.364 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 1.862 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.495 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.445 R5C6D.F0 to R5C6D.C1 n9 CTOF_DEL --- 0.495 R5C6D.C1 to R5C6D.F1 SLICE_52 ROUTE 4 0.619 R5C6D.F1 to R5C6B.WCK WE_mem -------- 15.386 (34.0% logic, 66.0% route), 9 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R4C4D.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Error: The following path exceeds requirements by 0.475ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +) Destination: FF Data in akku_i4 (to CLK_c +) Delay: 6.399ns (57.2% logic, 42.8% route), 5 logic levels. Constraint Details: 6.399ns physical path delay sram_impl/mem1/SLICE_10 to SLICE_17 exceeds 16.666ns delay constraint less 10.576ns skew and 0.166ns DIN_SET requirement (totaling 5.924ns) by 0.475ns Physical Path Details: Data path sram_impl/mem1/SLICE_10 to SLICE_17: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6A.WCK to R5C6A.F0 sram_impl/mem1/SLICE_10 (from WE_mem) ROUTE 2 1.735 R5C6A.F0 to R5C4A.A0 mem_data_0 C0TOFCO_DE --- 1.023 R5C4A.A0 to R5C4A.FCO SLICE_8 ROUTE 1 0.000 R5C4A.FCO to R5C4B.FCI n1330 FCITOFCO_D --- 0.162 R5C4B.FCI to R5C4B.FCO SLICE_7 ROUTE 1 0.000 R5C4B.FCO to R5C4C.FCI n1331 FCITOF0_DE --- 0.585 R5C4C.FCI to R5C4C.F0 SLICE_5 ROUTE 1 1.001 R5C4C.F0 to R4C4D.B0 n768 CTOF_DEL --- 0.495 R4C4D.B0 to R4C4D.F0 SLICE_17 ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 n133 (to CLK_c) -------- 6.399 (57.2% logic, 42.8% route), 5 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_10: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.452 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 1.802 R4C4A.Q0 to R2C6D.B1 r_addr_0 CTOOFX_DEL --- 0.721 R2C6D.B1 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.241 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.623 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.721 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.241 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 1.364 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 1.862 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.495 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.445 R5C6D.F0 to R5C6D.C1 n9 CTOF_DEL --- 0.495 R5C6D.C1 to R5C6D.F1 SLICE_52 ROUTE 4 0.619 R5C6D.F1 to R5C6A.WCK WE_mem -------- 15.386 (34.0% logic, 66.0% route), 9 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R4C4D.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Error: The following path exceeds requirements by 0.463ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem0/RAM0 (from WE_mem +) Destination: FF Data in akku_i6 (to CLK_c +) Delay: 5.553ns (63.0% logic, 37.0% route), 4 logic levels. Constraint Details: 5.553ns physical path delay SLICE_13 to SLICE_18 exceeds 16.666ns delay constraint less 11.410ns skew and 0.166ns DIN_SET requirement (totaling 5.090ns) by 0.463ns Physical Path Details: Data path SLICE_13 to SLICE_18: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R4C4A.WCK to R4C4A.F0 SLICE_13 (from WE_mem) ROUTE 2 1.429 R4C4A.F0 to R5C4C.B0 mem_data_4 C0TOFCO_DE --- 1.023 R5C4C.B0 to R5C4C.FCO SLICE_5 ROUTE 1 0.000 R5C4C.FCO to R5C4D.FCI n1332 FCITOF0_DE --- 0.585 R5C4D.FCI to R5C4D.F0 SLICE_4 ROUTE 1 0.623 R5C4D.F0 to R5C3D.D0 n766 CTOF_DEL --- 0.495 R5C3D.D0 to R5C3D.F0 SLICE_18 ROUTE 1 0.000 R5C3D.F0 to R5C3D.DI0 n131 (to CLK_c) -------- 5.553 (63.0% logic, 37.0% route), 4 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.452 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 1.802 R4C4A.Q0 to R2C6D.B1 r_addr_0 CTOOFX_DEL --- 0.721 R2C6D.B1 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.241 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.623 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.721 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.241 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 1.364 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 1.862 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.495 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.445 R5C6D.F0 to R5C6D.C1 n9 CTOF_DEL --- 0.495 R5C6D.C1 to R5C6D.F1 SLICE_52 ROUTE 4 1.453 R5C6D.F1 to R4C4A.WCK WE_mem -------- 16.220 (32.3% logic, 67.7% route), 9 logic levels. Destination Clock Path CLK to SLICE_18: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R5C3D.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Error: The following path exceeds requirements by 0.425ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM1 (from WE_mem +) Destination: FF Data in akku_i4 (to CLK_c +) Delay: 6.349ns (55.1% logic, 44.9% route), 4 logic levels. Constraint Details: 6.349ns physical path delay sram_impl/mem1/SLICE_11 to SLICE_17 exceeds 16.666ns delay constraint less 10.576ns skew and 0.166ns DIN_SET requirement (totaling 5.924ns) by 0.425ns Physical Path Details: Data path sram_impl/mem1/SLICE_11 to SLICE_17: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6B.WCK to R5C6B.F0 sram_impl/mem1/SLICE_11 (from WE_mem) ROUTE 2 1.847 R5C6B.F0 to R5C4B.A0 mem_data_2 C0TOFCO_DE --- 1.023 R5C4B.A0 to R5C4B.FCO SLICE_7 ROUTE 1 0.000 R5C4B.FCO to R5C4C.FCI n1331 FCITOF0_DE --- 0.585 R5C4C.FCI to R5C4C.F0 SLICE_5 ROUTE 1 1.001 R5C4C.F0 to R4C4D.B0 n768 CTOF_DEL --- 0.495 R4C4D.B0 to R4C4D.F0 SLICE_17 ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 n133 (to CLK_c) -------- 6.349 (55.1% logic, 44.9% route), 4 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_11: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.452 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 1.802 R4C4A.Q0 to R2C6D.B1 r_addr_0 CTOOFX_DEL --- 0.721 R2C6D.B1 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.241 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.623 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.721 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.241 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 1.364 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 1.862 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.495 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.445 R5C6D.F0 to R5C6D.C1 n9 CTOF_DEL --- 0.495 R5C6D.C1 to R5C6D.F1 SLICE_52 ROUTE 4 0.619 R5C6D.F1 to R5C6B.WCK WE_mem -------- 15.386 (34.0% logic, 66.0% route), 9 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 15 3.438 12.PADDI to R4C4D.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Warning: 56.411MHz is the maximum frequency for this preference. ================================================================================ Preference: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.500000 X ; 3927 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 4.906ns (weighted slack = 7.359ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 11.594ns (37.9% logic, 62.1% route), 9 logic levels. Constraint Details: 11.594ns physical path delay SLICE_28 to SLICE_18 meets 16.666ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 16.500ns) by 4.906ns Physical Path Details: Data path SLICE_28 to SLICE_18: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5C.CLK to R4C5C.Q0 SLICE_28 (from CLK_c) ROUTE 37 2.343 R4C5C.Q0 to R4C5A.D1 r_addr_4 CTOOFX_DEL --- 0.721 R4C5A.D1 to R4C5A.OFX0 rom_impl/SLICE_51 ROUTE 1 0.000 R4C5A.OFX0 to R4C5A.FXB rom_impl/mux_53_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R4C5A.FXB to R4C5A.OFX1 rom_impl/SLICE_51 ROUTE 11 1.959 R4C5A.OFX1 to R5C6A.B0 code_data_1 CTOF_DEL --- 0.495 R5C6A.B0 to R5C6A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 1.735 R5C6A.F0 to R5C4A.A0 mem_data_0 C0TOFCO_DE --- 1.023 R5C4A.A0 to R5C4A.FCO SLICE_8 ROUTE 1 0.000 R5C4A.FCO to R5C4B.FCI n1330 FCITOFCO_D --- 0.162 R5C4B.FCI to R5C4B.FCO SLICE_7 ROUTE 1 0.000 R5C4B.FCO to R5C4C.FCI n1331 FCITOFCO_D --- 0.162 R5C4C.FCI to R5C4C.FCO SLICE_5 ROUTE 1 0.000 R5C4C.FCO to R5C4D.FCI n1332 FCITOF1_DE --- 0.643 R5C4D.FCI to R5C4D.F1 SLICE_4 ROUTE 1 1.163 R5C4D.F1 to R5C3D.C1 n765 CTOF_DEL --- 0.495 R5C3D.C1 to R5C3D.F1 SLICE_18 ROUTE 1 0.000 R5C3D.F1 to R5C3D.DI1 n130 (to CLK_c) -------- 11.594 (37.9% logic, 62.1% route), 9 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R4C5C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R5C3D.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 4.906ns (weighted slack = 7.359ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 11.594ns (37.9% logic, 62.1% route), 9 logic levels. Constraint Details: 11.594ns physical path delay SLICE_28 to SLICE_18 meets 16.666ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 16.500ns) by 4.906ns Physical Path Details: Data path SLICE_28 to SLICE_18: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5C.CLK to R4C5C.Q0 SLICE_28 (from CLK_c) ROUTE 37 2.343 R4C5C.Q0 to R4C5A.D0 r_addr_4 CTOOFX_DEL --- 0.721 R4C5A.D0 to R4C5A.OFX0 rom_impl/SLICE_51 ROUTE 1 0.000 R4C5A.OFX0 to R4C5A.FXB rom_impl/mux_53_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R4C5A.FXB to R4C5A.OFX1 rom_impl/SLICE_51 ROUTE 11 1.959 R4C5A.OFX1 to R5C6A.B0 code_data_1 CTOF_DEL --- 0.495 R5C6A.B0 to R5C6A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 1.735 R5C6A.F0 to R5C4A.A0 mem_data_0 C0TOFCO_DE --- 1.023 R5C4A.A0 to R5C4A.FCO SLICE_8 ROUTE 1 0.000 R5C4A.FCO to R5C4B.FCI n1330 FCITOFCO_D --- 0.162 R5C4B.FCI to R5C4B.FCO SLICE_7 ROUTE 1 0.000 R5C4B.FCO to R5C4C.FCI n1331 FCITOFCO_D --- 0.162 R5C4C.FCI to R5C4C.FCO SLICE_5 ROUTE 1 0.000 R5C4C.FCO to R5C4D.FCI n1332 FCITOF1_DE --- 0.643 R5C4D.FCI to R5C4D.F1 SLICE_4 ROUTE 1 1.163 R5C4D.F1 to R5C3D.C1 n765 CTOF_DEL --- 0.495 R5C3D.C1 to R5C3D.F1 SLICE_18 ROUTE 1 0.000 R5C3D.F1 to R5C3D.DI1 n130 (to CLK_c) -------- 11.594 (37.9% logic, 62.1% route), 9 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R4C5C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R5C3D.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 4.956ns (weighted slack = 7.434ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 11.544ns (36.7% logic, 63.3% route), 8 logic levels. Constraint Details: 11.544ns physical path delay SLICE_28 to SLICE_18 meets 16.666ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 16.500ns) by 4.956ns Physical Path Details: Data path SLICE_28 to SLICE_18: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5C.CLK to R4C5C.Q0 SLICE_28 (from CLK_c) ROUTE 37 2.343 R4C5C.Q0 to R4C5A.D1 r_addr_4 CTOOFX_DEL --- 0.721 R4C5A.D1 to R4C5A.OFX0 rom_impl/SLICE_51 ROUTE 1 0.000 R4C5A.OFX0 to R4C5A.FXB rom_impl/mux_53_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R4C5A.FXB to R4C5A.OFX1 rom_impl/SLICE_51 ROUTE 11 1.959 R4C5A.OFX1 to R5C6B.B0 code_data_1 CTOF_DEL --- 0.495 R5C6B.B0 to R5C6B.F0 sram_impl/mem1/SLICE_11 ROUTE 2 1.847 R5C6B.F0 to R5C4B.A0 mem_data_2 C0TOFCO_DE --- 1.023 R5C4B.A0 to R5C4B.FCO SLICE_7 ROUTE 1 0.000 R5C4B.FCO to R5C4C.FCI n1331 FCITOFCO_D --- 0.162 R5C4C.FCI to R5C4C.FCO SLICE_5 ROUTE 1 0.000 R5C4C.FCO to R5C4D.FCI n1332 FCITOF1_DE --- 0.643 R5C4D.FCI to R5C4D.F1 SLICE_4 ROUTE 1 1.163 R5C4D.F1 to R5C3D.C1 n765 CTOF_DEL --- 0.495 R5C3D.C1 to R5C3D.F1 SLICE_18 ROUTE 1 0.000 R5C3D.F1 to R5C3D.DI1 n130 (to CLK_c) -------- 11.544 (36.7% logic, 63.3% route), 8 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R4C5C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R5C3D.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 4.956ns (weighted slack = 7.434ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 11.544ns (36.7% logic, 63.3% route), 8 logic levels. Constraint Details: 11.544ns physical path delay SLICE_28 to SLICE_18 meets 16.666ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 16.500ns) by 4.956ns Physical Path Details: Data path SLICE_28 to SLICE_18: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5C.CLK to R4C5C.Q0 SLICE_28 (from CLK_c) ROUTE 37 2.343 R4C5C.Q0 to R4C5A.D0 r_addr_4 CTOOFX_DEL --- 0.721 R4C5A.D0 to R4C5A.OFX0 rom_impl/SLICE_51 ROUTE 1 0.000 R4C5A.OFX0 to R4C5A.FXB rom_impl/mux_53_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R4C5A.FXB to R4C5A.OFX1 rom_impl/SLICE_51 ROUTE 11 1.959 R4C5A.OFX1 to R5C6B.B0 code_data_1 CTOF_DEL --- 0.495 R5C6B.B0 to R5C6B.F0 sram_impl/mem1/SLICE_11 ROUTE 2 1.847 R5C6B.F0 to R5C4B.A0 mem_data_2 C0TOFCO_DE --- 1.023 R5C4B.A0 to R5C4B.FCO SLICE_7 ROUTE 1 0.000 R5C4B.FCO to R5C4C.FCI n1331 FCITOFCO_D --- 0.162 R5C4C.FCI to R5C4C.FCO SLICE_5 ROUTE 1 0.000 R5C4C.FCO to R5C4D.FCI n1332 FCITOF1_DE --- 0.643 R5C4D.FCI to R5C4D.F1 SLICE_4 ROUTE 1 1.163 R5C4D.F1 to R5C3D.C1 n765 CTOF_DEL --- 0.495 R5C3D.C1 to R5C3D.F1 SLICE_18 ROUTE 1 0.000 R5C3D.F1 to R5C3D.DI1 n130 (to CLK_c) -------- 11.544 (36.7% logic, 63.3% route), 8 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R4C5C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R5C3D.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 5.066ns (weighted slack = 7.599ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in akku_i2 (to CLK_c +) Delay: 11.434ns (35.1% logic, 64.9% route), 7 logic levels. Constraint Details: 11.434ns physical path delay SLICE_28 to SLICE_16 meets 16.666ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 16.500ns) by 5.066ns Physical Path Details: Data path SLICE_28 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5C.CLK to R4C5C.Q0 SLICE_28 (from CLK_c) ROUTE 37 2.343 R4C5C.Q0 to R4C5A.D1 r_addr_4 CTOOFX_DEL --- 0.721 R4C5A.D1 to R4C5A.OFX0 rom_impl/SLICE_51 ROUTE 1 0.000 R4C5A.OFX0 to R4C5A.FXB rom_impl/mux_53_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R4C5A.FXB to R4C5A.OFX1 rom_impl/SLICE_51 ROUTE 11 1.959 R4C5A.OFX1 to R5C6A.B0 code_data_1 CTOF_DEL --- 0.495 R5C6A.B0 to R5C6A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 1.735 R5C6A.F0 to R5C4A.A0 mem_data_0 C0TOFCO_DE --- 1.023 R5C4A.A0 to R5C4A.FCO SLICE_8 ROUTE 1 0.000 R5C4A.FCO to R5C4B.FCI n1330 FCITOF0_DE --- 0.585 R5C4B.FCI to R5C4B.F0 SLICE_7 ROUTE 1 1.385 R5C4B.F0 to R5C5D.D0 n770 CTOF_DEL --- 0.495 R5C5D.D0 to R5C5D.F0 SLICE_16 ROUTE 1 0.000 R5C5D.F0 to R5C5D.DI0 n135 (to CLK_c) -------- 11.434 (35.1% logic, 64.9% route), 7 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R4C5C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R5C5D.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 5.066ns (weighted slack = 7.599ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in akku_i2 (to CLK_c +) Delay: 11.434ns (35.1% logic, 64.9% route), 7 logic levels. Constraint Details: 11.434ns physical path delay SLICE_28 to SLICE_16 meets 16.666ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 16.500ns) by 5.066ns Physical Path Details: Data path SLICE_28 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5C.CLK to R4C5C.Q0 SLICE_28 (from CLK_c) ROUTE 37 2.343 R4C5C.Q0 to R4C5A.D0 r_addr_4 CTOOFX_DEL --- 0.721 R4C5A.D0 to R4C5A.OFX0 rom_impl/SLICE_51 ROUTE 1 0.000 R4C5A.OFX0 to R4C5A.FXB rom_impl/mux_53_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R4C5A.FXB to R4C5A.OFX1 rom_impl/SLICE_51 ROUTE 11 1.959 R4C5A.OFX1 to R5C6A.B0 code_data_1 CTOF_DEL --- 0.495 R5C6A.B0 to R5C6A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 1.735 R5C6A.F0 to R5C4A.A0 mem_data_0 C0TOFCO_DE --- 1.023 R5C4A.A0 to R5C4A.FCO SLICE_8 ROUTE 1 0.000 R5C4A.FCO to R5C4B.FCI n1330 FCITOF0_DE --- 0.585 R5C4B.FCI to R5C4B.F0 SLICE_7 ROUTE 1 1.385 R5C4B.F0 to R5C5D.D0 n770 CTOF_DEL --- 0.495 R5C5D.D0 to R5C5D.F0 SLICE_16 ROUTE 1 0.000 R5C5D.F0 to R5C5D.DI0 n135 (to CLK_c) -------- 11.434 (35.1% logic, 64.9% route), 7 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R4C5C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R5C5D.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 5.159ns (weighted slack = 7.738ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in akku_i5 (to CLK_c +) Delay: 11.341ns (37.3% logic, 62.7% route), 8 logic levels. Constraint Details: 11.341ns physical path delay SLICE_28 to SLICE_17 meets 16.666ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 16.500ns) by 5.159ns Physical Path Details: Data path SLICE_28 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5C.CLK to R4C5C.Q0 SLICE_28 (from CLK_c) ROUTE 37 2.343 R4C5C.Q0 to R4C5A.D1 r_addr_4 CTOOFX_DEL --- 0.721 R4C5A.D1 to R4C5A.OFX0 rom_impl/SLICE_51 ROUTE 1 0.000 R4C5A.OFX0 to R4C5A.FXB rom_impl/mux_53_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R4C5A.FXB to R4C5A.OFX1 rom_impl/SLICE_51 ROUTE 11 1.959 R4C5A.OFX1 to R5C6A.B0 code_data_1 CTOF_DEL --- 0.495 R5C6A.B0 to R5C6A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 1.735 R5C6A.F0 to R5C4A.A0 mem_data_0 C0TOFCO_DE --- 1.023 R5C4A.A0 to R5C4A.FCO SLICE_8 ROUTE 1 0.000 R5C4A.FCO to R5C4B.FCI n1330 FCITOFCO_D --- 0.162 R5C4B.FCI to R5C4B.FCO SLICE_7 ROUTE 1 0.000 R5C4B.FCO to R5C4C.FCI n1331 FCITOF1_DE --- 0.643 R5C4C.FCI to R5C4C.F1 SLICE_5 ROUTE 1 1.072 R5C4C.F1 to R4C4D.D1 n767 CTOF_DEL --- 0.495 R4C4D.D1 to R4C4D.F1 SLICE_17 ROUTE 1 0.000 R4C4D.F1 to R4C4D.DI1 n132 (to CLK_c) -------- 11.341 (37.3% logic, 62.7% route), 8 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R4C5C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R4C4D.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 5.159ns (weighted slack = 7.738ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in akku_i5 (to CLK_c +) Delay: 11.341ns (37.3% logic, 62.7% route), 8 logic levels. Constraint Details: 11.341ns physical path delay SLICE_28 to SLICE_17 meets 16.666ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 16.500ns) by 5.159ns Physical Path Details: Data path SLICE_28 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5C.CLK to R4C5C.Q0 SLICE_28 (from CLK_c) ROUTE 37 2.343 R4C5C.Q0 to R4C5A.D0 r_addr_4 CTOOFX_DEL --- 0.721 R4C5A.D0 to R4C5A.OFX0 rom_impl/SLICE_51 ROUTE 1 0.000 R4C5A.OFX0 to R4C5A.FXB rom_impl/mux_53_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R4C5A.FXB to R4C5A.OFX1 rom_impl/SLICE_51 ROUTE 11 1.959 R4C5A.OFX1 to R5C6A.B0 code_data_1 CTOF_DEL --- 0.495 R5C6A.B0 to R5C6A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 1.735 R5C6A.F0 to R5C4A.A0 mem_data_0 C0TOFCO_DE --- 1.023 R5C4A.A0 to R5C4A.FCO SLICE_8 ROUTE 1 0.000 R5C4A.FCO to R5C4B.FCI n1330 FCITOFCO_D --- 0.162 R5C4B.FCI to R5C4B.FCO SLICE_7 ROUTE 1 0.000 R5C4B.FCO to R5C4C.FCI n1331 FCITOF1_DE --- 0.643 R5C4C.FCI to R5C4C.F1 SLICE_5 ROUTE 1 1.072 R5C4C.F1 to R4C4D.D1 n767 CTOF_DEL --- 0.495 R4C4D.D1 to R4C4D.F1 SLICE_17 ROUTE 1 0.000 R4C4D.F1 to R4C4D.DI1 n132 (to CLK_c) -------- 11.341 (37.3% logic, 62.7% route), 8 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R4C5C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R4C4D.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 5.209ns (weighted slack = 7.813ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in akku_i5 (to CLK_c +) Delay: 11.291ns (36.0% logic, 64.0% route), 7 logic levels. Constraint Details: 11.291ns physical path delay SLICE_28 to SLICE_17 meets 16.666ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 16.500ns) by 5.209ns Physical Path Details: Data path SLICE_28 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5C.CLK to R4C5C.Q0 SLICE_28 (from CLK_c) ROUTE 37 2.343 R4C5C.Q0 to R4C5A.D1 r_addr_4 CTOOFX_DEL --- 0.721 R4C5A.D1 to R4C5A.OFX0 rom_impl/SLICE_51 ROUTE 1 0.000 R4C5A.OFX0 to R4C5A.FXB rom_impl/mux_53_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R4C5A.FXB to R4C5A.OFX1 rom_impl/SLICE_51 ROUTE 11 1.959 R4C5A.OFX1 to R5C6B.B0 code_data_1 CTOF_DEL --- 0.495 R5C6B.B0 to R5C6B.F0 sram_impl/mem1/SLICE_11 ROUTE 2 1.847 R5C6B.F0 to R5C4B.A0 mem_data_2 C0TOFCO_DE --- 1.023 R5C4B.A0 to R5C4B.FCO SLICE_7 ROUTE 1 0.000 R5C4B.FCO to R5C4C.FCI n1331 FCITOF1_DE --- 0.643 R5C4C.FCI to R5C4C.F1 SLICE_5 ROUTE 1 1.072 R5C4C.F1 to R4C4D.D1 n767 CTOF_DEL --- 0.495 R4C4D.D1 to R4C4D.F1 SLICE_17 ROUTE 1 0.000 R4C4D.F1 to R4C4D.DI1 n132 (to CLK_c) -------- 11.291 (36.0% logic, 64.0% route), 7 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R4C5C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R4C4D.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 5.209ns (weighted slack = 7.813ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in akku_i5 (to CLK_c +) Delay: 11.291ns (36.0% logic, 64.0% route), 7 logic levels. Constraint Details: 11.291ns physical path delay SLICE_28 to SLICE_17 meets 16.666ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 16.500ns) by 5.209ns Physical Path Details: Data path SLICE_28 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5C.CLK to R4C5C.Q0 SLICE_28 (from CLK_c) ROUTE 37 2.343 R4C5C.Q0 to R4C5A.D0 r_addr_4 CTOOFX_DEL --- 0.721 R4C5A.D0 to R4C5A.OFX0 rom_impl/SLICE_51 ROUTE 1 0.000 R4C5A.OFX0 to R4C5A.FXB rom_impl/mux_53_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R4C5A.FXB to R4C5A.OFX1 rom_impl/SLICE_51 ROUTE 11 1.959 R4C5A.OFX1 to R5C6B.B0 code_data_1 CTOF_DEL --- 0.495 R5C6B.B0 to R5C6B.F0 sram_impl/mem1/SLICE_11 ROUTE 2 1.847 R5C6B.F0 to R5C4B.A0 mem_data_2 C0TOFCO_DE --- 1.023 R5C4B.A0 to R5C4B.FCO SLICE_7 ROUTE 1 0.000 R5C4B.FCO to R5C4C.FCI n1331 FCITOF1_DE --- 0.643 R5C4C.FCI to R5C4C.F1 SLICE_5 ROUTE 1 1.072 R5C4C.F1 to R4C4D.D1 n767 CTOF_DEL --- 0.495 R4C4D.D1 to R4C4D.F1 SLICE_17 ROUTE 1 0.000 R4C4D.F1 to R4C4D.DI1 n132 (to CLK_c) -------- 11.291 (36.0% logic, 64.0% route), 7 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R4C5C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 15 3.438 12.PADDI to R4C4D.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "CLK" 60.000000 MHz ; | 60.000 MHz| 56.411 MHz| 4 * | | | MULTICYCLE FROM GROUP "code" TO GROUP | | | "akku" 1.500000 X ; | 16.666 ns| 11.760 ns| 9 | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- n1331 | 1| 10| 55.56% | | | n1330 | 1| 9| 50.00% | | | n1332 | 1| 9| 50.00% | | | mem_data_0 | 2| 6| 33.33% | | | n765 | 1| 5| 27.78% | | | n130 | 1| 5| 27.78% | | | n767 | 1| 4| 22.22% | | | n766 | 1| 4| 22.22% | | | mem_data_2 | 2| 4| 22.22% | | | n131 | 1| 4| 22.22% | | | n132 | 1| 4| 22.22% | | | mem_data_1 | 2| 3| 16.67% | | | mem_data_4 | 2| 3| 16.67% | | | mem_data_5 | 2| 2| 11.11% | | | n133 | 1| 2| 11.11% | | | n768 | 1| 2| 11.11% | | | n135 | 1| 2| 11.11% | | | n770 | 1| 2| 11.11% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 3 clocks: Clock Domain: CLK_c Source: CLK.PAD Loads: 15 Covered under: FREQUENCY PORT "CLK" 60.000000 MHz ; Covered under: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.500000 X ; Data transfers from: Clock Domain: WE_mem Source: SLICE_52.F1 Covered under: FREQUENCY PORT "CLK" 60.000000 MHz ; Transfers: 8 Clock Domain: WE_mem Source: SLICE_52.F1 Loads: 4 No transfer within this clock domain is found Data transfers from: Clock Domain: CLK_c Source: CLK.PAD Covered under: FREQUENCY PORT "CLK" 60.000000 MHz ; Transfers: 14 Clock Domain: O_STB_c Source: SLICE_53.F1 Loads: 9 No transfer within this clock domain is found Data transfers from: Clock Domain: CLK_c Source: CLK.PAD Covered under: FREQUENCY PORT "CLK" 60.000000 MHz ; Transfers: 8 Timing summary (Setup): --------------- Timing errors: 18 Score: 8980 Cumulative negative slack: 8980 Constraints cover 4672 paths, 10 nets, and 516 connections (95.9% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond_1.4_Production (87) Mon Jun 25 10:57:47 2012 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_mcpu2.twr qfn32samples_mcpu2.ncd qfn32samples_mcpu2.prf Design file: qfn32samples_mcpu2.ncd Preference file: qfn32samples_mcpu2.prf Device,speed: LCMXO2-256HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY PORT "CLK" 60.000000 MHz (16 errors)
  • 745 items scored, 16 timing errors detected.
  • MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.500000 X (0 errors)
  • 3927 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "CLK" 60.000000 MHz ; 745 items scored, 16 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 4.064ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i7 (from CLK_c +) Destination: FF Data in r_oport_i7 (to O_STB_c +) Delay: 0.384ns (34.1% logic, 65.9% route), 1 logic levels. Constraint Details: 0.384ns physical path delay SLICE_18 to O_PORT_7_MGIOL exceeds -0.036ns DO_HLD and 0.000ns delay constraint less -4.484ns skew requirement (totaling 4.448ns) by 4.064ns Physical Path Details: Data path SLICE_18 to O_PORT_7_MGIOL: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R5C3D.CLK to R5C3D.Q1 SLICE_18 (from CLK_c) ROUTE 4 0.253 R5C3D.Q1 to IOL_L5D.OPOS akku_7 (to O_STB_c) -------- 0.384 (34.1% logic, 65.9% route), 1 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_18: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R5C3D.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to O_PORT_7_MGIOL: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.151 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 0.592 R4C4A.Q0 to R2C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R2C6D.B0 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.098 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.196 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.267 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.098 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 0.429 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.174 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 0.630 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.174 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.482 R5C6D.F0 to R5C2D.A1 n9 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_53 ROUTE 9 0.752 R5C2D.F1 to IOL_L5D.CLK O_STB_c -------- 6.107 (30.2% logic, 69.8% route), 9 logic levels. Error: The following path exceeds requirements by 4.043ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i5 (from CLK_c +) Destination: FF Data in r_oport_i5 (to O_STB_c +) Delay: 0.405ns (32.3% logic, 67.7% route), 1 logic levels. Constraint Details: 0.405ns physical path delay SLICE_17 to O_PORT_5_MGIOL exceeds -0.036ns DO_HLD and 0.000ns delay constraint less -4.484ns skew requirement (totaling 4.448ns) by 4.043ns Physical Path Details: Data path SLICE_17 to O_PORT_5_MGIOL: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C4D.CLK to R4C4D.Q1 SLICE_17 (from CLK_c) ROUTE 4 0.274 R4C4D.Q1 to IOL_B2C.OPOS akku_5 (to O_STB_c) -------- 0.405 (32.3% logic, 67.7% route), 1 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R4C4D.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to O_PORT_5_MGIOL: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.151 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 0.592 R4C4A.Q0 to R2C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R2C6D.B0 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.098 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.196 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.267 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.098 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 0.429 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.174 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 0.630 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.174 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.482 R5C6D.F0 to R5C2D.A1 n9 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_53 ROUTE 9 0.752 R5C2D.F1 to IOL_B2C.CLK O_STB_c -------- 6.107 (30.2% logic, 69.8% route), 9 logic levels. Error: The following path exceeds requirements by 3.956ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i6 (from CLK_c +) Destination: FF Data in r_oport_i6 (to O_STB_c +) Delay: 0.492ns (26.6% logic, 73.4% route), 1 logic levels. Constraint Details: 0.492ns physical path delay SLICE_18 to O_PORT_6_MGIOL exceeds -0.036ns DO_HLD and 0.000ns delay constraint less -4.484ns skew requirement (totaling 4.448ns) by 3.956ns Physical Path Details: Data path SLICE_18 to O_PORT_6_MGIOL: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R5C3D.CLK to R5C3D.Q0 SLICE_18 (from CLK_c) ROUTE 4 0.361 R5C3D.Q0 to IOL_B2A.OPOS akku_6 (to O_STB_c) -------- 0.492 (26.6% logic, 73.4% route), 1 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_18: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R5C3D.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to O_PORT_6_MGIOL: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.151 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 0.592 R4C4A.Q0 to R2C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R2C6D.B0 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.098 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.196 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.267 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.098 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 0.429 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.174 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 0.630 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.174 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.482 R5C6D.F0 to R5C2D.A1 n9 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_53 ROUTE 9 0.752 R5C2D.F1 to IOL_B2A.CLK O_STB_c -------- 6.107 (30.2% logic, 69.8% route), 9 logic levels. Error: The following path exceeds requirements by 3.858ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i4 (from CLK_c +) Destination: FF Data in r_oport_i4 (to O_STB_c +) Delay: 0.590ns (22.2% logic, 77.8% route), 1 logic levels. Constraint Details: 0.590ns physical path delay SLICE_17 to O_PORT_4_MGIOL exceeds -0.036ns DO_HLD and 0.000ns delay constraint less -4.484ns skew requirement (totaling 4.448ns) by 3.858ns Physical Path Details: Data path SLICE_17 to O_PORT_4_MGIOL: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C4D.CLK to R4C4D.Q0 SLICE_17 (from CLK_c) ROUTE 4 0.459 R4C4D.Q0 to IOL_B2D.OPOS akku_4 (to O_STB_c) -------- 0.590 (22.2% logic, 77.8% route), 1 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R4C4D.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to O_PORT_4_MGIOL: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.151 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 0.592 R4C4A.Q0 to R2C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R2C6D.B0 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.098 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.196 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.267 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.098 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 0.429 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.174 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 0.630 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.174 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.482 R5C6D.F0 to R5C2D.A1 n9 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_53 ROUTE 9 0.752 R5C2D.F1 to IOL_B2D.CLK O_STB_c -------- 6.107 (30.2% logic, 69.8% route), 9 logic levels. Error: The following path exceeds requirements by 3.828ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i0 (from CLK_c +) Destination: FF Data in r_oport_i0 (to O_STB_c +) Delay: 0.620ns (21.1% logic, 78.9% route), 1 logic levels. Constraint Details: 0.620ns physical path delay SLICE_15 to O_PORT_0_MGIOL exceeds -0.036ns DO_HLD and 0.000ns delay constraint less -4.484ns skew requirement (totaling 4.448ns) by 3.828ns Physical Path Details: Data path SLICE_15 to O_PORT_0_MGIOL: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R5C5B.CLK to R5C5B.Q0 SLICE_15 (from CLK_c) ROUTE 4 0.489 R5C5B.Q0 to IOL_R5B.OPOS akku_0 (to O_STB_c) -------- 0.620 (21.1% logic, 78.9% route), 1 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_15: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R5C5B.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to O_PORT_0_MGIOL: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.151 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 0.592 R4C4A.Q0 to R2C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R2C6D.B0 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.098 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.196 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.267 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.098 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 0.429 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.174 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 0.630 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.174 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.482 R5C6D.F0 to R5C2D.A1 n9 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_53 ROUTE 9 0.752 R5C2D.F1 to IOL_R5B.CLK O_STB_c -------- 6.107 (30.2% logic, 69.8% route), 9 logic levels. Error: The following path exceeds requirements by 3.828ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i1 (from CLK_c +) Destination: FF Data in r_oport_i1 (to O_STB_c +) Delay: 0.620ns (21.1% logic, 78.9% route), 1 logic levels. Constraint Details: 0.620ns physical path delay SLICE_15 to O_PORT_1_MGIOL exceeds -0.036ns DO_HLD and 0.000ns delay constraint less -4.484ns skew requirement (totaling 4.448ns) by 3.828ns Physical Path Details: Data path SLICE_15 to O_PORT_1_MGIOL: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R5C5B.CLK to R5C5B.Q1 SLICE_15 (from CLK_c) ROUTE 4 0.489 R5C5B.Q1 to IOL_R5A.OPOS akku_1 (to O_STB_c) -------- 0.620 (21.1% logic, 78.9% route), 1 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_15: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R5C5B.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to O_PORT_1_MGIOL: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.151 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 0.592 R4C4A.Q0 to R2C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R2C6D.B0 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.098 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.196 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.267 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.098 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 0.429 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.174 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 0.630 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.174 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.482 R5C6D.F0 to R5C2D.A1 n9 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_53 ROUTE 9 0.752 R5C2D.F1 to IOL_R5A.CLK O_STB_c -------- 6.107 (30.2% logic, 69.8% route), 9 logic levels. Error: The following path exceeds requirements by 3.651ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i4 (from CLK_c +) Destination: FF Data in sram_impl/mem0/RAM0 (to WE_mem +) FF sram_impl/mem0/RAM0 Delay: 0.340ns (38.5% logic, 61.5% route), 2 logic levels. Constraint Details: 0.340ns physical path delay SLICE_17 to SLICE_13 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.862ns skew requirement (totaling 3.991ns) by 3.651ns Physical Path Details: Data path SLICE_17 to SLICE_13: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C4D.CLK to R4C4D.Q0 SLICE_17 (from CLK_c) ROUTE 4 0.209 R4C4D.Q0 to R4C4C.A1 akku_4 ZERO_DEL --- 0.000 R4C4C.A1 to R4C4C.WDO0 sram_impl/mem0/SLICE_12 ROUTE 1 0.000 R4C4C.WDO0 to R4C4A.WD0 sram_impl/mem0/WD0_INT (to WE_mem) -------- 0.340 (38.5% logic, 61.5% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R4C4D.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.151 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 0.592 R4C4A.Q0 to R2C6D.B1 r_addr_0 CTOOFX_DEL --- 0.267 R2C6D.B1 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.098 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.196 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.267 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.098 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 0.429 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.174 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 0.630 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.174 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.160 R5C6D.F0 to R5C6D.C1 n9 CTOF_DEL --- 0.174 R5C6D.C1 to R5C6D.F1 SLICE_52 ROUTE 4 0.452 R5C6D.F1 to R4C4A.WCK WE_mem -------- 5.485 (33.6% logic, 66.4% route), 9 logic levels. Error: The following path exceeds requirements by 3.635ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i5 (from CLK_c +) Destination: FF Data in sram_impl/mem0/RAM0 (to WE_mem +) FF sram_impl/mem0/RAM0 Delay: 0.356ns (36.8% logic, 63.2% route), 2 logic levels. Constraint Details: 0.356ns physical path delay SLICE_17 to SLICE_13 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.862ns skew requirement (totaling 3.991ns) by 3.635ns Physical Path Details: Data path SLICE_17 to SLICE_13: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C4D.CLK to R4C4D.Q1 SLICE_17 (from CLK_c) ROUTE 4 0.225 R4C4D.Q1 to R4C4C.B1 akku_5 ZERO_DEL --- 0.000 R4C4C.B1 to R4C4C.WDO1 sram_impl/mem0/SLICE_12 ROUTE 1 0.000 R4C4C.WDO1 to R4C4A.WD1 sram_impl/mem0/WD1_INT (to WE_mem) -------- 0.356 (36.8% logic, 63.2% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R4C4D.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.151 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 0.592 R4C4A.Q0 to R2C6D.B1 r_addr_0 CTOOFX_DEL --- 0.267 R2C6D.B1 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.098 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.196 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.267 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.098 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 0.429 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.174 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 0.630 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.174 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.160 R5C6D.F0 to R5C6D.C1 n9 CTOF_DEL --- 0.174 R5C6D.C1 to R5C6D.F1 SLICE_52 ROUTE 4 0.452 R5C6D.F1 to R4C4A.WCK WE_mem -------- 5.485 (33.6% logic, 66.4% route), 9 logic levels. Error: The following path exceeds requirements by 3.617ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i2 (from CLK_c +) Destination: FF Data in r_oport_i2 (to O_STB_c +) Delay: 0.831ns (15.8% logic, 84.2% route), 1 logic levels. Constraint Details: 0.831ns physical path delay SLICE_16 to O_PORT_2_MGIOL exceeds -0.036ns DO_HLD and 0.000ns delay constraint less -4.484ns skew requirement (totaling 4.448ns) by 3.617ns Physical Path Details: Data path SLICE_16 to O_PORT_2_MGIOL: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R5C5D.CLK to R5C5D.Q0 SLICE_16 (from CLK_c) ROUTE 4 0.700 R5C5D.Q0 to IOL_T9D.OPOS akku_2 (to O_STB_c) -------- 0.831 (15.8% logic, 84.2% route), 1 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R5C5D.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to O_PORT_2_MGIOL: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.151 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 0.592 R4C4A.Q0 to R2C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R2C6D.B0 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.098 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.196 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.267 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.098 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 0.429 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.174 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 0.630 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.174 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.482 R5C6D.F0 to R5C2D.A1 n9 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_53 ROUTE 9 0.752 R5C2D.F1 to IOL_T9D.CLK O_STB_c -------- 6.107 (30.2% logic, 69.8% route), 9 logic levels. Error: The following path exceeds requirements by 3.617ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i3 (from CLK_c +) Destination: FF Data in r_oport_i3 (to O_STB_c +) Delay: 0.831ns (15.8% logic, 84.2% route), 1 logic levels. Constraint Details: 0.831ns physical path delay SLICE_16 to O_PORT_3_MGIOL exceeds -0.036ns DO_HLD and 0.000ns delay constraint less -4.484ns skew requirement (totaling 4.448ns) by 3.617ns Physical Path Details: Data path SLICE_16 to O_PORT_3_MGIOL: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R5C5D.CLK to R5C5D.Q1 SLICE_16 (from CLK_c) ROUTE 4 0.700 R5C5D.Q1 to IOL_T9B.OPOS akku_3 (to O_STB_c) -------- 0.831 (15.8% logic, 84.2% route), 1 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R5C5D.CLK CLK_c -------- 1.623 (27.0% logic, 73.0% route), 1 logic levels. Destination Clock Path CLK to O_PORT_3_MGIOL: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c REG_DEL --- 0.151 R4C4A.CLK to R4C4A.Q0 SLICE_13 ROUTE 26 0.592 R4C4A.Q0 to R2C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R2C6D.B0 to R2C6D.OFX0 SLICE_38 ROUTE 1 0.000 R2C6D.OFX0 to R2C6C.FXA n1471 FXTOOFX_DE --- 0.098 R2C6C.FXA to R2C6C.OFX1 SLICE_39 ROUTE 1 0.196 R2C6C.OFX1 to R2C5B.D0 n15_adj_5 CTOOFX_DEL --- 0.267 R2C5B.D0 to R2C5B.OFX0 SLICE_30 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA n1462 FXTOOFX_DE --- 0.098 R2C5A.FXA to R2C5A.OFX1 i847/SLICE_37 ROUTE 2 0.429 R2C5A.OFX1 to R4C5C.B0 code_data_5 CTOF_DEL --- 0.174 R4C5C.B0 to R4C5C.F0 SLICE_28 ROUTE 2 0.630 R4C5C.F0 to R5C6D.B0 n1052 CTOF_DEL --- 0.174 R5C6D.B0 to R5C6D.F0 SLICE_52 ROUTE 2 0.482 R5C6D.F0 to R5C2D.A1 n9 CTOF_DEL --- 0.174 R5C2D.A1 to R5C2D.F1 SLICE_53 ROUTE 9 0.752 R5C2D.F1 to IOL_T9B.CLK O_STB_c -------- 6.107 (30.2% logic, 69.8% route), 9 logic levels. ================================================================================ Preference: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.500000 X ; 3927 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 9.287ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in akku_i4 (to CLK_c +) Delay: 0.941ns (44.8% logic, 55.2% route), 4 logic levels. Constraint Details: 0.941ns physical path delay SLICE_13 to SLICE_17 meets -0.013ns DIN_HLD and -8.333ns delay constraint less 0.000ns skew requirement (totaling -8.346ns) by 9.287ns Physical Path Details: Data path SLICE_13 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C4A.CLK to R4C4A.Q0 SLICE_13 (from CLK_c) ROUTE 26 0.159 R4C4A.Q0 to R4C5A.M1 r_addr_0 MTOOFX_DEL --- 0.093 R4C5A.M1 to R4C5A.OFX1 rom_impl/SLICE_51 ROUTE 11 0.228 R4C5A.OFX1 to R4C4A.B0 code_data_1 CTOF_DEL --- 0.099 R4C4A.B0 to R4C4A.F0 SLICE_13 ROUTE 2 0.132 R4C4A.F0 to R4C4D.D0 mem_data_4 CTOF_DEL --- 0.099 R4C4D.D0 to R4C4D.F0 SLICE_17 ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 n133 (to CLK_c) -------- 0.941 (44.8% logic, 55.2% route), 4 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4D.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 9.290ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in akku_i5 (to CLK_c +) Delay: 0.944ns (44.7% logic, 55.3% route), 4 logic levels. Constraint Details: 0.944ns physical path delay SLICE_13 to SLICE_17 meets -0.013ns DIN_HLD and -8.333ns delay constraint less 0.000ns skew requirement (totaling -8.346ns) by 9.290ns Physical Path Details: Data path SLICE_13 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C4A.CLK to R4C4A.Q0 SLICE_13 (from CLK_c) ROUTE 26 0.159 R4C4A.Q0 to R4C5A.M1 r_addr_0 MTOOFX_DEL --- 0.093 R4C5A.M1 to R4C5A.OFX1 rom_impl/SLICE_51 ROUTE 11 0.228 R4C5A.OFX1 to R4C4A.B1 code_data_1 CTOF_DEL --- 0.099 R4C4A.B1 to R4C4A.F1 SLICE_13 ROUTE 2 0.135 R4C4A.F1 to R4C4D.C1 mem_data_5 CTOF_DEL --- 0.099 R4C4D.C1 to R4C4D.F1 SLICE_17 ROUTE 1 0.000 R4C4D.F1 to R4C4D.DI1 n132 (to CLK_c) -------- 0.944 (44.7% logic, 55.3% route), 4 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4D.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 9.324ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in akku_i4 (to CLK_c +) Delay: 0.978ns (43.1% logic, 56.9% route), 4 logic levels. Constraint Details: 0.978ns physical path delay SLICE_13 to SLICE_17 meets -0.013ns DIN_HLD and -8.333ns delay constraint less 0.000ns skew requirement (totaling -8.346ns) by 9.324ns Physical Path Details: Data path SLICE_13 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C4A.CLK to R4C4A.Q0 SLICE_13 (from CLK_c) ROUTE 26 0.273 R4C4A.Q0 to R4C6A.M1 r_addr_0 MTOOFX_DEL --- 0.093 R4C6A.M1 to R4C6A.OFX1 SLICE_41 ROUTE 11 0.151 R4C6A.OFX1 to R4C4A.C0 code_data_2 CTOF_DEL --- 0.099 R4C4A.C0 to R4C4A.F0 SLICE_13 ROUTE 2 0.132 R4C4A.F0 to R4C4D.D0 mem_data_4 CTOF_DEL --- 0.099 R4C4D.D0 to R4C4D.F0 SLICE_17 ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 n133 (to CLK_c) -------- 0.978 (43.1% logic, 56.9% route), 4 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4D.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 9.327ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in akku_i0 (to CLK_c +) Delay: 0.981ns (43.0% logic, 57.0% route), 4 logic levels. Constraint Details: 0.981ns physical path delay SLICE_13 to SLICE_15 meets -0.013ns DIN_HLD and -8.333ns delay constraint less 0.000ns skew requirement (totaling -8.346ns) by 9.327ns Physical Path Details: Data path SLICE_13 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C4A.CLK to R4C4A.Q0 SLICE_13 (from CLK_c) ROUTE 26 0.273 R4C4A.Q0 to R4C6A.M1 r_addr_0 MTOOFX_DEL --- 0.093 R4C6A.M1 to R4C6A.OFX1 SLICE_41 ROUTE 11 0.149 R4C6A.OFX1 to R5C6A.C0 code_data_2 CTOF_DEL --- 0.099 R5C6A.C0 to R5C6A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 0.137 R5C6A.F0 to R5C5B.C0 mem_data_0 CTOF_DEL --- 0.099 R5C5B.C0 to R5C5B.F0 SLICE_15 ROUTE 1 0.000 R5C5B.F0 to R5C5B.DI0 n137 (to CLK_c) -------- 0.981 (43.0% logic, 57.0% route), 4 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R5C5B.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 9.327ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in akku_i5 (to CLK_c +) Delay: 0.981ns (43.0% logic, 57.0% route), 4 logic levels. Constraint Details: 0.981ns physical path delay SLICE_13 to SLICE_17 meets -0.013ns DIN_HLD and -8.333ns delay constraint less 0.000ns skew requirement (totaling -8.346ns) by 9.327ns Physical Path Details: Data path SLICE_13 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C4A.CLK to R4C4A.Q0 SLICE_13 (from CLK_c) ROUTE 26 0.273 R4C4A.Q0 to R4C6A.M1 r_addr_0 MTOOFX_DEL --- 0.093 R4C6A.M1 to R4C6A.OFX1 SLICE_41 ROUTE 11 0.151 R4C6A.OFX1 to R4C4A.C1 code_data_2 CTOF_DEL --- 0.099 R4C4A.C1 to R4C4A.F1 SLICE_13 ROUTE 2 0.135 R4C4A.F1 to R4C4D.C1 mem_data_5 CTOF_DEL --- 0.099 R4C4D.C1 to R4C4D.F1 SLICE_17 ROUTE 1 0.000 R4C4D.F1 to R4C4D.DI1 n132 (to CLK_c) -------- 0.981 (43.0% logic, 57.0% route), 4 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4D.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 9.340ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in akku_i4 (to CLK_c +) Delay: 0.994ns (55.2% logic, 44.8% route), 5 logic levels. Constraint Details: 0.994ns physical path delay SLICE_13 to SLICE_17 meets -0.013ns DIN_HLD and -8.333ns delay constraint less 0.000ns skew requirement (totaling -8.346ns) by 9.340ns Physical Path Details: Data path SLICE_13 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C4A.CLK to R4C4A.Q1 SLICE_13 (from CLK_c) ROUTE 44 0.162 R4C4A.Q1 to R4C6B.C0 r_addr_1 CTOOFX_DEL --- 0.153 R4C6B.C0 to R4C6B.OFX0 SLICE_40 ROUTE 1 0.000 R4C6B.OFX0 to R4C6A.FXA mux_53_Mux_2_0_f5a FXTOOFX_DE --- 0.067 R4C6A.FXA to R4C6A.OFX1 SLICE_41 ROUTE 11 0.151 R4C6A.OFX1 to R4C4A.C0 code_data_2 CTOF_DEL --- 0.099 R4C4A.C0 to R4C4A.F0 SLICE_13 ROUTE 2 0.132 R4C4A.F0 to R4C4D.D0 mem_data_4 CTOF_DEL --- 0.099 R4C4D.D0 to R4C4D.F0 SLICE_17 ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 n133 (to CLK_c) -------- 0.994 (55.2% logic, 44.8% route), 5 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4D.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 9.340ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in akku_i4 (to CLK_c +) Delay: 0.994ns (55.2% logic, 44.8% route), 5 logic levels. Constraint Details: 0.994ns physical path delay SLICE_13 to SLICE_17 meets -0.013ns DIN_HLD and -8.333ns delay constraint less 0.000ns skew requirement (totaling -8.346ns) by 9.340ns Physical Path Details: Data path SLICE_13 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C4A.CLK to R4C4A.Q1 SLICE_13 (from CLK_c) ROUTE 44 0.162 R4C4A.Q1 to R4C6B.C1 r_addr_1 CTOOFX_DEL --- 0.153 R4C6B.C1 to R4C6B.OFX0 SLICE_40 ROUTE 1 0.000 R4C6B.OFX0 to R4C6A.FXA mux_53_Mux_2_0_f5a FXTOOFX_DE --- 0.067 R4C6A.FXA to R4C6A.OFX1 SLICE_41 ROUTE 11 0.151 R4C6A.OFX1 to R4C4A.C0 code_data_2 CTOF_DEL --- 0.099 R4C4A.C0 to R4C4A.F0 SLICE_13 ROUTE 2 0.132 R4C4A.F0 to R4C4D.D0 mem_data_4 CTOF_DEL --- 0.099 R4C4D.D0 to R4C4D.F0 SLICE_17 ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 n133 (to CLK_c) -------- 0.994 (55.2% logic, 44.8% route), 5 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4D.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 9.340ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in akku_i4 (to CLK_c +) Delay: 0.994ns (55.2% logic, 44.8% route), 5 logic levels. Constraint Details: 0.994ns physical path delay SLICE_13 to SLICE_17 meets -0.013ns DIN_HLD and -8.333ns delay constraint less 0.000ns skew requirement (totaling -8.346ns) by 9.340ns Physical Path Details: Data path SLICE_13 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C4A.CLK to R4C4A.Q1 SLICE_13 (from CLK_c) ROUTE 44 0.162 R4C4A.Q1 to R4C6A.C0 r_addr_1 CTOOFX_DEL --- 0.153 R4C6A.C0 to R4C6A.OFX0 SLICE_41 ROUTE 1 0.000 R4C6A.OFX0 to R4C6A.FXB mux_53_Mux_2_1_f5b FXTOOFX_DE --- 0.067 R4C6A.FXB to R4C6A.OFX1 SLICE_41 ROUTE 11 0.151 R4C6A.OFX1 to R4C4A.C0 code_data_2 CTOF_DEL --- 0.099 R4C4A.C0 to R4C4A.F0 SLICE_13 ROUTE 2 0.132 R4C4A.F0 to R4C4D.D0 mem_data_4 CTOF_DEL --- 0.099 R4C4D.D0 to R4C4D.F0 SLICE_17 ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 n133 (to CLK_c) -------- 0.994 (55.2% logic, 44.8% route), 5 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4D.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 9.340ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in akku_i4 (to CLK_c +) Delay: 0.994ns (55.2% logic, 44.8% route), 5 logic levels. Constraint Details: 0.994ns physical path delay SLICE_13 to SLICE_17 meets -0.013ns DIN_HLD and -8.333ns delay constraint less 0.000ns skew requirement (totaling -8.346ns) by 9.340ns Physical Path Details: Data path SLICE_13 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C4A.CLK to R4C4A.Q1 SLICE_13 (from CLK_c) ROUTE 44 0.162 R4C4A.Q1 to R4C6A.C1 r_addr_1 CTOOFX_DEL --- 0.153 R4C6A.C1 to R4C6A.OFX0 SLICE_41 ROUTE 1 0.000 R4C6A.OFX0 to R4C6A.FXB mux_53_Mux_2_1_f5b FXTOOFX_DE --- 0.067 R4C6A.FXB to R4C6A.OFX1 SLICE_41 ROUTE 11 0.151 R4C6A.OFX1 to R4C4A.C0 code_data_2 CTOF_DEL --- 0.099 R4C4A.C0 to R4C4A.F0 SLICE_13 ROUTE 2 0.132 R4C4A.F0 to R4C4D.D0 mem_data_4 CTOF_DEL --- 0.099 R4C4D.D0 to R4C4D.F0 SLICE_17 ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 n133 (to CLK_c) -------- 0.994 (55.2% logic, 44.8% route), 5 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4D.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 9.343ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in akku_i0 (to CLK_c +) Delay: 0.997ns (55.1% logic, 44.9% route), 5 logic levels. Constraint Details: 0.997ns physical path delay SLICE_13 to SLICE_15 meets -0.013ns DIN_HLD and -8.333ns delay constraint less 0.000ns skew requirement (totaling -8.346ns) by 9.343ns Physical Path Details: Data path SLICE_13 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C4A.CLK to R4C4A.Q1 SLICE_13 (from CLK_c) ROUTE 44 0.162 R4C4A.Q1 to R4C6A.C1 r_addr_1 CTOOFX_DEL --- 0.153 R4C6A.C1 to R4C6A.OFX0 SLICE_41 ROUTE 1 0.000 R4C6A.OFX0 to R4C6A.FXB mux_53_Mux_2_1_f5b FXTOOFX_DE --- 0.067 R4C6A.FXB to R4C6A.OFX1 SLICE_41 ROUTE 11 0.149 R4C6A.OFX1 to R5C6A.C0 code_data_2 CTOF_DEL --- 0.099 R5C6A.C0 to R5C6A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 0.137 R5C6A.F0 to R5C5B.C0 mem_data_0 CTOF_DEL --- 0.099 R5C5B.C0 to R5C5B.F0 SLICE_15 ROUTE 1 0.000 R5C5B.F0 to R5C5B.DI0 n137 (to CLK_c) -------- 0.997 (55.1% logic, 44.9% route), 5 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R4C4A.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 15 1.184 12.PADDI to R5C5B.CLK CLK_c -------- 1.184 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "CLK" 60.000000 MHz ; | -| -| 1 * | | | MULTICYCLE FROM GROUP "code" TO GROUP | | | "akku" 1.500000 X ; | -| -| 4 | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- akku_3 | 4| 2| 12.50% | | | akku_4 | 4| 2| 12.50% | | | akku_0 | 4| 2| 12.50% | | | akku_7 | 4| 2| 12.50% | | | akku_1 | 4| 2| 12.50% | | | akku_2 | 4| 2| 12.50% | | | akku_6 | 4| 2| 12.50% | | | akku_5 | 4| 2| 12.50% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 3 clocks: Clock Domain: CLK_c Source: CLK.PAD Loads: 15 Covered under: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.500000 X ; Covered under: FREQUENCY PORT "CLK" 60.000000 MHz ; Data transfers from: Clock Domain: WE_mem Source: SLICE_52.F1 Covered under: FREQUENCY PORT "CLK" 60.000000 MHz ; Transfers: 8 Clock Domain: WE_mem Source: SLICE_52.F1 Loads: 4 No transfer within this clock domain is found Data transfers from: Clock Domain: CLK_c Source: CLK.PAD Covered under: FREQUENCY PORT "CLK" 60.000000 MHz ; Transfers: 14 Clock Domain: O_STB_c Source: SLICE_53.F1 Loads: 9 No transfer within this clock domain is found Data transfers from: Clock Domain: CLK_c Source: CLK.PAD Covered under: FREQUENCY PORT "CLK" 60.000000 MHz ; Transfers: 8 Timing summary (Hold): --------------- Timing errors: 16 Score: 58752 Cumulative negative slack: 58752 Constraints cover 4672 paths, 10 nets, and 516 connections (95.9% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 18 (setup), 16 (hold) Score: 8980 (setup), 58752 (hold) Cumulative negative slack: 67732 (8980+58752) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------