PAR: Place And Route Diamond_1.4_Production (87).
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.
Fri Jun 22 16:24:50 2012

Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_dac.p2t
qfn32samples_dac_map.ncd qfn32samples_dac.dir qfn32samples_dac.prf

Preference file: qfn32samples_dac.prf.

Cost Table Summary
Level/      Number      Timing      Run         NCD
Cost [ncd]  Unrouted    Score       Time        Status
----------  --------    --------    -----       ------------
5_1   *     0           1509737     01:33       Complete        


* : Design saved.

par done!

Lattice Place and Route Report for Design "qfn32samples_dac_map.ncd"
Fri Jun 22 16:24:50 2012


Best Par Run
PAR: Place And Route Diamond_1.4_Production (87).
Command Line: Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_dac.p2t
qfn32samples_dac_map.ncd qfn32samples_dac.dir qfn32samples_dac.prf
Preference file: qfn32samples_dac.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file qfn32samples_dac_map.ncd.
Design name: dac3
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-256HC
Package:     TQFP100
Performance: 4
Loading device for application par from file 'xo2c256.nph' in environment: Y:/Program_Files/lscc/diamond/1.4/ispfpga.
Package Status:                     Final          Version 1.34
Performance Hardware Data Status:   Final)         Version 22.4
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)      22/56           39% used
                     22/56           39% bonded
   IOLOGIC            3/56            5% used

   SLICE             25/128          19% used



Number of Signals: 105
Number of Connections: 214
WARNING - par: Placement timing preferences are hard to meet.  However, placement will continue.  Use static timing analysis to identify errors.  For more information, see online help subjects "Place & Route TRACE Report"  or the "TRACE" application.

Pin Constraint Summary:
   0 out of 22 pins locked (0% locked).

The following 1 signal is selected to use the primary clock routing resources:
    CLK_c (driver: CLK, clk load #: 24)


The following 1 signal is selected to use the secondary clock routing resources:
    n39 (driver: SLICE_30, clk load #: 0, sr load #: 8, ce load #: 11)

No signal is selected as Global Set/Reset.
.
Starting Placer Phase 0.
.........
Finished Placer Phase 0.  REAL time: 24 secs 

Starting Placer Phase 1.
....................
Placer score = 121504.
Finished Placer Phase 1.  REAL time: 1 mins 11 secs 

Starting Placer Phase 2.
.
Placer score =  114944
Finished Placer Phase 2.  REAL time: 1 mins 11 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 1 out of 8 (12%)
  DCM        : 0 out of 2 (0%)
  DCC        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "CLK_c" from comp "CLK" on CLK_PIN site "38 (PB4C)", clk load = 24
  SECONDARY "n39" from F0 on comp "SLICE_30" on site "R5C3D", clk load = 0, ce load = 11, sr load = 8

  PRIMARY  : 1 out of 8 (12%)
  SECONDARY: 1 out of 8 (12%)




I/O Usage Summary (final):
   22 out of 56 (39.3%) PIO sites used.
   22 out of 56 (39.3%) bonded PIO sites used.
   Number of PIO comps: 22; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0        | 2 / 14 ( 14%)  | 2.5V       | -         |
| 1        | 0 / 14 (  0%)  | -          | -         |
| 2        | 10 / 14 ( 71%) | 2.5V       | -         |
| 3        | 10 / 14 ( 71%) | 2.5V       | -         |
+----------+----------------+------------+-----------+

Total placer CPU time: 36 secs 

Dumping design to file qfn32samples_dac.dir/5_1.ncd.

0 connections routed; 214 unrouted.
Starting router resource preassignment

Completed router resource preassignment. Real time: 1 mins 16 secs 
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
214 successful; 0 unrouted; (1941329) real time: 1 mins 17 secs 
Dumping design to file qfn32samples_dac.dir/5_1.ncd.
End of iteration 2
214 successful; 0 unrouted; (1683245) real time: 1 mins 17 secs 
Dumping design to file qfn32samples_dac.dir/5_1.ncd.
End of iteration 3
214 successful; 0 unrouted; (1575337) real time: 1 mins 21 secs 
Dumping design to file qfn32samples_dac.dir/5_1.ncd.
End of iteration 4
214 successful; 0 unrouted; (1509737) real time: 1 mins 26 secs 
Dumping design to file qfn32samples_dac.dir/5_1.ncd.
End of iteration 5
214 successful; 0 unrouted; (1509737) real time: 1 mins 29 secs 
End of iteration 6
214 successful; 0 unrouted; (1509737) real time: 1 mins 29 secs 
Total CPU time 45 secs 
Total REAL time: 1 mins 29 secs 
Completely routed.
End of route.  214 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.

Timing score: 1509737 

Total REAL time to completion: 1 mins 33 secs 

Dumping design to file qfn32samples_dac.dir/5_1.ncd.


All signals are completely routed.


par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.