Lattice Mapping Report File for Design Module 'mcpu'


Design Information

Command line:   map -a MachXO2 -p LCMXO2-256HC -t QFN32 -s 4 -oc Commercial
     qfn32samples_mcpu3.ngd -o qfn32samples_mcpu3_map.ncd -pr
     qfn32samples_mcpu3.prf -mp qfn32samples_mcpu3.mrp
     Z:/XC2C/xo2qfn-w08/src/mcpu3_g.lpf -c 0
Target Vendor:  LATTICE
Target Device:  LCMXO2-256HCQFN32
Target Performance:   4
Mapper:  xo2c00,  version:  Diamond_1.4_Production (87)
Mapped on:  06/26/12  09:46:06


Design Summary
   Number of registers:    28
      PFU registers:    20
      PIO registers:    8
   Number of SLICEs:           101 out of   128 (79%)
      SLICEs(logic/ROM):        32 out of    32 (100%)
      SLICEs(logic/ROM/RAM):    69 out of    96 (72%)
          As RAM:            6 out of    96 (6%)
          As Logic/ROM:     63 out of    96 (66%)
   Number of logic LUT4s:     182
   Number of distributed RAM:   6 (12 LUT4s)
   Number of ripple logic:      4 (8 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:     202
   Number of PIO sites used: 11 out of 22 (50%)
   Number of block RAMs:  0 out of 0
   Number of GSRs:  0 out of 1 (0%)
   EFB used :       No
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   POR :            On
   Bandgap :        On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  2
     Net O_STB_c: 8 loads, 8 rising, 0 falling (Driver: i3_4_lut )
     Net CLK_c: 13 loads, 13 rising, 0 falling (Driver: PIO CLK )
   Number of Clock Enables:  4
     Net n3002: 1 loads, 1 LSLICEs
     Net n3651: 1 loads, 1 LSLICEs
     Net n1191: 4 loads, 4 LSLICEs
     Net alu_impl_I/alu_impl/alu_hi/n3698: 1 loads, 1 LSLICEs
   Number of LSRs:  2
     Net RST_c: 11 loads, 11 LSLICEs

     Net n1258: 2 loads, 2 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net pc_2: 68 loads
     Net pc_3: 68 loads
     Net pc_1: 67 loads
     Net pc_4: 61 loads
     Net pc_5: 31 loads
     Net pc_0: 29 loads
     Net int_c_adj_27: 20 loads
     Net code_data_8: 19 loads
     Net inst_1: 19 loads
     Net inst_2: 19 loads




   Number of warnings:  5
   Number of errors:    0




Design Errors/Warnings

WARNING: input pad net 'SCL' has no legal load
WARNING: input pad net 'SDA' has no legal load
WARNING: logical net 'add_35_1/CI' has no driver
WARNING: IO buffer missing for top level port SCL...logic will be discarded.
WARNING: IO buffer missing for top level port SDA...logic will be discarded.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| RST                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| CLK                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| O_STB               | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| O_PORT_0            | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+
| O_PORT_1            | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+
| O_PORT_2            | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+
| O_PORT_3            | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+
| O_PORT_4            | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+
| O_PORT_5            | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+
| O_PORT_6            | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+

| O_PORT_7            | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+



Removed logic

Block GSR_INST undriven or does not drive anything - clipped.
Signal GND_net undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.
Signal add_35_1/S0 undriven or does not drive anything - clipped.
Signal add_35_1/CI undriven or does not drive anything - clipped.
Signal add_35_7/CO undriven or does not drive anything - clipped.
Block i1 was optimized away.
Block i2 was optimized away.



Memory Usage

/sram_impl/mem0:
    EBRs: 0
    RAM SLICEs: 3
    Logic SLICEs: 0
    PFU Registers: 0
/sram_impl/mem1:
    EBRs: 0
    RAM SLICEs: 3
    Logic SLICEs: 0
    PFU Registers: 0



Run Time and Memory Usage
-------------------------

   Total CPU Time: 2 secs
   Total REAL Time: 27 secs
   Peak Memory Usage: 25 MB























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