Lattice Mapping Report File for Design Module 'mcpu'


Design Information

Command line:   map -a MachXO2 -p LCMXO2-256HC -t QFN32 -s 4 -oc Commercial
     qfn32samples_mcpu_efb.ngd -o qfn32samples_mcpu_efb_map.ncd -pr
     qfn32samples_mcpu_efb.prf -mp qfn32samples_mcpu_efb.mrp
     Z:/XC2C/xo2qfn-w08/src/mcpu2_efb.lpf -c 0
Target Vendor:  LATTICE
Target Device:  LCMXO2-256HCQFN32
Target Performance:   4
Mapper:  xo2c00,  version:  Diamond_1.4_Production (87)
Mapped on:  06/26/12  09:43:31


Design Summary
   Number of registers:    39
      PFU registers:    31
      PIO registers:    8
   Number of SLICEs:            64 out of   128 (50%)
      SLICEs(logic/ROM):        32 out of    32 (100%)
      SLICEs(logic/ROM/RAM):    32 out of    96 (33%)
          As RAM:            6 out of    96 (6%)
          As Logic/ROM:     26 out of    96 (27%)
   Number of logic LUT4s:      97
   Number of distributed RAM:   6 (12 LUT4s)
   Number of ripple logic:      9 (18 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:     127
   Number of PIO sites used: 13 out of 22 (59%)
   Number of block RAMs:  0 out of 0
   Number of GSRs:  1 out of 1 (100%)
   EFB used :       Yes
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   POR :            On
   Bandgap :        On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  4
     Net CLK_2X_c: 8 loads, 8 rising, 0 falling (Driver: PIO CLK_2X )
     Net master_clk: 13 loads, 13 rising, 0 falling (Driver: master_clk_71 )
     Net i2c1_scli: 1 loads, 1 rising, 0 falling (Driver: PIO SCL )
     Net O_STB_c: 8 loads, 8 rising, 0 falling (Driver: i3_4_lut_adj_2 )
   Number of Clock Enables:  3
     Net n1009: 4 loads, 4 LSLICEs
     Net n995: 1 loads, 1 LSLICEs
     Net n810: 4 loads, 4 LSLICEs
   Number of local set/reset loads for net RST_NEG merged into GSR:  1

   Number of LSRs:  5
     Net n1016: 2 loads, 2 LSLICEs
     Net wb_stat_1: 1 loads, 1 LSLICEs
     Net RST_c: 9 loads, 8 LSLICEs
     Net n1601: 1 loads, 1 LSLICEs
     Net n1239: 2 loads, 2 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net pc_2: 46 loads
     Net pc_3: 46 loads
     Net pc_1: 45 loads
     Net pc_4: 38 loads
     Net pc_0: 26 loads
     Net pc_5: 19 loads
     Net n1241: 16 loads
     Net RST_c: 16 loads
     Net code_data_3: 13 loads
     Net code_data_0: 12 loads




   Number of warnings:  3
   Number of errors:    0




Design Errors/Warnings

WARNING: logical net 'add_51_1/CI' has no driver
WARNING: logical net 'add_196_1/CI' has no driver
WARNING: Using local reset signal 'RST_NEG' to infer global GSR net.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| SDA                 | BIDIR     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| SCL                 | BIDIR     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| RST                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| CLK_2X              | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| O_STB               | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| O_PORT_0            | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+
| O_PORT_1            | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+
| O_PORT_2            | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+
| O_PORT_3            | OUTPUT    | LVCMOS25  | OUT        |

+---------------------+-----------+-----------+------------+
| O_PORT_4            | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+
| O_PORT_5            | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+
| O_PORT_6            | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+
| O_PORT_7            | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+



Removed logic

Block m0_lut undriven or does not drive anything - clipped.
Signal n1721 undriven or does not drive anything - clipped.
Signal GND_net undriven or does not drive anything - clipped.
Signal add_196_1/S0 undriven or does not drive anything - clipped.
Signal add_196_1/CI undriven or does not drive anything - clipped.
Signal add_51_1/S0 undriven or does not drive anything - clipped.
Signal add_51_1/CI undriven or does not drive anything - clipped.
Signal add_196_9/CO undriven or does not drive anything - clipped.
Signal add_51_7/CO undriven or does not drive anything - clipped.
Block i1 was optimized away.



Memory Usage

/sram_impl/mem0:
    EBRs: 0
    RAM SLICEs: 3
    Logic SLICEs: 0
    PFU Registers: 0
/sram_impl/mem1:
    EBRs: 0
    RAM SLICEs: 3
    Logic SLICEs: 0
    PFU Registers: 0

Embedded Functional Block Connection Summary:
---------------------------------------------

   Desired WISHBONE clock frequency: 50.0 MHz
   Clock source:                     CLK_2X_c
   Reset source:                     RST_c
   Functions mode:
      I2C #1 (Primary) Function:     ENABLED
      I2C #2 (Secondary) Function:   DISABLED
      SPI Function:                  DISABLED
      Timer/Counter Function:        ENABLED
      Timer/Counter Mode:            WB
      UFM Connection:                DISABLED
      PLL0 Connection:               DISABLED
      PLL1 Connection:               DISABLED
   I2C Function Summary:
   --------------------

      I2C Component:          PRIMARY
      I2C Addressing:         7BIT
      I2C Performance:        400kHz
      Slave Address:          0b1010001
      General Call:           DISABLED
      I2C Wake Up:            DISABLED
      I2C Component:          UFM/Configuration
      I2C Addressing:         7BIT
      I2C Performance:        400kHz
      Slave Address:          0b1010000
   SPI Function Summary:
   --------------------
      None
   Timer/Counter Function Summary:
   ------------------------------
      TC_MODE:                CTCM
      TC_SCLK_SEL:            Positive Edge
      TC_CCLK_SEL:            1
      GSR:                    ENABLED
      TC_TOP_SET:             65535
      TC_OCR_SET:             32767
      TC_OC_MODE:             TOGGLE
      TC_RESETN:              DISABLED
      TC_TOP_SEL:             ON
      TC_OV_INT:              OFF
      TC_OCR_INT:             OFF
      TC_ICR_INT:             OFF
      TC_OVERFLOW:            DISABLED
      TC_ICAPTURE:            DISABLED
   UFM Function Summary:
   --------------------
      UFM Utilization:        General Purpose Flash Memory
      Available General
      Purpose Flash Memory:   0 Pages (0*128 Bits)

      EBR Blocks with Unique
      Initialization Data:    0

      WID		EBR Instance
      ---		------------



ASIC Components
---------------

Instance Name: efb_impl/EFBInst_0
         Type: EFB



GSR Usage
---------

GSR Component:
   The local reset signal 'RST_NEG' of the design has been inferred as Global
        Set Reset (GSR). The reset signal used for GSR control is 'RST_NEG'.

GSR Property:
   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.




Run Time and Memory Usage
-------------------------

   Total CPU Time: 1 secs
   Total REAL Time: 16 secs
   Peak Memory Usage: 25 MB






















































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