Map TRACE Report
Loading design for application trce from file qfn32samples_udrv_map.ncd.
Design name: udrv
NCD version: 3.2
Vendor: LATTICE
Device: LCMXO2-256HC
Package: QFN32
Performance: 4
Loading device for application trce from file 'xo2c256.nph' in environment: C:/lscc/diamond/1.4/ispfpga.
Package Status: Advanced Version 1.34
Performance Hardware Data Status: Final) Version 22.4
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond_1.4_Production (87)
Sat Jun 30 14:40:12 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o qfn32samples_udrv.tw1 qfn32samples_udrv_map.ncd qfn32samples_udrv.prf
Design file: qfn32samples_udrv_map.ncd
Preference file: qfn32samples_udrv.prf
Device,speed: LCMXO2-256HC,4
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY PORT "CLK_4X" 100.000000 MHz (242 errors)
2159 items scored, 242 timing errors detected.
Warning: 62.846MHz is the maximum frequency for this preference.
MULTICYCLE TO PORT "DP" 20.000000 X (2 errors)
2 items scored, 2 timing errors detected.
MULTICYCLE TO PORT "DM" 20.000000 X (2 errors)
2 items scored, 2 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "CLK_4X" 100.000000 MHz ;
2159 items scored, 242 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 2.956ns (weighted slack = -5.912ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q reciever_impl/data_rdy_100 (from CLK +)
Destination: FF Data in fifo_impl/mem0/RAM0 (to CLK -)
FF fifo_impl/mem0/RAM0
Delay: 7.848ns (31.0% logic, 69.0% route), 5 logic levels.
Constraint Details:
7.848ns physical path delay SLICE_22 to SLICE_1 exceeds
5.000ns delay constraint less
0.108ns WRE_SET requirement (totaling 4.892ns) by 2.956ns
Physical Path Details:
Data path SLICE_22 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_22.CLK to SLICE_22.Q0 SLICE_22 (from CLK)
ROUTE 1 e 1.234 SLICE_22.Q0 to SLICE_23.C1 R_DATA_RDY
CTOF_DEL --- 0.495 SLICE_23.C1 to SLICE_23.F1 SLICE_23
ROUTE 1 e 0.480 SLICE_23.F1 to SLICE_23.A0 n200
CTOF_DEL --- 0.495 SLICE_23.A0 to SLICE_23.F0 SLICE_23
ROUTE 5 e 1.234 SLICE_23.F0 to */SLICE_119.A1 fifo_impl/n21
CTOF_DEL --- 0.495 */SLICE_119.A1 to */SLICE_119.F1 fifo_impl/SLICE_119
ROUTE 6 e 1.234 */SLICE_119.F1 to SLICE_125.C0 fifo_impl/n262
CTOF_DEL --- 0.495 SLICE_125.C0 to SLICE_125.F0 SLICE_125
ROUTE 4 e 1.234 SLICE_125.F0 to SLICE_1.WRE fifo_impl/n493 (to CLK)
--------
7.848 (31.0% logic, 69.0% route), 5 logic levels.
Warning: 62.846MHz is the maximum frequency for this preference.
================================================================================
Preference: MULTICYCLE TO PORT "DP" 20.000000 X ;
2 items scored, 2 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 6.390ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sender_impl/r_oe_150 (from CLK +)
Destination: Port Pad DP
Delay: 6.390ns (80.7% logic, 19.3% route), 2 logic levels.
Constraint Details:
6.390ns physical path delay DP_MGIOL to DP exceeds
0.000ns delay constraint by 6.390ns
Physical Path Details:
Data path DP_MGIOL to DP:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 0.500 DP_MGIOL.CLK to DP_MGIOL.IOLTO DP_MGIOL (from CLK)
ROUTE 1 e 1.234 DP_MGIOL.IOLTO to 27.IOLTO n715
TOTS_DEL --- 4.656 27.IOLTO to 27.PAD DP
--------
6.390 (80.7% logic, 19.3% route), 2 logic levels.
================================================================================
Preference: MULTICYCLE TO PORT "DM" 20.000000 X ;
2 items scored, 2 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 6.390ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sender_impl/r_oe_150$r0 (from CLK +)
Destination: Port Pad DM
Delay: 6.390ns (80.7% logic, 19.3% route), 2 logic levels.
Constraint Details:
6.390ns physical path delay DM_MGIOL to DM exceeds
0.000ns delay constraint by 6.390ns
Physical Path Details:
Data path DM_MGIOL to DM:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 0.500 DM_MGIOL.CLK to DM_MGIOL.IOLTO DM_MGIOL (from CLK)
ROUTE 1 e 1.234 DM_MGIOL.IOLTO to 28.IOLTO n715$n0
TOTS_DEL --- 4.656 28.IOLTO to 28.PAD DM
--------
6.390 (80.7% logic, 19.3% route), 2 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "CLK_4X" 100.000000 MHz | | |
; | 100.000 MHz| 62.846 MHz| 5 *
| | |
MULTICYCLE TO PORT "DP" 20.000000 X ; | 0.000 ns| 6.390 ns| 2 *
| | |
MULTICYCLE TO PORT "DM" 20.000000 X ; | 0.000 ns| 6.390 ns| 2 *
| | |
----------------------------------------------------------------------------
3 preferences(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
sender_impl/n349 | 5| 70| 28.46%
| | |
sender_impl/n57 | 10| 45| 18.29%
| | |
O_DATA_RDY | 7| 42| 17.07%
| | |
sender_impl/n2814 | 3| 40| 16.26%
| | |
sender_impl/n2824 | 2| 32| 13.01%
| | |
sender_impl/n2816 | 4| 27| 10.98%
| | |
crc16_impl/crc16_sel_0 | 6| 26| 10.57%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: CLK Source: clkgen_impl/SLICE_12.Q0 Loads: 86
Covered under: FREQUENCY PORT "CLK_4X" 100.000000 MHz ;
Data transfers from:
Clock Domain: CLK_4X_c Source: CLK_4X.PAD
Covered under: FREQUENCY PORT "CLK_4X" 100.000000 MHz ; Transfers: 1
Clock Domain: CLK_4X_c Source: CLK_4X.PAD Loads: 4
Covered under: FREQUENCY PORT "CLK_4X" 100.000000 MHz ;
Data transfers from:
Clock Domain: CLK Source: clkgen_impl/SLICE_12.Q0
Covered under: FREQUENCY PORT "CLK_4X" 100.000000 MHz ; Transfers: 2
Timing summary (Setup):
---------------
Timing errors: 246 Score: 357044
Cumulative negative slack: 201252
Constraints cover 2166 paths, 2 nets, and 1047 connections (91.9% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond_1.4_Production (87)
Sat Jun 30 14:40:13 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o qfn32samples_udrv.tw1 qfn32samples_udrv_map.ncd qfn32samples_udrv.prf
Design file: qfn32samples_udrv_map.ncd
Preference file: qfn32samples_udrv.prf
Device,speed: LCMXO2-256HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY PORT "CLK_4X" 100.000000 MHz (0 errors) 2159 items scored, 0 timing errors detected.
MULTICYCLE TO PORT "DP" 20.000000 X (0 errors) 2 items scored, 0 timing errors detected.
MULTICYCLE TO PORT "DM" 20.000000 X (0 errors) 2 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "CLK_4X" 100.000000 MHz ;
2159 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.349ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q crc16_impl/r_crc_i8 (from CLK -)
Destination: FF Data in crc16_impl/r_crc_i7 (to CLK -)
Delay: 0.330ns (39.7% logic, 60.3% route), 1 logic levels.
Constraint Details:
0.330ns physical path delay SLICE_1 to SLICE_1 meets
-0.019ns M_HLD and
0.000ns delay constraint requirement (totaling -0.019ns) by 0.349ns
Physical Path Details:
Data path SLICE_1 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 SLICE_1.CLK to SLICE_1.Q1 SLICE_1 (from CLK)
ROUTE 2 e 0.199 SLICE_1.Q1 to SLICE_1.M0 crc16_impl/r_crc_8 (to CLK)
--------
0.330 (39.7% logic, 60.3% route), 1 logic levels.
================================================================================
Preference: MULTICYCLE TO PORT "DP" 20.000000 X ;
2 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.507ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sender_impl/r_oe_150 (from CLK +)
Destination: Port Pad DP
Delay: 1.507ns (65.8% logic, 34.2% route), 2 logic levels.
Constraint Details:
1.507ns physical path delay DP_MGIOL to DP meets
0.000ns delay constraint by 1.507ns
Physical Path Details:
Data path DP_MGIOL to DP:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 0.150 DP_MGIOL.CLK to DP_MGIOL.IOLTO DP_MGIOL (from CLK)
ROUTE 1 e 0.515 DP_MGIOL.IOLTO to 27.IOLTO n715
TOTS_DEL --- 0.842 27.IOLTO to 27.PAD DP
--------
1.507 (65.8% logic, 34.2% route), 2 logic levels.
================================================================================
Preference: MULTICYCLE TO PORT "DM" 20.000000 X ;
2 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.507ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sender_impl/r_oe_150$r0 (from CLK +)
Destination: Port Pad DM
Delay: 1.507ns (65.8% logic, 34.2% route), 2 logic levels.
Constraint Details:
1.507ns physical path delay DM_MGIOL to DM meets
0.000ns delay constraint by 1.507ns
Physical Path Details:
Data path DM_MGIOL to DM:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 0.150 DM_MGIOL.CLK to DM_MGIOL.IOLTO DM_MGIOL (from CLK)
ROUTE 1 e 0.515 DM_MGIOL.IOLTO to 28.IOLTO n715$n0
TOTS_DEL --- 0.842 28.IOLTO to 28.PAD DM
--------
1.507 (65.8% logic, 34.2% route), 2 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "CLK_4X" 100.000000 MHz | | |
; | -| -| 1
| | |
MULTICYCLE TO PORT "DP" 20.000000 X ; | -| -| 2
| | |
MULTICYCLE TO PORT "DM" 20.000000 X ; | -| -| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: CLK Source: clkgen_impl/SLICE_12.Q0 Loads: 86
Covered under: FREQUENCY PORT "CLK_4X" 100.000000 MHz ;
Data transfers from:
Clock Domain: CLK_4X_c Source: CLK_4X.PAD
Covered under: FREQUENCY PORT "CLK_4X" 100.000000 MHz ; Transfers: 1
Clock Domain: CLK_4X_c Source: CLK_4X.PAD Loads: 4
Covered under: FREQUENCY PORT "CLK_4X" 100.000000 MHz ;
Data transfers from:
Clock Domain: CLK Source: clkgen_impl/SLICE_12.Q0
Covered under: FREQUENCY PORT "CLK_4X" 100.000000 MHz ; Transfers: 2
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 2166 paths, 2 nets, and 1047 connections (91.9% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 246 (setup), 0 (hold)
Score: 357044 (setup), 0 (hold)
Cumulative negative slack: 201252 (201252+0)
--------------------------------------------------------------------------------
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