Synthesis and Ngdbuild  Report
synthesis:  version Diamond_1.4_Production (87) 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp.   All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved. Copyright (c) 2001 Agere Systems   All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.
Fri Jul 06 15:58:50 2012 

Command Line:  synthesis -f qfn32samples_udrv_lattice.synproj 

-- all messages logged in file synthesis.log

Synthesis Options

INFO: Synthesis Options: (LSE-1022)
INFO: -a option is = MachXO2
INFO: -s option is = 4
INFO: -t option is = QFN32
INFO: -d option is = LCMXO2-256HC
INFO: Using package QFN32
INFO: Using performance grade 4
INFO:                                                           
INFO: ##########################################################
INFO: ### Lattice Family : MachXO2
INFO: ### Device  : LCMXO2-256HC
INFO: ### Package : QFN32
INFO: ### Speed   : 4
INFO: ##########################################################
INFO:                                                           
INFO: Optimization Goal = Area
INFO: -top option is not used
WARNING: Ignoring Frequency option in Area Mode, Setting to default frequency of 1.0 MHz
INFO: Target Frequency = 1.000000 MHz
INFO: Max Fanout = 1000
INFO: Timing Path count = 3
INFO: bram Utilization = 100.000000 %
INFO: dsp usage = TRUE (default)
INFO: dsp utilization = 100 (default)
INFO: fsm_encoding_style = auto
INFO: Mux style = Auto
INFO: Use Carry Chain = TRUE
INFO: carry_chain_length = 0
INFO: Use IO Insertion = TRUE
INFO: Use IO Reg = TRUE
INFO: Resource Sharing = TRUE
INFO: Propagate Constants = TRUE
INFO: Remove Duplicate Registers = TRUE
INFO: force_gsr = auto
INFO: ROM style = auto
INFO: RAM style = auto
INFO: -comp option is FALSE
INFO: -syn option is FALSE
INFO: -p Z:/XC2C/xo2qfn-w11 (searchpath added)
INFO: -p Y:/Program_Files/lscc/diamond/1.4/ispfpga/xo2c00/data (searchpath added)
INFO: -p Z:/XC2C/xo2qfn-w11/udrv (searchpath added)
INFO: -p Z:/XC2C/xo2qfn-w11 (searchpath added)
INFO: Verilog design file = Z:/XC2C/xo2qfn-w11/src/udrv.v
INFO: Ngd file = qfn32samples_udrv.ngd
INFO: -sdc option: sdc file input not used
INFO: -lpf option: output file option is OFF
INFO: hardtimer checking is enabled (default); -dt option not used
INFO: -r option is OFF [ Remove LOC Properties is OFF ]
-- Technology check ok...MachXO, MachXO2...
INFO: The default vhdl library search path is now "y:/program_files/lscc/diamond/1.4/cae_library/vhdl_packages/vdbs" (VHDL-1504)
INFO: * compile design *

Compile Design

INFO: Compile Design Begin
z:/xc2c/xo2qfn-w11/src/udrv.v(75): INFO: compiling module udrv (VERI-1018)
z:/xc2c/xo2qfn-w11/src/udrv.v(471): INFO: compiling module udrv_clkgen(PH=2) (VERI-1018)
z:/xc2c/xo2qfn-w11/src/udrv.v(796): INFO: compiling module udrv_fifo(DEPTH=5,DELAYED_INPUT=1) (VERI-1018)
z:/xc2c/xo2qfn-w11/src/udrv.v(502): INFO: compiling module udrv_reciever (VERI-1018)
z:/xc2c/xo2qfn-w11/src/udrv.v(625): INFO: compiling module udrv_sender(FS=1,SUPPORT_HOST=0) (VERI-1018)
z:/xc2c/xo2qfn-w11/src/udrv.v(874): INFO: compiling module udrv_crc(WIDTH=5,SEQUENTIAL_MATCHING=1) (VERI-1018)
z:/xc2c/xo2qfn-w11/src/udrv.v(874): INFO: compiling module udrv_crc(WIDTH=16,SEQUENTIAL_MATCHING=0) (VERI-1018)
z:/xc2c/xo2qfn-w11/src/udrv.v(922): INFO: compiling module udrv_spi (VERI-1018)
INFO: ######## Missing driver on net : n181, patching with GND... (LSE-1017)


INFO: ######## Found 1 RAM Nets in design (LSE-1115)
INFO: ######## Mapping RAM Net \fifo_impl/mem to 4 Distributed blocks in PSEUDO_DUAL_PORT Mode
INFO: GSR Instance connected to net: n310 (LSE-1148)
WARNING: No lpf file will be written because -lpf option is not used or set to 0
INFO: Applying 1.000000 MHz constraint to all clocks (LSE-5000)
INFO: Results of ngd drc checks are available in udrv_drc.log
INFO: All blocks are expanded and NGD expansion is successful
INFO: Writing ngd file qfn32samples_udrv.ngd

################### Begin Area Report (udrv)######################
Number of register bits => 140 of 1090 (12 % )
BB => 2
DCMA => 1
DPR16X4C => 4
FD1P3AX => 18
FD1P3IX => 50
FD1P3JX => 31
FD1S3AX => 26
FD1S3IX => 9
FD1S3JX => 4
GSR => 1
IB => 5
IFS1P3DX => 1
INV => 11
LUT4 => 207
OB => 6
OBZ => 1
OFS1P3DX => 1
PFUMX => 2
################### End Area Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 4
  Net : CLK, loads : 74
  Net : n19, loads : 35
  Net : i_clk4x, loads : 4
  Net : SCK_c, loads : 3
Clock Enable Nets
Number of Clock Enables: 36
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : i_recv_mode, loads : 32
  Net : n12, loads : 21
  Net : n7, loads : 20
  Net : recv_stat, loads : 16
  Net : n185, loads : 16
  Net : n953, loads : 16
  Net : RS_c, loads : 13
  Net : r_send_en, loads : 13
  Net : n1043, loads : 13
  Net : S_DATA_RDY, loads : 12
################### End Clock Report ##################

Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk2 [get_nets i_clk4x]                 |    1.000 MHz|  153.752 MHz|     4  
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk1 [get_nets SCK_c]                   |    1.000 MHz|  140.726 MHz|     2  
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk0 [get_nets CLK]                     |    1.000 MHz|   52.301 MHz|     5  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.


Peak Memory Usage: 41.824  MB

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Elapsed CPU time for LSE flow : 5.563  secs
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