Place & Route TRACE Report
Loading design for application trce from file qfn32samples_mcpu_efb.ncd.
Design name: mcpu
NCD version: 3.2
Vendor: LATTICE
Device: LCMXO2-256HC
Package: QFN32
Performance: 4
Loading device for application trce from file 'xo2c256.nph' in environment: Y:/Program_Files/lscc/diamond/1.4/ispfpga.
Package Status: Advanced Version 1.34
Performance Hardware Data Status: Final) Version 22.4
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond_1.4_Production (87)
Mon Jun 25 18:31:25 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_mcpu_efb.twr qfn32samples_mcpu_efb.ncd qfn32samples_mcpu_efb.prf
Design file: qfn32samples_mcpu_efb.ncd
Preference file: qfn32samples_mcpu_efb.prf
Device,speed: LCMXO2-256HC,4
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY PORT "CLK_3X" 48.000000 MHz (0 errors) 1182 items scored, 0 timing errors detected.
Report: 48.490MHz is the maximum frequency for this preference.
MULTICYCLE FROM GROUP "code" TO GROUP "akku" 2.000000 X (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY PORT "CLK_3X" 48.000000 MHz ;
1182 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 0.210ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM1 (from WE_mem +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 6.867ns (53.7% logic, 46.3% route), 6 logic levels.
Constraint Details:
6.867ns physical path delay sram_impl/mem1/SLICE_14 to SLICE_18 meets
20.833ns delay constraint less
13.590ns skew and
0.166ns DIN_SET requirement (totaling 7.077ns) by 0.210ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_14 to SLICE_18:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R3C2B.WCK to R3C2B.F0 sram_impl/mem1/SLICE_14 (from WE_mem)
ROUTE 2 1.394 R3C2B.F0 to R3C3B.D1 mem_data_2
C1TOFCO_DE --- 0.889 R3C3B.D1 to R3C3B.FCO SLICE_7
ROUTE 1 0.000 R3C3B.FCO to R3C3C.FCI n1545
FCITOFCO_D --- 0.162 R3C3C.FCI to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOFCO_D --- 0.162 R3C3D.FCI to R3C3D.FCO SLICE_5
ROUTE 1 0.000 R3C3D.FCO to R3C4A.FCI n1547
FCITOF0_DE --- 0.585 R3C4A.FCI to R3C4A.F0 SLICE_2
ROUTE 1 1.782 R3C4A.F0 to R2C3A.D1 n904
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
6.867 (53.7% logic, 46.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to sram_impl/mem1/SLICE_14:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.452 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 1.998 R4C4D.Q0 to R3C6C.A0 pc_2
CTOOFX_DEL --- 0.721 R3C6C.A0 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.241 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 1.001 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.721 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.241 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 2.256 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.495 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 2.140 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.495 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.445 R4C2D.F1 to R4C2D.C0 n9
CTOF_DEL --- 0.495 R4C2D.C0 to R4C2D.F0 SLICE_56
ROUTE 4 1.889 R4C2D.F0 to R3C2B.WCK WE_mem
--------
21.012 (27.1% logic, 72.9% route), 10 logic levels.
Destination Clock Path CLK_3X to SLICE_18:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 0.393ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 6.684ns (57.6% logic, 42.4% route), 7 logic levels.
Constraint Details:
6.684ns physical path delay sram_impl/mem1/SLICE_13 to SLICE_18 meets
20.833ns delay constraint less
13.590ns skew and
0.166ns DIN_SET requirement (totaling 7.077ns) by 0.393ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_13 to SLICE_18:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R3C2A.WCK to R3C2A.F0 sram_impl/mem1/SLICE_13 (from WE_mem)
ROUTE 2 1.049 R3C2A.F0 to R3C3A.D1 mem_data_0
C1TOFCO_DE --- 0.889 R3C3A.D1 to R3C3A.FCO SLICE_8
ROUTE 1 0.000 R3C3A.FCO to R3C3B.FCI n1544
FCITOFCO_D --- 0.162 R3C3B.FCI to R3C3B.FCO SLICE_7
ROUTE 1 0.000 R3C3B.FCO to R3C3C.FCI n1545
FCITOFCO_D --- 0.162 R3C3C.FCI to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOFCO_D --- 0.162 R3C3D.FCI to R3C3D.FCO SLICE_5
ROUTE 1 0.000 R3C3D.FCO to R3C4A.FCI n1547
FCITOF0_DE --- 0.585 R3C4A.FCI to R3C4A.F0 SLICE_2
ROUTE 1 1.782 R3C4A.F0 to R2C3A.D1 n904
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
6.684 (57.6% logic, 42.4% route), 7 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to sram_impl/mem1/SLICE_13:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.452 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 1.998 R4C4D.Q0 to R3C6C.A0 pc_2
CTOOFX_DEL --- 0.721 R3C6C.A0 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.241 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 1.001 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.721 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.241 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 2.256 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.495 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 2.140 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.495 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.445 R4C2D.F1 to R4C2D.C0 n9
CTOF_DEL --- 0.495 R4C2D.C0 to R4C2D.F0 SLICE_56
ROUTE 4 1.889 R4C2D.F0 to R3C2A.WCK WE_mem
--------
21.012 (27.1% logic, 72.9% route), 10 logic levels.
Destination Clock Path CLK_3X to SLICE_18:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 0.581ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM1 (from WE_mem +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 6.496ns (56.4% logic, 43.6% route), 5 logic levels.
Constraint Details:
6.496ns physical path delay sram_impl/mem1/SLICE_14 to SLICE_18 meets
20.833ns delay constraint less
13.590ns skew and
0.166ns DIN_SET requirement (totaling 7.077ns) by 0.581ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_14 to SLICE_18:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R3C2B.WCK to R3C2B.F1 sram_impl/mem1/SLICE_14 (from WE_mem)
ROUTE 2 1.051 R3C2B.F1 to R3C3C.D0 mem_data_3
C0TOFCO_DE --- 1.023 R3C3C.D0 to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOFCO_D --- 0.162 R3C3D.FCI to R3C3D.FCO SLICE_5
ROUTE 1 0.000 R3C3D.FCO to R3C4A.FCI n1547
FCITOF0_DE --- 0.585 R3C4A.FCI to R3C4A.F0 SLICE_2
ROUTE 1 1.782 R3C4A.F0 to R2C3A.D1 n904
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
6.496 (56.4% logic, 43.6% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to sram_impl/mem1/SLICE_14:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.452 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 1.998 R4C4D.Q0 to R3C6C.A0 pc_2
CTOOFX_DEL --- 0.721 R3C6C.A0 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.241 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 1.001 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.721 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.241 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 2.256 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.495 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 2.140 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.495 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.445 R4C2D.F1 to R4C2D.C0 n9
CTOF_DEL --- 0.495 R4C2D.C0 to R4C2D.F0 SLICE_56
ROUTE 4 1.889 R4C2D.F0 to R3C2B.WCK WE_mem
--------
21.012 (27.1% logic, 72.9% route), 10 logic levels.
Destination Clock Path CLK_3X to SLICE_18:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 0.726ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in akku_i2 (to master_clk +)
Delay: 6.351ns (53.9% logic, 46.1% route), 4 logic levels.
Constraint Details:
6.351ns physical path delay sram_impl/mem1/SLICE_13 to SLICE_16 meets
20.833ns delay constraint less
13.590ns skew and
0.166ns DIN_SET requirement (totaling 7.077ns) by 0.726ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_13 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R3C2A.WCK to R3C2A.F0 sram_impl/mem1/SLICE_13 (from WE_mem)
ROUTE 2 1.049 R3C2A.F0 to R3C3A.D1 mem_data_0
C1TOFCO_DE --- 0.889 R3C3A.D1 to R3C3A.FCO SLICE_8
ROUTE 1 0.000 R3C3A.FCO to R3C3B.FCI n1544
FCITOF1_DE --- 0.643 R3C3B.FCI to R3C3B.F1 SLICE_7
ROUTE 1 1.877 R3C3B.F1 to R4C3B.B0 n909
CTOF_DEL --- 0.495 R4C3B.B0 to R4C3B.F0 SLICE_16
ROUTE 1 0.000 R4C3B.F0 to R4C3B.DI0 n248 (to master_clk)
--------
6.351 (53.9% logic, 46.1% route), 4 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to sram_impl/mem1/SLICE_13:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.452 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 1.998 R4C4D.Q0 to R3C6C.A0 pc_2
CTOOFX_DEL --- 0.721 R3C6C.A0 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.241 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 1.001 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.721 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.241 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 2.256 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.495 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 2.140 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.495 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.445 R4C2D.F1 to R4C2D.C0 n9
CTOF_DEL --- 0.495 R4C2D.C0 to R4C2D.F0 SLICE_56
ROUTE 4 1.889 R4C2D.F0 to R3C2A.WCK WE_mem
--------
21.012 (27.1% logic, 72.9% route), 10 logic levels.
Destination Clock Path CLK_3X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R4C3B.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 0.838ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 6.239ns (61.3% logic, 38.7% route), 6 logic levels.
Constraint Details:
6.239ns physical path delay sram_impl/mem1/SLICE_13 to SLICE_18 meets
20.833ns delay constraint less
13.590ns skew and
0.166ns DIN_SET requirement (totaling 7.077ns) by 0.838ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_13 to SLICE_18:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R3C2A.WCK to R3C2A.F1 sram_impl/mem1/SLICE_13 (from WE_mem)
ROUTE 2 0.632 R3C2A.F1 to R3C3B.D0 mem_data_1
C0TOFCO_DE --- 1.023 R3C3B.D0 to R3C3B.FCO SLICE_7
ROUTE 1 0.000 R3C3B.FCO to R3C3C.FCI n1545
FCITOFCO_D --- 0.162 R3C3C.FCI to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOFCO_D --- 0.162 R3C3D.FCI to R3C3D.FCO SLICE_5
ROUTE 1 0.000 R3C3D.FCO to R3C4A.FCI n1547
FCITOF0_DE --- 0.585 R3C4A.FCI to R3C4A.F0 SLICE_2
ROUTE 1 1.782 R3C4A.F0 to R2C3A.D1 n904
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
6.239 (61.3% logic, 38.7% route), 6 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to sram_impl/mem1/SLICE_13:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.452 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 1.998 R4C4D.Q0 to R3C6C.A0 pc_2
CTOOFX_DEL --- 0.721 R3C6C.A0 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.241 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 1.001 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.721 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.241 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 2.256 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.495 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 2.140 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.495 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.445 R4C2D.F1 to R4C2D.C0 n9
CTOF_DEL --- 0.495 R4C2D.C0 to R4C2D.F0 SLICE_56
ROUTE 4 1.889 R4C2D.F0 to R3C2A.WCK WE_mem
--------
21.012 (27.1% logic, 72.9% route), 10 logic levels.
Destination Clock Path CLK_3X to SLICE_18:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 0.894ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem0/RAM1 (from WE_mem +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 7.453ns (45.2% logic, 54.8% route), 4 logic levels.
Constraint Details:
7.453ns physical path delay sram_impl/mem0/SLICE_11 to SLICE_18 meets
20.833ns delay constraint less
12.320ns skew and
0.166ns DIN_SET requirement (totaling 8.347ns) by 0.894ns
Physical Path Details:
Data path sram_impl/mem0/SLICE_11 to SLICE_18:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R4C2B.WCK to R4C2B.F0 sram_impl/mem0/SLICE_11 (from WE_mem)
ROUTE 2 2.304 R4C2B.F0 to R3C3D.D1 mem_data_6
C1TOFCO_DE --- 0.889 R3C3D.D1 to R3C3D.FCO SLICE_5
ROUTE 1 0.000 R3C3D.FCO to R3C4A.FCI n1547
FCITOF0_DE --- 0.585 R3C4A.FCI to R3C4A.F0 SLICE_2
ROUTE 1 1.782 R3C4A.F0 to R2C3A.D1 n904
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
7.453 (45.2% logic, 54.8% route), 4 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to sram_impl/mem0/SLICE_11:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.452 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 1.998 R4C4D.Q0 to R3C6C.A0 pc_2
CTOOFX_DEL --- 0.721 R3C6C.A0 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.241 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 1.001 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.721 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.241 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 2.256 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.495 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 2.140 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.495 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.445 R4C2D.F1 to R4C2D.C0 n9
CTOF_DEL --- 0.495 R4C2D.C0 to R4C2D.F0 SLICE_56
ROUTE 4 0.619 R4C2D.F0 to R4C2B.WCK WE_mem
--------
19.742 (28.8% logic, 71.2% route), 10 logic levels.
Destination Clock Path CLK_3X to SLICE_18:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 0.933ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM1 (from WE_mem +)
Destination: FF Data in akku_i6 (to master_clk +)
Delay: 6.144ns (58.4% logic, 41.6% route), 5 logic levels.
Constraint Details:
6.144ns physical path delay sram_impl/mem1/SLICE_14 to SLICE_18 meets
20.833ns delay constraint less
13.590ns skew and
0.166ns DIN_SET requirement (totaling 7.077ns) by 0.933ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_14 to SLICE_18:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R3C2B.WCK to R3C2B.F0 sram_impl/mem1/SLICE_14 (from WE_mem)
ROUTE 2 1.394 R3C2B.F0 to R3C3B.D1 mem_data_2
C1TOFCO_DE --- 0.889 R3C3B.D1 to R3C3B.FCO SLICE_7
ROUTE 1 0.000 R3C3B.FCO to R3C3C.FCI n1545
FCITOFCO_D --- 0.162 R3C3C.FCI to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOF1_DE --- 0.643 R3C3D.FCI to R3C3D.F1 SLICE_5
ROUTE 1 1.163 R3C3D.F1 to R2C3A.C0 n905
CTOF_DEL --- 0.495 R2C3A.C0 to R2C3A.F0 SLICE_18
ROUTE 1 0.000 R2C3A.F0 to R2C3A.DI0 n244 (to master_clk)
--------
6.144 (58.4% logic, 41.6% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to sram_impl/mem1/SLICE_14:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.452 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 1.998 R4C4D.Q0 to R3C6C.A0 pc_2
CTOOFX_DEL --- 0.721 R3C6C.A0 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.241 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 1.001 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.721 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.241 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 2.256 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.495 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 2.140 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.495 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.445 R4C2D.F1 to R4C2D.C0 n9
CTOF_DEL --- 0.495 R4C2D.C0 to R4C2D.F0 SLICE_56
ROUTE 4 1.889 R4C2D.F0 to R3C2B.WCK WE_mem
--------
21.012 (27.1% logic, 72.9% route), 10 logic levels.
Destination Clock Path CLK_3X to SLICE_18:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 1.116ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in akku_i6 (to master_clk +)
Delay: 5.961ns (62.9% logic, 37.1% route), 6 logic levels.
Constraint Details:
5.961ns physical path delay sram_impl/mem1/SLICE_13 to SLICE_18 meets
20.833ns delay constraint less
13.590ns skew and
0.166ns DIN_SET requirement (totaling 7.077ns) by 1.116ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_13 to SLICE_18:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R3C2A.WCK to R3C2A.F0 sram_impl/mem1/SLICE_13 (from WE_mem)
ROUTE 2 1.049 R3C2A.F0 to R3C3A.D1 mem_data_0
C1TOFCO_DE --- 0.889 R3C3A.D1 to R3C3A.FCO SLICE_8
ROUTE 1 0.000 R3C3A.FCO to R3C3B.FCI n1544
FCITOFCO_D --- 0.162 R3C3B.FCI to R3C3B.FCO SLICE_7
ROUTE 1 0.000 R3C3B.FCO to R3C3C.FCI n1545
FCITOFCO_D --- 0.162 R3C3C.FCI to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOF1_DE --- 0.643 R3C3D.FCI to R3C3D.F1 SLICE_5
ROUTE 1 1.163 R3C3D.F1 to R2C3A.C0 n905
CTOF_DEL --- 0.495 R2C3A.C0 to R2C3A.F0 SLICE_18
ROUTE 1 0.000 R2C3A.F0 to R2C3A.DI0 n244 (to master_clk)
--------
5.961 (62.9% logic, 37.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to sram_impl/mem1/SLICE_13:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.452 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 1.998 R4C4D.Q0 to R3C6C.A0 pc_2
CTOOFX_DEL --- 0.721 R3C6C.A0 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.241 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 1.001 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.721 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.241 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 2.256 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.495 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 2.140 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.495 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.445 R4C2D.F1 to R4C2D.C0 n9
CTOF_DEL --- 0.495 R4C2D.C0 to R4C2D.F0 SLICE_56
ROUTE 4 1.889 R4C2D.F0 to R3C2A.WCK WE_mem
--------
21.012 (27.1% logic, 72.9% route), 10 logic levels.
Destination Clock Path CLK_3X to SLICE_18:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 1.153ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM1 (from WE_mem +)
Destination: FF Data in akku_i5 (to master_clk +)
Delay: 5.924ns (59.6% logic, 40.4% route), 5 logic levels.
Constraint Details:
5.924ns physical path delay sram_impl/mem1/SLICE_14 to SLICE_17 meets
20.833ns delay constraint less
13.590ns skew and
0.166ns DIN_SET requirement (totaling 7.077ns) by 1.153ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_14 to SLICE_17:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R3C2B.WCK to R3C2B.F0 sram_impl/mem1/SLICE_14 (from WE_mem)
ROUTE 2 1.394 R3C2B.F0 to R3C3B.D1 mem_data_2
C1TOFCO_DE --- 0.889 R3C3B.D1 to R3C3B.FCO SLICE_7
ROUTE 1 0.000 R3C3B.FCO to R3C3C.FCI n1545
FCITOFCO_D --- 0.162 R3C3C.FCI to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOF0_DE --- 0.585 R3C3D.FCI to R3C3D.F0 SLICE_5
ROUTE 1 1.001 R3C3D.F0 to R4C3D.B1 n906
CTOF_DEL --- 0.495 R4C3D.B1 to R4C3D.F1 SLICE_17
ROUTE 1 0.000 R4C3D.F1 to R4C3D.DI1 n245 (to master_clk)
--------
5.924 (59.6% logic, 40.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to sram_impl/mem1/SLICE_14:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.452 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 1.998 R4C4D.Q0 to R3C6C.A0 pc_2
CTOOFX_DEL --- 0.721 R3C6C.A0 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.241 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 1.001 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.721 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.241 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 2.256 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.495 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 2.140 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.495 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.445 R4C2D.F1 to R4C2D.C0 n9
CTOF_DEL --- 0.495 R4C2D.C0 to R4C2D.F0 SLICE_56
ROUTE 4 1.889 R4C2D.F0 to R3C2B.WCK WE_mem
--------
21.012 (27.1% logic, 72.9% route), 10 logic levels.
Destination Clock Path CLK_3X to SLICE_17:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R4C3D.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Passed: The following path meets requirements by 1.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM1 (from WE_mem +)
Destination: FF Data in akku_i6 (to master_clk +)
Delay: 5.773ns (61.6% logic, 38.4% route), 4 logic levels.
Constraint Details:
5.773ns physical path delay sram_impl/mem1/SLICE_14 to SLICE_18 meets
20.833ns delay constraint less
13.590ns skew and
0.166ns DIN_SET requirement (totaling 7.077ns) by 1.304ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_14 to SLICE_18:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R3C2B.WCK to R3C2B.F1 sram_impl/mem1/SLICE_14 (from WE_mem)
ROUTE 2 1.051 R3C2B.F1 to R3C3C.D0 mem_data_3
C0TOFCO_DE --- 1.023 R3C3C.D0 to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOF1_DE --- 0.643 R3C3D.FCI to R3C3D.F1 SLICE_5
ROUTE 1 1.163 R3C3D.F1 to R2C3A.C0 n905
CTOF_DEL --- 0.495 R2C3A.C0 to R2C3A.F0 SLICE_18
ROUTE 1 0.000 R2C3A.F0 to R2C3A.DI0 n244 (to master_clk)
--------
5.773 (61.6% logic, 38.4% route), 4 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to sram_impl/mem1/SLICE_14:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.452 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 1.998 R4C4D.Q0 to R3C6C.A0 pc_2
CTOOFX_DEL --- 0.721 R3C6C.A0 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.241 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 1.001 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.721 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.241 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 2.256 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.495 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 2.140 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.495 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.445 R4C2D.F1 to R4C2D.C0 n9
CTOF_DEL --- 0.495 R4C2D.C0 to R4C2D.F0 SLICE_56
ROUTE 4 1.889 R4C2D.F0 to R3C2B.WCK WE_mem
--------
21.012 (27.1% logic, 72.9% route), 10 logic levels.
Destination Clock Path CLK_3X to SLICE_18:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK_3X
ROUTE 8 2.762 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
7.422 (24.6% logic, 75.4% route), 2 logic levels.
Report: 48.490MHz is the maximum frequency for this preference.
================================================================================
Preference: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 2.000000 X ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 28.238ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 13.262ns (36.6% logic, 63.4% route), 11 logic levels.
Constraint Details:
13.262ns physical path delay SLICE_23 to SLICE_18 meets
41.666ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 41.500ns) by 28.238ns
Physical Path Details:
Data path SLICE_23 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C4B.CLK to R4C4B.Q0 SLICE_23 (from master_clk)
ROUTE 26 2.524 R4C4B.Q0 to R2C6C.C1 pc_0
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_34
ROUTE 1 1.004 R2C6C.F1 to R2C6C.B0 n949
CTOOFX_DEL --- 0.721 R2C6C.B0 to R2C6C.OFX0 SLICE_34
ROUTE 1 0.000 R2C6C.OFX0 to R2C6C.FXB n1669
FXTOOFX_DE --- 0.241 R2C6C.FXB to R2C6C.OFX1 SLICE_34
ROUTE 6 2.043 R2C6C.OFX1 to R4C3C.C1 code_data_6
CTOF_DEL --- 0.495 R4C3C.C1 to R4C3C.F1 SLICE_58
ROUTE 16 1.050 R4C3C.F1 to R3C3A.A1 n1241
C1TOFCO_DE --- 0.889 R3C3A.A1 to R3C3A.FCO SLICE_8
ROUTE 1 0.000 R3C3A.FCO to R3C3B.FCI n1544
FCITOFCO_D --- 0.162 R3C3B.FCI to R3C3B.FCO SLICE_7
ROUTE 1 0.000 R3C3B.FCO to R3C3C.FCI n1545
FCITOFCO_D --- 0.162 R3C3C.FCI to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOFCO_D --- 0.162 R3C3D.FCI to R3C3D.FCO SLICE_5
ROUTE 1 0.000 R3C3D.FCO to R3C4A.FCI n1547
FCITOF0_DE --- 0.585 R3C4A.FCI to R3C4A.F0 SLICE_2
ROUTE 1 1.782 R3C4A.F0 to R2C3A.D1 n904
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
13.262 (36.6% logic, 63.4% route), 11 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R4C4B.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 28.242ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 13.258ns (36.4% logic, 63.6% route), 10 logic levels.
Constraint Details:
13.258ns physical path delay SLICE_23 to SLICE_18 meets
41.666ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 41.500ns) by 28.242ns
Physical Path Details:
Data path SLICE_23 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C4B.CLK to R4C4B.Q0 SLICE_23 (from master_clk)
ROUTE 26 2.524 R4C4B.Q0 to R2C6C.C1 pc_0
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_34
ROUTE 1 1.004 R2C6C.F1 to R2C6C.B0 n949
CTOOFX_DEL --- 0.721 R2C6C.B0 to R2C6C.OFX0 SLICE_34
ROUTE 1 0.000 R2C6C.OFX0 to R2C6C.FXB n1669
FXTOOFX_DE --- 0.241 R2C6C.FXB to R2C6C.OFX1 SLICE_34
ROUTE 6 2.043 R2C6C.OFX1 to R4C3C.C1 code_data_6
CTOF_DEL --- 0.495 R4C3C.C1 to R4C3C.F1 SLICE_58
ROUTE 16 1.074 R4C3C.F1 to R3C3B.B0 n1241
C0TOFCO_DE --- 1.023 R3C3B.B0 to R3C3B.FCO SLICE_7
ROUTE 1 0.000 R3C3B.FCO to R3C3C.FCI n1545
FCITOFCO_D --- 0.162 R3C3C.FCI to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOFCO_D --- 0.162 R3C3D.FCI to R3C3D.FCO SLICE_5
ROUTE 1 0.000 R3C3D.FCO to R3C4A.FCI n1547
FCITOF0_DE --- 0.585 R3C4A.FCI to R3C4A.F0 SLICE_2
ROUTE 1 1.782 R3C4A.F0 to R2C3A.D1 n904
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
13.258 (36.4% logic, 63.6% route), 10 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R4C4B.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 28.273ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 13.227ns (33.1% logic, 66.9% route), 8 logic levels.
Constraint Details:
13.227ns physical path delay SLICE_23 to SLICE_18 meets
41.666ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 41.500ns) by 28.273ns
Physical Path Details:
Data path SLICE_23 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C4B.CLK to R4C4B.Q0 SLICE_23 (from master_clk)
ROUTE 26 1.876 R4C4B.Q0 to R3C6D.A1 pc_0
CTOF_DEL --- 0.495 R3C6D.A1 to R3C6D.F1 SLICE_42
ROUTE 3 0.635 R3C6D.F1 to R3C6B.D1 n1251
CTOOFX_DEL --- 0.721 R3C6B.D1 to R3C6B.OFX0 i954/SLICE_36
ROUTE 1 0.000 R3C6B.OFX0 to R3C6A.FXA n1659
FXTOOFX_DE --- 0.241 R3C6A.FXA to R3C6A.OFX1 i955/SLICE_35
ROUTE 13 2.257 R3C6A.OFX1 to R4C2B.D0 code_data_3
CTOF_DEL --- 0.495 R4C2B.D0 to R4C2B.F0 sram_impl/mem0/SLICE_11
ROUTE 2 2.304 R4C2B.F0 to R3C3D.D1 mem_data_6
C1TOFCO_DE --- 0.889 R3C3D.D1 to R3C3D.FCO SLICE_5
ROUTE 1 0.000 R3C3D.FCO to R3C4A.FCI n1547
FCITOF0_DE --- 0.585 R3C4A.FCI to R3C4A.F0 SLICE_2
ROUTE 1 1.782 R3C4A.F0 to R2C3A.D1 n904
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
13.227 (33.1% logic, 66.9% route), 8 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R4C4B.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 28.376ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 13.124ns (35.8% logic, 64.2% route), 10 logic levels.
Constraint Details:
13.124ns physical path delay SLICE_23 to SLICE_18 meets
41.666ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 41.500ns) by 28.376ns
Physical Path Details:
Data path SLICE_23 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C4B.CLK to R4C4B.Q0 SLICE_23 (from master_clk)
ROUTE 26 2.524 R4C4B.Q0 to R2C6C.C1 pc_0
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_34
ROUTE 1 1.004 R2C6C.F1 to R2C6C.B0 n949
CTOOFX_DEL --- 0.721 R2C6C.B0 to R2C6C.OFX0 SLICE_34
ROUTE 1 0.000 R2C6C.OFX0 to R2C6C.FXB n1669
FXTOOFX_DE --- 0.241 R2C6C.FXB to R2C6C.OFX1 SLICE_34
ROUTE 6 2.043 R2C6C.OFX1 to R4C3C.C1 code_data_6
CTOF_DEL --- 0.495 R4C3C.C1 to R4C3C.F1 SLICE_58
ROUTE 16 1.074 R4C3C.F1 to R3C3B.B1 n1241
C1TOFCO_DE --- 0.889 R3C3B.B1 to R3C3B.FCO SLICE_7
ROUTE 1 0.000 R3C3B.FCO to R3C3C.FCI n1545
FCITOFCO_D --- 0.162 R3C3C.FCI to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOFCO_D --- 0.162 R3C3D.FCI to R3C3D.FCO SLICE_5
ROUTE 1 0.000 R3C3D.FCO to R3C4A.FCI n1547
FCITOF0_DE --- 0.585 R3C4A.FCI to R3C4A.F0 SLICE_2
ROUTE 1 1.782 R3C4A.F0 to R2C3A.D1 n904
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
13.124 (35.8% logic, 64.2% route), 10 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R4C4B.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 28.428ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 13.072ns (35.7% logic, 64.3% route), 9 logic levels.
Constraint Details:
13.072ns physical path delay SLICE_23 to SLICE_18 meets
41.666ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 41.500ns) by 28.428ns
Physical Path Details:
Data path SLICE_23 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C4B.CLK to R4C4B.Q0 SLICE_23 (from master_clk)
ROUTE 26 2.524 R4C4B.Q0 to R2C6C.C1 pc_0
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 SLICE_34
ROUTE 1 1.004 R2C6C.F1 to R2C6C.B0 n949
CTOOFX_DEL --- 0.721 R2C6C.B0 to R2C6C.OFX0 SLICE_34
ROUTE 1 0.000 R2C6C.OFX0 to R2C6C.FXB n1669
FXTOOFX_DE --- 0.241 R2C6C.FXB to R2C6C.OFX1 SLICE_34
ROUTE 6 2.043 R2C6C.OFX1 to R4C3C.C1 code_data_6
CTOF_DEL --- 0.495 R4C3C.C1 to R4C3C.F1 SLICE_58
ROUTE 16 1.050 R4C3C.F1 to R3C3C.A0 n1241
C0TOFCO_DE --- 1.023 R3C3C.A0 to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOFCO_D --- 0.162 R3C3D.FCI to R3C3D.FCO SLICE_5
ROUTE 1 0.000 R3C3D.FCO to R3C4A.FCI n1547
FCITOF0_DE --- 0.585 R3C4A.FCI to R3C4A.F0 SLICE_2
ROUTE 1 1.782 R3C4A.F0 to R2C3A.D1 n904
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
13.072 (35.7% logic, 64.3% route), 9 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R4C4B.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 28.435ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i2 (from master_clk +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 13.065ns (40.8% logic, 59.2% route), 12 logic levels.
Constraint Details:
13.065ns physical path delay SLICE_24 to SLICE_18 meets
41.666ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 41.500ns) by 28.435ns
Physical Path Details:
Data path SLICE_24 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C4D.CLK to R4C4D.Q0 SLICE_24 (from master_clk)
ROUTE 46 1.998 R4C4D.Q0 to R3C6C.A0 pc_2
CTOOFX_DEL --- 0.721 R3C6C.A0 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.241 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 1.001 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.721 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.241 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 1.908 R2C6A.OFX1 to R4C3C.D1 code_data_5
CTOF_DEL --- 0.495 R4C3C.D1 to R4C3C.F1 SLICE_58
ROUTE 16 1.050 R4C3C.F1 to R3C3A.A1 n1241
C1TOFCO_DE --- 0.889 R3C3A.A1 to R3C3A.FCO SLICE_8
ROUTE 1 0.000 R3C3A.FCO to R3C3B.FCI n1544
FCITOFCO_D --- 0.162 R3C3B.FCI to R3C3B.FCO SLICE_7
ROUTE 1 0.000 R3C3B.FCO to R3C3C.FCI n1545
FCITOFCO_D --- 0.162 R3C3C.FCI to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOFCO_D --- 0.162 R3C3D.FCI to R3C3D.FCO SLICE_5
ROUTE 1 0.000 R3C3D.FCO to R3C4A.FCI n1547
FCITOF0_DE --- 0.585 R3C4A.FCI to R3C4A.F0 SLICE_2
ROUTE 1 1.782 R3C4A.F0 to R2C3A.D1 n904
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
13.065 (40.8% logic, 59.2% route), 12 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R4C4D.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 28.435ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i2 (from master_clk +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 13.065ns (40.8% logic, 59.2% route), 12 logic levels.
Constraint Details:
13.065ns physical path delay SLICE_24 to SLICE_18 meets
41.666ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 41.500ns) by 28.435ns
Physical Path Details:
Data path SLICE_24 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C4D.CLK to R4C4D.Q0 SLICE_24 (from master_clk)
ROUTE 46 1.998 R4C4D.Q0 to R3C6C.A1 pc_2
CTOOFX_DEL --- 0.721 R3C6C.A1 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.241 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 1.001 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.721 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.241 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 1.908 R2C6A.OFX1 to R4C3C.D1 code_data_5
CTOF_DEL --- 0.495 R4C3C.D1 to R4C3C.F1 SLICE_58
ROUTE 16 1.050 R4C3C.F1 to R3C3A.A1 n1241
C1TOFCO_DE --- 0.889 R3C3A.A1 to R3C3A.FCO SLICE_8
ROUTE 1 0.000 R3C3A.FCO to R3C3B.FCI n1544
FCITOFCO_D --- 0.162 R3C3B.FCI to R3C3B.FCO SLICE_7
ROUTE 1 0.000 R3C3B.FCO to R3C3C.FCI n1545
FCITOFCO_D --- 0.162 R3C3C.FCI to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOFCO_D --- 0.162 R3C3D.FCI to R3C3D.FCO SLICE_5
ROUTE 1 0.000 R3C3D.FCO to R3C4A.FCI n1547
FCITOF0_DE --- 0.585 R3C4A.FCI to R3C4A.F0 SLICE_2
ROUTE 1 1.782 R3C4A.F0 to R2C3A.D1 n904
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
13.065 (40.8% logic, 59.2% route), 12 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R4C4D.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 28.439ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i2 (from master_clk +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 13.061ns (40.6% logic, 59.4% route), 11 logic levels.
Constraint Details:
13.061ns physical path delay SLICE_24 to SLICE_18 meets
41.666ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 41.500ns) by 28.439ns
Physical Path Details:
Data path SLICE_24 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C4D.CLK to R4C4D.Q0 SLICE_24 (from master_clk)
ROUTE 46 1.998 R4C4D.Q0 to R3C6C.A0 pc_2
CTOOFX_DEL --- 0.721 R3C6C.A0 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.241 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 1.001 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.721 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.241 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 1.908 R2C6A.OFX1 to R4C3C.D1 code_data_5
CTOF_DEL --- 0.495 R4C3C.D1 to R4C3C.F1 SLICE_58
ROUTE 16 1.074 R4C3C.F1 to R3C3B.B0 n1241
C0TOFCO_DE --- 1.023 R3C3B.B0 to R3C3B.FCO SLICE_7
ROUTE 1 0.000 R3C3B.FCO to R3C3C.FCI n1545
FCITOFCO_D --- 0.162 R3C3C.FCI to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOFCO_D --- 0.162 R3C3D.FCI to R3C3D.FCO SLICE_5
ROUTE 1 0.000 R3C3D.FCO to R3C4A.FCI n1547
FCITOF0_DE --- 0.585 R3C4A.FCI to R3C4A.F0 SLICE_2
ROUTE 1 1.782 R3C4A.F0 to R2C3A.D1 n904
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
13.061 (40.6% logic, 59.4% route), 11 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R4C4D.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 28.439ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i2 (from master_clk +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 13.061ns (40.6% logic, 59.4% route), 11 logic levels.
Constraint Details:
13.061ns physical path delay SLICE_24 to SLICE_18 meets
41.666ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 41.500ns) by 28.439ns
Physical Path Details:
Data path SLICE_24 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C4D.CLK to R4C4D.Q0 SLICE_24 (from master_clk)
ROUTE 46 1.998 R4C4D.Q0 to R3C6C.A1 pc_2
CTOOFX_DEL --- 0.721 R3C6C.A1 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.241 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 1.001 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.721 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.241 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 1.908 R2C6A.OFX1 to R4C3C.D1 code_data_5
CTOF_DEL --- 0.495 R4C3C.D1 to R4C3C.F1 SLICE_58
ROUTE 16 1.074 R4C3C.F1 to R3C3B.B0 n1241
C0TOFCO_DE --- 1.023 R3C3B.B0 to R3C3B.FCO SLICE_7
ROUTE 1 0.000 R3C3B.FCO to R3C3C.FCI n1545
FCITOFCO_D --- 0.162 R3C3C.FCI to R3C3C.FCO SLICE_6
ROUTE 1 0.000 R3C3C.FCO to R3C3D.FCI n1546
FCITOFCO_D --- 0.162 R3C3D.FCI to R3C3D.FCO SLICE_5
ROUTE 1 0.000 R3C3D.FCO to R3C4A.FCI n1547
FCITOF0_DE --- 0.585 R3C4A.FCI to R3C4A.F0 SLICE_2
ROUTE 1 1.782 R3C4A.F0 to R2C3A.D1 n904
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
13.061 (40.6% logic, 59.4% route), 11 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R4C4D.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 28.492ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i2 (from master_clk +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 13.008ns (33.6% logic, 66.4% route), 8 logic levels.
Constraint Details:
13.008ns physical path delay SLICE_24 to SLICE_18 meets
41.666ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 41.500ns) by 28.492ns
Physical Path Details:
Data path SLICE_24 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C4D.CLK to R4C4D.Q0 SLICE_24 (from master_clk)
ROUTE 46 1.657 R4C4D.Q0 to R3C6D.D1 pc_2
CTOF_DEL --- 0.495 R3C6D.D1 to R3C6D.F1 SLICE_42
ROUTE 3 0.635 R3C6D.F1 to R3C6B.D1 n1251
CTOOFX_DEL --- 0.721 R3C6B.D1 to R3C6B.OFX0 i954/SLICE_36
ROUTE 1 0.000 R3C6B.OFX0 to R3C6A.FXA n1659
FXTOOFX_DE --- 0.241 R3C6A.FXA to R3C6A.OFX1 i955/SLICE_35
ROUTE 13 2.257 R3C6A.OFX1 to R4C2B.D0 code_data_3
CTOF_DEL --- 0.495 R4C2B.D0 to R4C2B.F0 sram_impl/mem0/SLICE_11
ROUTE 2 2.304 R4C2B.F0 to R3C3D.D1 mem_data_6
C1TOFCO_DE --- 0.889 R3C3D.D1 to R3C3D.FCO SLICE_5
ROUTE 1 0.000 R3C3D.FCO to R3C4A.FCI n1547
FCITOF0_DE --- 0.585 R3C4A.FCI to R3C4A.F0 SLICE_2
ROUTE 1 1.782 R3C4A.F0 to R2C3A.D1 n904
CTOF_DEL --- 0.495 R2C3A.D1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
13.008 (33.6% logic, 66.4% route), 8 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R4C4D.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 13 2.836 R2C5C.Q0 to R2C3A.CLK master_clk
--------
2.836 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "CLK_3X" 48.000000 MHz ; | 48.000 MHz| 48.490 MHz| 6
| | |
MULTICYCLE FROM GROUP "code" TO GROUP | | |
"akku" 2.000000 X ; | 41.666 ns| 13.428 ns| 11
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 6 clocks:
Clock Domain: CLK_3X_c Source: CLK_3X.PAD Loads: 8
Covered under: FREQUENCY PORT "CLK_3X" 48.000000 MHz ;
Data transfers from:
Clock Domain: master_clk Source: SLICE_22.Q0
Covered under: FREQUENCY PORT "CLK_3X" 48.000000 MHz ; Transfers: 14
Clock Domain: master_clk Source: SLICE_22.Q0 Loads: 13
Covered under: FREQUENCY PORT "CLK_3X" 48.000000 MHz ;
Covered under: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 2.000000 X ;
Data transfers from:
Clock Domain: CLK_3X_c Source: CLK_3X.PAD
Covered under: FREQUENCY PORT "CLK_3X" 48.000000 MHz ; Transfers: 8
Clock Domain: WE_mem Source: SLICE_56.F0
Covered under: FREQUENCY PORT "CLK_3X" 48.000000 MHz ; Transfers: 8
Clock Domain: WE_mem Source: SLICE_56.F0 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: master_clk Source: SLICE_22.Q0
Covered under: FREQUENCY PORT "CLK_3X" 48.000000 MHz ; Transfers: 14
Clock Domain: i2c1_sclo Source: efb_impl/EFBInst_0.I2C1SCLO Loads: 1
No transfer within this clock domain is found
Clock Domain: i2c1_scli Source: SCL.PAD Loads: 1
No transfer within this clock domain is found
Clock Domain: O_STB_c Source: SLICE_59.F1 Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: master_clk Source: SLICE_22.Q0
Covered under: FREQUENCY PORT "CLK_3X" 48.000000 MHz ; Transfers: 8
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 8670 paths, 11 nets, and 615 connections (95.5% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond_1.4_Production (87)
Mon Jun 25 18:31:30 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_mcpu_efb.twr qfn32samples_mcpu_efb.ncd qfn32samples_mcpu_efb.prf
Design file: qfn32samples_mcpu_efb.ncd
Preference file: qfn32samples_mcpu_efb.prf
Device,speed: LCMXO2-256HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY PORT "CLK_3X" 48.000000 MHz (364 errors)
1182 items scored, 364 timing errors detected.
MULTICYCLE FROM GROUP "code" TO GROUP "akku" 2.000000 X (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "CLK_3X" 48.000000 MHz ;
1182 items scored, 364 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 4.809ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q akku_i5 (from master_clk +)
Destination: FF Data in r_oport_i5 (to O_STB_c +)
Delay: 0.385ns (34.0% logic, 66.0% route), 1 logic levels.
Constraint Details:
0.385ns physical path delay SLICE_17 to O_PORT_5_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-5.230ns skew requirement (totaling 5.194ns) by 4.809ns
Physical Path Details:
Data path SLICE_17 to O_PORT_5_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C3D.CLK to R4C3D.Q1 SLICE_17 (from master_clk)
ROUTE 5 0.254 R4C3D.Q1 to IOL_B2C.OPOS akku_5 (to O_STB_c)
--------
0.385 (34.0% logic, 66.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to SLICE_17:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R4C3D.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_3X to O_PORT_5_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.151 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 0.806 R4C4D.Q0 to R3C6C.A1 pc_2
CTOOFX_DEL --- 0.267 R3C6C.A1 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.098 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 0.316 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.267 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.098 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 0.743 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.174 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 0.727 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.174 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.327 R4C2D.F1 to R5C2A.B1 n9
CTOF_DEL --- 0.174 R5C2A.B1 to R5C2A.F1 SLICE_59
ROUTE 9 0.908 R5C2A.F1 to IOL_B2C.CLK O_STB_c
--------
7.696 (25.9% logic, 74.1% route), 10 logic levels.
Error: The following path exceeds requirements by 4.757ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q akku_i1 (from master_clk +)
Destination: FF Data in r_oport_i1 (to O_STB_c +)
Delay: 0.437ns (30.0% logic, 70.0% route), 1 logic levels.
Constraint Details:
0.437ns physical path delay SLICE_15 to O_PORT_1_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-5.230ns skew requirement (totaling 5.194ns) by 4.757ns
Physical Path Details:
Data path SLICE_15 to O_PORT_1_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R2C3D.CLK to R2C3D.Q1 SLICE_15 (from master_clk)
ROUTE 5 0.306 R2C3D.Q1 to IOL_T9D.OPOS akku_1 (to O_STB_c)
--------
0.437 (30.0% logic, 70.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to SLICE_15:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R2C3D.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_3X to O_PORT_1_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.151 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 0.806 R4C4D.Q0 to R3C6C.A1 pc_2
CTOOFX_DEL --- 0.267 R3C6C.A1 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.098 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 0.316 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.267 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.098 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 0.743 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.174 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 0.727 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.174 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.327 R4C2D.F1 to R5C2A.B1 n9
CTOF_DEL --- 0.174 R5C2A.B1 to R5C2A.F1 SLICE_59
ROUTE 9 0.908 R5C2A.F1 to IOL_T9D.CLK O_STB_c
--------
7.696 (25.9% logic, 74.1% route), 10 logic levels.
Error: The following path exceeds requirements by 4.701ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q akku_i4 (from master_clk +)
Destination: FF Data in r_oport_i4 (to O_STB_c +)
Delay: 0.493ns (26.6% logic, 73.4% route), 1 logic levels.
Constraint Details:
0.493ns physical path delay SLICE_17 to O_PORT_4_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-5.230ns skew requirement (totaling 5.194ns) by 4.701ns
Physical Path Details:
Data path SLICE_17 to O_PORT_4_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C3D.CLK to R4C3D.Q0 SLICE_17 (from master_clk)
ROUTE 5 0.362 R4C3D.Q0 to IOL_B2D.OPOS akku_4 (to O_STB_c)
--------
0.493 (26.6% logic, 73.4% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to SLICE_17:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R4C3D.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_3X to O_PORT_4_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.151 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 0.806 R4C4D.Q0 to R3C6C.A1 pc_2
CTOOFX_DEL --- 0.267 R3C6C.A1 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.098 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 0.316 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.267 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.098 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 0.743 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.174 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 0.727 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.174 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.327 R4C2D.F1 to R5C2A.B1 n9
CTOF_DEL --- 0.174 R5C2A.B1 to R5C2A.F1 SLICE_59
ROUTE 9 0.908 R5C2A.F1 to IOL_B2D.CLK O_STB_c
--------
7.696 (25.9% logic, 74.1% route), 10 logic levels.
Error: The following path exceeds requirements by 4.677ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q akku_i0 (from master_clk +)
Destination: FF Data in r_oport_i0 (to O_STB_c +)
Delay: 0.517ns (25.3% logic, 74.7% route), 1 logic levels.
Constraint Details:
0.517ns physical path delay SLICE_15 to O_PORT_0_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-5.230ns skew requirement (totaling 5.194ns) by 4.677ns
Physical Path Details:
Data path SLICE_15 to O_PORT_0_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R2C3D.CLK to R2C3D.Q0 SLICE_15 (from master_clk)
ROUTE 5 0.386 R2C3D.Q0 to IOL_T9B.OPOS akku_0 (to O_STB_c)
--------
0.517 (25.3% logic, 74.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to SLICE_15:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R2C3D.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_3X to O_PORT_0_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.151 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 0.806 R4C4D.Q0 to R3C6C.A1 pc_2
CTOOFX_DEL --- 0.267 R3C6C.A1 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.098 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 0.316 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.267 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.098 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 0.743 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.174 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 0.727 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.174 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.327 R4C2D.F1 to R5C2A.B1 n9
CTOF_DEL --- 0.174 R5C2A.B1 to R5C2A.F1 SLICE_59
ROUTE 9 0.908 R5C2A.F1 to IOL_T9B.CLK O_STB_c
--------
7.696 (25.9% logic, 74.1% route), 10 logic levels.
Error: The following path exceeds requirements by 4.579ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q akku_i7 (from master_clk +)
Destination: FF Data in r_oport_i7 (to O_STB_c +)
Delay: 0.615ns (21.3% logic, 78.7% route), 1 logic levels.
Constraint Details:
0.615ns physical path delay SLICE_18 to O_PORT_7_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-5.230ns skew requirement (totaling 5.194ns) by 4.579ns
Physical Path Details:
Data path SLICE_18 to O_PORT_7_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R2C3A.CLK to R2C3A.Q1 SLICE_18 (from master_clk)
ROUTE 5 0.484 R2C3A.Q1 to IOL_L5D.OPOS akku_7 (to O_STB_c)
--------
0.615 (21.3% logic, 78.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to SLICE_18:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R2C3A.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_3X to O_PORT_7_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.151 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 0.806 R4C4D.Q0 to R3C6C.A1 pc_2
CTOOFX_DEL --- 0.267 R3C6C.A1 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.098 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 0.316 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.267 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.098 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 0.743 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.174 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 0.727 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.174 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.327 R4C2D.F1 to R5C2A.B1 n9
CTOF_DEL --- 0.174 R5C2A.B1 to R5C2A.F1 SLICE_59
ROUTE 9 0.908 R5C2A.F1 to IOL_L5D.CLK O_STB_c
--------
7.696 (25.9% logic, 74.1% route), 10 logic levels.
Error: The following path exceeds requirements by 4.550ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q akku_i3 (from master_clk +)
Destination: FF Data in r_oport_i3 (to O_STB_c +)
Delay: 0.644ns (20.3% logic, 79.7% route), 1 logic levels.
Constraint Details:
0.644ns physical path delay SLICE_16 to O_PORT_3_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-5.230ns skew requirement (totaling 5.194ns) by 4.550ns
Physical Path Details:
Data path SLICE_16 to O_PORT_3_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C3B.CLK to R4C3B.Q1 SLICE_16 (from master_clk)
ROUTE 5 0.513 R4C3B.Q1 to IOL_R5B.OPOS akku_3 (to O_STB_c)
--------
0.644 (20.3% logic, 79.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R4C3B.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_3X to O_PORT_3_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.151 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 0.806 R4C4D.Q0 to R3C6C.A1 pc_2
CTOOFX_DEL --- 0.267 R3C6C.A1 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.098 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 0.316 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.267 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.098 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 0.743 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.174 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 0.727 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.174 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.327 R4C2D.F1 to R5C2A.B1 n9
CTOF_DEL --- 0.174 R5C2A.B1 to R5C2A.F1 SLICE_59
ROUTE 9 0.908 R5C2A.F1 to IOL_R5B.CLK O_STB_c
--------
7.696 (25.9% logic, 74.1% route), 10 logic levels.
Error: The following path exceeds requirements by 4.545ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q akku_i6 (from master_clk +)
Destination: FF Data in r_oport_i6 (to O_STB_c +)
Delay: 0.649ns (20.2% logic, 79.8% route), 1 logic levels.
Constraint Details:
0.649ns physical path delay SLICE_18 to O_PORT_6_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-5.230ns skew requirement (totaling 5.194ns) by 4.545ns
Physical Path Details:
Data path SLICE_18 to O_PORT_6_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R2C3A.CLK to R2C3A.Q0 SLICE_18 (from master_clk)
ROUTE 5 0.518 R2C3A.Q0 to IOL_B2A.OPOS akku_6 (to O_STB_c)
--------
0.649 (20.2% logic, 79.8% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to SLICE_18:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R2C3A.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_3X to O_PORT_6_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.151 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 0.806 R4C4D.Q0 to R3C6C.A1 pc_2
CTOOFX_DEL --- 0.267 R3C6C.A1 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.098 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 0.316 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.267 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.098 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 0.743 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.174 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 0.727 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.174 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.327 R4C2D.F1 to R5C2A.B1 n9
CTOF_DEL --- 0.174 R5C2A.B1 to R5C2A.F1 SLICE_59
ROUTE 9 0.908 R5C2A.F1 to IOL_B2A.CLK O_STB_c
--------
7.696 (25.9% logic, 74.1% route), 10 logic levels.
Error: The following path exceeds requirements by 4.444ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q akku_i2 (from master_clk +)
Destination: FF Data in sram_impl/mem1/RAM1 (to WE_mem +)
FF sram_impl/mem1/RAM1
Delay: 0.486ns (27.0% logic, 73.0% route), 2 logic levels.
Constraint Details:
0.486ns physical path delay SLICE_16 to sram_impl/mem1/SLICE_14 exceeds
0.129ns WD_HLD and
0.000ns delay constraint less
-4.801ns skew requirement (totaling 4.930ns) by 4.444ns
Physical Path Details:
Data path SLICE_16 to sram_impl/mem1/SLICE_14:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C3B.CLK to R4C3B.Q0 SLICE_16 (from master_clk)
ROUTE 5 0.355 R4C3B.Q0 to R3C2C.C1 akku_2
ZERO_DEL --- 0.000 R3C2C.C1 to R3C2C.WDO2 sram_impl/mem1/SLICE_12
ROUTE 1 0.000 R3C2C.WDO2 to R3C2B.WD0 sram_impl/mem1/WD2_INT (to WE_mem)
--------
0.486 (27.0% logic, 73.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R4C3B.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_3X to sram_impl/mem1/SLICE_14:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.151 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 0.806 R4C4D.Q0 to R3C6C.A0 pc_2
CTOOFX_DEL --- 0.267 R3C6C.A0 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.098 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 0.316 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.267 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.098 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 0.743 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.174 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 0.727 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.174 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.160 R4C2D.F1 to R4C2D.C0 n9
CTOF_DEL --- 0.174 R4C2D.C0 to R4C2D.F0 SLICE_56
ROUTE 4 0.646 R4C2D.F0 to R3C2B.WCK WE_mem
--------
7.267 (27.4% logic, 72.6% route), 10 logic levels.
Error: The following path exceeds requirements by 4.374ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q akku_i0 (from master_clk +)
Destination: FF Data in sram_impl/mem1/RAM0 (to WE_mem +)
FF sram_impl/mem1/RAM0
Delay: 0.556ns (23.6% logic, 76.4% route), 2 logic levels.
Constraint Details:
0.556ns physical path delay SLICE_15 to sram_impl/mem1/SLICE_13 exceeds
0.129ns WD_HLD and
0.000ns delay constraint less
-4.801ns skew requirement (totaling 4.930ns) by 4.374ns
Physical Path Details:
Data path SLICE_15 to sram_impl/mem1/SLICE_13:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R2C3D.CLK to R2C3D.Q0 SLICE_15 (from master_clk)
ROUTE 5 0.425 R2C3D.Q0 to R3C2C.A1 akku_0
ZERO_DEL --- 0.000 R3C2C.A1 to R3C2C.WDO0 sram_impl/mem1/SLICE_12
ROUTE 1 0.000 R3C2C.WDO0 to R3C2A.WD0 sram_impl/mem1/WD0_INT (to WE_mem)
--------
0.556 (23.6% logic, 76.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to SLICE_15:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R2C3D.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_3X to sram_impl/mem1/SLICE_13:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.151 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 0.806 R4C4D.Q0 to R3C6C.A0 pc_2
CTOOFX_DEL --- 0.267 R3C6C.A0 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.098 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 0.316 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.267 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.098 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 0.743 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.174 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 0.727 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.174 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.160 R4C2D.F1 to R4C2D.C0 n9
CTOF_DEL --- 0.174 R4C2D.C0 to R4C2D.F0 SLICE_56
ROUTE 4 0.646 R4C2D.F0 to R3C2A.WCK WE_mem
--------
7.267 (27.4% logic, 72.6% route), 10 logic levels.
Error: The following path exceeds requirements by 4.371ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q akku_i2 (from master_clk +)
Destination: FF Data in r_oport_i2 (to O_STB_c +)
Delay: 0.823ns (15.9% logic, 84.1% route), 1 logic levels.
Constraint Details:
0.823ns physical path delay SLICE_16 to O_PORT_2_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-5.230ns skew requirement (totaling 5.194ns) by 4.371ns
Physical Path Details:
Data path SLICE_16 to O_PORT_2_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C3B.CLK to R4C3B.Q0 SLICE_16 (from master_clk)
ROUTE 5 0.692 R4C3B.Q0 to IOL_R5A.OPOS akku_2 (to O_STB_c)
--------
0.823 (15.9% logic, 84.1% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK_3X to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R4C3B.CLK master_clk
--------
2.466 (23.9% logic, 76.1% route), 2 logic levels.
Destination Clock Path CLK_3X to O_PORT_2_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK_3X
ROUTE 8 0.883 12.PADDI to R2C5C.CLK CLK_3X_c
REG_DEL --- 0.151 R2C5C.CLK to R2C5C.Q0 SLICE_22
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
REG_DEL --- 0.151 R4C4D.CLK to R4C4D.Q0 SLICE_24
ROUTE 46 0.806 R4C4D.Q0 to R3C6C.A1 pc_2
CTOOFX_DEL --- 0.267 R3C6C.A1 to R3C6C.OFX0 SLICE_43
ROUTE 1 0.000 R3C6C.OFX0 to R3C6C.FXB n1666
FXTOOFX_DE --- 0.098 R3C6C.FXB to R3C6C.OFX1 SLICE_43
ROUTE 1 0.316 R3C6C.OFX1 to R2C6B.B0 n15_adj_7
CTOOFX_DEL --- 0.267 R2C6B.B0 to R2C6B.OFX0 SLICE_33
ROUTE 1 0.000 R2C6B.OFX0 to R2C6A.FXA n1656
FXTOOFX_DE --- 0.098 R2C6A.FXA to R2C6A.OFX1 i949/SLICE_39
ROUTE 5 0.743 R2C6A.OFX1 to R3C2D.A0 code_data_5
CTOF_DEL --- 0.174 R3C2D.A0 to R3C2D.F0 SLICE_57
ROUTE 3 0.727 R3C2D.F0 to R4C2D.A1 n1654
CTOF_DEL --- 0.174 R4C2D.A1 to R4C2D.F1 SLICE_56
ROUTE 2 0.327 R4C2D.F1 to R5C2A.B1 n9
CTOF_DEL --- 0.174 R5C2A.B1 to R5C2A.F1 SLICE_59
ROUTE 9 0.908 R5C2A.F1 to IOL_R5A.CLK O_STB_c
--------
7.696 (25.9% logic, 74.1% route), 10 logic levels.
================================================================================
Preference: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 2.000000 X ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.411ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from master_clk +)
Destination: FF Data in akku_i4 (to master_clk +)
Delay: 1.398ns (46.4% logic, 53.6% route), 6 logic levels.
Constraint Details:
1.398ns physical path delay SLICE_24 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.411ns
Physical Path Details:
Data path SLICE_24 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C4D.CLK to R4C4D.Q1 SLICE_24 (from master_clk)
ROUTE 46 0.145 R4C4D.Q1 to R4C5B.D1 pc_3
CTOOFX_DEL --- 0.153 R4C5B.D1 to R4C5B.OFX0 SLICE_50
ROUTE 1 0.000 R4C5B.OFX0 to R4C5A.FXA mux_86_Mux_2_0_f5a
FXTOOFX_DE --- 0.067 R4C5A.FXA to R4C5A.OFX1 SLICE_51
ROUTE 12 0.255 R4C5A.OFX1 to R4C2A.C0 code_data_2
CTOF_DEL --- 0.099 R4C2A.C0 to R4C2A.F0 sram_impl/mem0/SLICE_10
ROUTE 2 0.220 R4C2A.F0 to R4C3A.B1 mem_data_4
CTOF_DEL --- 0.099 R4C3A.B1 to R4C3A.F1 SLICE_63
ROUTE 1 0.130 R4C3A.F1 to R4C3D.D0 I_DATA_4
CTOF_DEL --- 0.099 R4C3D.D0 to R4C3D.F0 SLICE_17
ROUTE 1 0.000 R4C3D.F0 to R4C3D.DI0 n246 (to master_clk)
--------
1.398 (46.4% logic, 53.6% route), 6 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C3D.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.411ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from master_clk +)
Destination: FF Data in akku_i4 (to master_clk +)
Delay: 1.398ns (46.4% logic, 53.6% route), 6 logic levels.
Constraint Details:
1.398ns physical path delay SLICE_24 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.411ns
Physical Path Details:
Data path SLICE_24 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C4D.CLK to R4C4D.Q1 SLICE_24 (from master_clk)
ROUTE 46 0.145 R4C4D.Q1 to R4C5B.D0 pc_3
CTOOFX_DEL --- 0.153 R4C5B.D0 to R4C5B.OFX0 SLICE_50
ROUTE 1 0.000 R4C5B.OFX0 to R4C5A.FXA mux_86_Mux_2_0_f5a
FXTOOFX_DE --- 0.067 R4C5A.FXA to R4C5A.OFX1 SLICE_51
ROUTE 12 0.255 R4C5A.OFX1 to R4C2A.C0 code_data_2
CTOF_DEL --- 0.099 R4C2A.C0 to R4C2A.F0 sram_impl/mem0/SLICE_10
ROUTE 2 0.220 R4C2A.F0 to R4C3A.B1 mem_data_4
CTOF_DEL --- 0.099 R4C3A.B1 to R4C3A.F1 SLICE_63
ROUTE 1 0.130 R4C3A.F1 to R4C3D.D0 I_DATA_4
CTOF_DEL --- 0.099 R4C3D.D0 to R4C3D.F0 SLICE_17
ROUTE 1 0.000 R4C3D.F0 to R4C3D.DI0 n246 (to master_clk)
--------
1.398 (46.4% logic, 53.6% route), 6 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C3D.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.412ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: FF Data in akku_i4 (to master_clk +)
Delay: 1.399ns (37.2% logic, 62.8% route), 5 logic levels.
Constraint Details:
1.399ns physical path delay SLICE_23 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.412ns
Physical Path Details:
Data path SLICE_23 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C4B.CLK to R4C4B.Q0 SLICE_23 (from master_clk)
ROUTE 26 0.273 R4C4B.Q0 to R4C5A.M1 pc_0
MTOOFX_DEL --- 0.093 R4C5A.M1 to R4C5A.OFX1 SLICE_51
ROUTE 12 0.255 R4C5A.OFX1 to R4C2A.C0 code_data_2
CTOF_DEL --- 0.099 R4C2A.C0 to R4C2A.F0 sram_impl/mem0/SLICE_10
ROUTE 2 0.220 R4C2A.F0 to R4C3A.B1 mem_data_4
CTOF_DEL --- 0.099 R4C3A.B1 to R4C3A.F1 SLICE_63
ROUTE 1 0.130 R4C3A.F1 to R4C3D.D0 I_DATA_4
CTOF_DEL --- 0.099 R4C3D.D0 to R4C3D.F0 SLICE_17
ROUTE 1 0.000 R4C3D.F0 to R4C3D.DI0 n246 (to master_clk)
--------
1.399 (37.2% logic, 62.8% route), 5 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C4B.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C3D.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.414ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i2 (from master_clk +)
Destination: FF Data in akku_i4 (to master_clk +)
Delay: 1.401ns (46.3% logic, 53.7% route), 6 logic levels.
Constraint Details:
1.401ns physical path delay SLICE_24 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.414ns
Physical Path Details:
Data path SLICE_24 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C4D.CLK to R4C4D.Q0 SLICE_24 (from master_clk)
ROUTE 46 0.148 R4C4D.Q0 to R4C5A.C1 pc_2
CTOOFX_DEL --- 0.153 R4C5A.C1 to R4C5A.OFX0 SLICE_51
ROUTE 1 0.000 R4C5A.OFX0 to R4C5A.FXB mux_86_Mux_2_1_f5b
FXTOOFX_DE --- 0.067 R4C5A.FXB to R4C5A.OFX1 SLICE_51
ROUTE 12 0.255 R4C5A.OFX1 to R4C2A.C0 code_data_2
CTOF_DEL --- 0.099 R4C2A.C0 to R4C2A.F0 sram_impl/mem0/SLICE_10
ROUTE 2 0.220 R4C2A.F0 to R4C3A.B1 mem_data_4
CTOF_DEL --- 0.099 R4C3A.B1 to R4C3A.F1 SLICE_63
ROUTE 1 0.130 R4C3A.F1 to R4C3D.D0 I_DATA_4
CTOF_DEL --- 0.099 R4C3D.D0 to R4C3D.F0 SLICE_17
ROUTE 1 0.000 R4C3D.F0 to R4C3D.DI0 n246 (to master_clk)
--------
1.401 (46.3% logic, 53.7% route), 6 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C3D.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.414ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i2 (from master_clk +)
Destination: FF Data in akku_i4 (to master_clk +)
Delay: 1.401ns (46.3% logic, 53.7% route), 6 logic levels.
Constraint Details:
1.401ns physical path delay SLICE_24 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.414ns
Physical Path Details:
Data path SLICE_24 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C4D.CLK to R4C4D.Q0 SLICE_24 (from master_clk)
ROUTE 46 0.148 R4C4D.Q0 to R4C5A.C0 pc_2
CTOOFX_DEL --- 0.153 R4C5A.C0 to R4C5A.OFX0 SLICE_51
ROUTE 1 0.000 R4C5A.OFX0 to R4C5A.FXB mux_86_Mux_2_1_f5b
FXTOOFX_DE --- 0.067 R4C5A.FXB to R4C5A.OFX1 SLICE_51
ROUTE 12 0.255 R4C5A.OFX1 to R4C2A.C0 code_data_2
CTOF_DEL --- 0.099 R4C2A.C0 to R4C2A.F0 sram_impl/mem0/SLICE_10
ROUTE 2 0.220 R4C2A.F0 to R4C3A.B1 mem_data_4
CTOF_DEL --- 0.099 R4C3A.B1 to R4C3A.F1 SLICE_63
ROUTE 1 0.130 R4C3A.F1 to R4C3D.D0 I_DATA_4
CTOF_DEL --- 0.099 R4C3D.D0 to R4C3D.F0 SLICE_17
ROUTE 1 0.000 R4C3D.F0 to R4C3D.DI0 n246 (to master_clk)
--------
1.401 (46.3% logic, 53.7% route), 6 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C3D.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.485ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from master_clk +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 1.472ns (44.0% logic, 56.0% route), 6 logic levels.
Constraint Details:
1.472ns physical path delay SLICE_24 to SLICE_18 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.485ns
Physical Path Details:
Data path SLICE_24 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C4D.CLK to R4C4D.Q1 SLICE_24 (from master_clk)
ROUTE 46 0.145 R4C4D.Q1 to R4C5B.D1 pc_3
CTOOFX_DEL --- 0.153 R4C5B.D1 to R4C5B.OFX0 SLICE_50
ROUTE 1 0.000 R4C5B.OFX0 to R4C5A.FXA mux_86_Mux_2_0_f5a
FXTOOFX_DE --- 0.067 R4C5A.FXA to R4C5A.OFX1 SLICE_51
ROUTE 12 0.255 R4C5A.OFX1 to R4C2B.C1 code_data_2
CTOF_DEL --- 0.099 R4C2B.C1 to R4C2B.F1 sram_impl/mem0/SLICE_11
ROUTE 2 0.290 R4C2B.F1 to R2C2D.A1 mem_data_7
CTOF_DEL --- 0.099 R2C2D.A1 to R2C2D.F1 SLICE_27
ROUTE 1 0.134 R2C2D.F1 to R2C3A.C1 I_DATA_7
CTOF_DEL --- 0.099 R2C3A.C1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
1.472 (44.0% logic, 56.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R2C3A.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.485ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from master_clk +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 1.472ns (44.0% logic, 56.0% route), 6 logic levels.
Constraint Details:
1.472ns physical path delay SLICE_24 to SLICE_18 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.485ns
Physical Path Details:
Data path SLICE_24 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C4D.CLK to R4C4D.Q1 SLICE_24 (from master_clk)
ROUTE 46 0.145 R4C4D.Q1 to R4C5B.D0 pc_3
CTOOFX_DEL --- 0.153 R4C5B.D0 to R4C5B.OFX0 SLICE_50
ROUTE 1 0.000 R4C5B.OFX0 to R4C5A.FXA mux_86_Mux_2_0_f5a
FXTOOFX_DE --- 0.067 R4C5A.FXA to R4C5A.OFX1 SLICE_51
ROUTE 12 0.255 R4C5A.OFX1 to R4C2B.C1 code_data_2
CTOF_DEL --- 0.099 R4C2B.C1 to R4C2B.F1 sram_impl/mem0/SLICE_11
ROUTE 2 0.290 R4C2B.F1 to R2C2D.A1 mem_data_7
CTOF_DEL --- 0.099 R2C2D.A1 to R2C2D.F1 SLICE_27
ROUTE 1 0.134 R2C2D.F1 to R2C3A.C1 I_DATA_7
CTOF_DEL --- 0.099 R2C3A.C1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
1.472 (44.0% logic, 56.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_24:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C4D.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R2C3A.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.485ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i5 (from master_clk +)
Destination: FF Data in akku_i4 (to master_clk +)
Delay: 1.472ns (39.9% logic, 60.1% route), 6 logic levels.
Constraint Details:
1.472ns physical path delay SLICE_25 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.485ns
Physical Path Details:
Data path SLICE_25 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C4C.CLK to R4C4C.Q1 SLICE_25 (from master_clk)
ROUTE 19 0.279 R4C4C.Q1 to R4C5B.M0 pc_5
MTOOFX_DEL --- 0.093 R4C5B.M0 to R4C5B.OFX0 SLICE_50
ROUTE 1 0.000 R4C5B.OFX0 to R4C5A.FXA mux_86_Mux_2_0_f5a
FXTOOFX_DE --- 0.067 R4C5A.FXA to R4C5A.OFX1 SLICE_51
ROUTE 12 0.255 R4C5A.OFX1 to R4C2A.C0 code_data_2
CTOF_DEL --- 0.099 R4C2A.C0 to R4C2A.F0 sram_impl/mem0/SLICE_10
ROUTE 2 0.220 R4C2A.F0 to R4C3A.B1 mem_data_4
CTOF_DEL --- 0.099 R4C3A.B1 to R4C3A.F1 SLICE_63
ROUTE 1 0.130 R4C3A.F1 to R4C3D.D0 I_DATA_4
CTOF_DEL --- 0.099 R4C3D.D0 to R4C3D.F0 SLICE_17
ROUTE 1 0.000 R4C3D.F0 to R4C3D.DI0 n246 (to master_clk)
--------
1.472 (39.9% logic, 60.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_25:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C4C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C3D.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.485ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i5 (from master_clk +)
Destination: FF Data in akku_i4 (to master_clk +)
Delay: 1.472ns (39.9% logic, 60.1% route), 6 logic levels.
Constraint Details:
1.472ns physical path delay SLICE_25 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.485ns
Physical Path Details:
Data path SLICE_25 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C4C.CLK to R4C4C.Q1 SLICE_25 (from master_clk)
ROUTE 19 0.279 R4C4C.Q1 to R4C5A.M0 pc_5
MTOOFX_DEL --- 0.093 R4C5A.M0 to R4C5A.OFX0 SLICE_51
ROUTE 1 0.000 R4C5A.OFX0 to R4C5A.FXB mux_86_Mux_2_1_f5b
FXTOOFX_DE --- 0.067 R4C5A.FXB to R4C5A.OFX1 SLICE_51
ROUTE 12 0.255 R4C5A.OFX1 to R4C2A.C0 code_data_2
CTOF_DEL --- 0.099 R4C2A.C0 to R4C2A.F0 sram_impl/mem0/SLICE_10
ROUTE 2 0.220 R4C2A.F0 to R4C3A.B1 mem_data_4
CTOF_DEL --- 0.099 R4C3A.B1 to R4C3A.F1 SLICE_63
ROUTE 1 0.130 R4C3A.F1 to R4C3D.D0 I_DATA_4
CTOF_DEL --- 0.099 R4C3D.D0 to R4C3D.F0 SLICE_17
ROUTE 1 0.000 R4C3D.F0 to R4C3D.DI0 n246 (to master_clk)
--------
1.472 (39.9% logic, 60.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_25:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C4C.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C3D.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.486ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from master_clk +)
Destination: FF Data in akku_i7 (to master_clk +)
Delay: 1.473ns (35.4% logic, 64.6% route), 5 logic levels.
Constraint Details:
1.473ns physical path delay SLICE_23 to SLICE_18 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.486ns
Physical Path Details:
Data path SLICE_23 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C4B.CLK to R4C4B.Q0 SLICE_23 (from master_clk)
ROUTE 26 0.273 R4C4B.Q0 to R4C5A.M1 pc_0
MTOOFX_DEL --- 0.093 R4C5A.M1 to R4C5A.OFX1 SLICE_51
ROUTE 12 0.255 R4C5A.OFX1 to R4C2B.C1 code_data_2
CTOF_DEL --- 0.099 R4C2B.C1 to R4C2B.F1 sram_impl/mem0/SLICE_11
ROUTE 2 0.290 R4C2B.F1 to R2C2D.A1 mem_data_7
CTOF_DEL --- 0.099 R2C2D.A1 to R2C2D.F1 SLICE_27
ROUTE 1 0.134 R2C2D.F1 to R2C3A.C1 I_DATA_7
CTOF_DEL --- 0.099 R2C3A.C1 to R2C3A.F1 SLICE_18
ROUTE 1 0.000 R2C3A.F1 to R2C3A.DI1 n243 (to master_clk)
--------
1.473 (35.4% logic, 64.6% route), 5 logic levels.
Clock Skew Details:
Source Clock Path SLICE_22 to SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R4C4B.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path SLICE_22 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 13 0.993 R2C5C.Q0 to R2C3A.CLK master_clk
--------
0.993 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "CLK_3X" 48.000000 MHz ; | -| -| 1 *
| | |
MULTICYCLE FROM GROUP "code" TO GROUP | | |
"akku" 2.000000 X ; | -| -| 6
| | |
----------------------------------------------------------------------------
1 preference(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
code_data_3 | 13| 80| 21.98%
| | |
code_data_1 | 12| 76| 20.88%
| | |
code_data_2 | 12| 76| 20.88%
| | |
code_data_0 | 12| 76| 20.88%
| | |
pc_2 | 46| 68| 18.68%
| | |
pc_3 | 46| 64| 17.58%
| | |
pc_1 | 45| 64| 17.58%
| | |
pc_4 | 38| 56| 15.38%
| | |
sram_impl/mem1/AD3_INT | 2| 40| 10.99%
| | |
sram_impl/mem0/AD3_INT | 2| 40| 10.99%
| | |
n1659 | 1| 40| 10.99%
| | |
sram_impl/mem1/AD2_INT | 2| 38| 10.44%
| | |
sram_impl/mem1/AD1_INT | 2| 38| 10.44%
| | |
sram_impl/mem1/AD0_INT | 2| 38| 10.44%
| | |
sram_impl/mem0/AD2_INT | 2| 38| 10.44%
| | |
sram_impl/mem0/AD1_INT | 2| 38| 10.44%
| | |
sram_impl/mem0/AD0_INT | 2| 38| 10.44%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 6 clocks:
Clock Domain: CLK_3X_c Source: CLK_3X.PAD Loads: 8
Covered under: FREQUENCY PORT "CLK_3X" 48.000000 MHz ;
Data transfers from:
Clock Domain: master_clk Source: SLICE_22.Q0
Covered under: FREQUENCY PORT "CLK_3X" 48.000000 MHz ; Transfers: 14
Clock Domain: master_clk Source: SLICE_22.Q0 Loads: 13
Covered under: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 2.000000 X ;
Covered under: FREQUENCY PORT "CLK_3X" 48.000000 MHz ;
Data transfers from:
Clock Domain: CLK_3X_c Source: CLK_3X.PAD
Covered under: FREQUENCY PORT "CLK_3X" 48.000000 MHz ; Transfers: 8
Clock Domain: WE_mem Source: SLICE_56.F0
Covered under: FREQUENCY PORT "CLK_3X" 48.000000 MHz ; Transfers: 8
Clock Domain: WE_mem Source: SLICE_56.F0 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: master_clk Source: SLICE_22.Q0
Covered under: FREQUENCY PORT "CLK_3X" 48.000000 MHz ; Transfers: 14
Clock Domain: i2c1_sclo Source: efb_impl/EFBInst_0.I2C1SCLO Loads: 1
No transfer within this clock domain is found
Clock Domain: i2c1_scli Source: SCL.PAD Loads: 1
No transfer within this clock domain is found
Clock Domain: O_STB_c Source: SLICE_59.F1 Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: master_clk Source: SLICE_22.Q0
Covered under: FREQUENCY PORT "CLK_3X" 48.000000 MHz ; Transfers: 8
Timing summary (Hold):
---------------
Timing errors: 364 Score: 1165027
Cumulative negative slack: 1165027
Constraints cover 8670 paths, 11 nets, and 615 connections (95.5% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 364 (hold)
Score: 0 (setup), 1165027 (hold)
Cumulative negative slack: 1165027 (0+1165027)
--------------------------------------------------------------------------------
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