PAR: Place And Route Diamond_1.4_Production (87). Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Tue Jun 26 16:36:57 2012 Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_mcpu3_efb.p2t qfn32samples_mcpu3_efb_map.ncd qfn32samples_mcpu3_efb.dir qfn32samples_mcpu3_efb.prf Preference file: qfn32samples_mcpu3_efb.prf. Cost Table Summary Level/ Number Timing Run NCD Cost [ncd] Unrouted Score Time Status ---------- -------- -------- ----- ------------ 5_1 * 0 0 02:49 Complete * : Design saved. par done! Lattice Place and Route Report for Design "qfn32samples_mcpu3_efb_map.ncd" Tue Jun 26 16:36:57 2012 Best Par Run PAR: Place And Route Diamond_1.4_Production (87). Command Line: Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_mcpu3_efb.p2t qfn32samples_mcpu3_efb_map.ncd qfn32samples_mcpu3_efb.dir qfn32samples_mcpu3_efb.prf Preference file: qfn32samples_mcpu3_efb.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file qfn32samples_mcpu3_efb_map.ncd. Design name: mcpu NCD version: 3.2 Vendor: LATTICE Device: LCMXO2-256HC Package: QFN32 Performance: 4 Loading device for application par from file 'xo2c256.nph' in environment: Y:/Program_Files/lscc/diamond/1.4/ispfpga. Package Status: Advanced Version 1.34 Performance Hardware Data Status: Final) Version 22.4 License checked out. Ignore Preference Error(s): True WARNING - par: Source clock net WE_mem is not directly constrained. For this preference to work properly, please make sure the source of this clock is constrained. It appears in MULTICYCLE FROM CLKNET "WE_mem" 6.000000 X ; . Preserving this preference. Device utilization summary: PIO (prelim) 13/56 23% used 13/22 59% bonded IOLOGIC 8/56 14% used SLICE 109/128 85% used GSR 1/1 100% used EFB 1/1 100% used Number of Signals: 262 Number of Connections: 996 Pin Constraint Summary: 11 out of 13 pins locked (84% locked). The following 1 signal is selected to use the primary clock routing resources: master_clk (driver: SLICE_19, clk load #: 14) The following 3 signals are selected to use the secondary clock routing resources: CLK_2X_c (driver: CLK_2X, clk load #: 8, sr load #: 0, ce load #: 0) O_STB_c (driver: SLICE_88, clk load #: 8, sr load #: 0, ce load #: 0) RST_c (driver: RST, clk load #: 0, sr load #: 12, ce load #: 0) WARNING - par: Signal "CLK_2X_c" is selected to use Secondary clock resources; however its driver comp "CLK_2X" is located at "12", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it may suffer from excessive delay or skew. Signal RST_NEG is selected as Global Set/Reset. Starting Placer Phase 0. ...... Finished Placer Phase 0. REAL time: 45 secs Starting Placer Phase 1. ..................... Placer score = 34586. Finished Placer Phase 1. REAL time: 2 mins 19 secs Starting Placer Phase 2. . Placer score = 34493 Finished Placer Phase 2. REAL time: 2 mins 26 secs Clock Report Global Clock Resources: CLK_PIN : 1 out of 8 (12%) General PIO: 1 out of 56 (1%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY "master_clk" from Q0 on comp "SLICE_19" on site "R2C5A", clk load = 14 SECONDARY "CLK_2X_c" from comp "CLK_2X" on PIO site "12 (PB4B)", clk load = 8, ce load = 0, sr load = 0 SECONDARY "RST_c" from comp "RST" on CLK_PIN site "13 (PB4C)", clk load = 0, ce load = 0, sr load = 12 SECONDARY "O_STB_c" from F0 on comp "SLICE_88" on site "R5C2D", clk load = 8, ce load = 0, sr load = 0 PRIMARY : 1 out of 8 (12%) SECONDARY: 3 out of 8 (37%) I/O Usage Summary (final): 13 out of 56 (23.2%) PIO sites used. 13 out of 22 (59.1%) bonded PIO sites used. Number of PIO comps: 13; differential: 0 Number of Vref pins used: 0 I/O Bank Usage Summary: +----------+--------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+--------------+------------+-----------+ | 0 | 4 / 9 ( 44%) | 2.5V | - | | 1 | 2 / 2 (100%) | 2.5V | - | | 2 | 6 / 9 ( 66%) | 2.5V | - | | 3 | 1 / 2 ( 50%) | 2.5V | - | +----------+--------------+------------+-----------+ Total placer CPU time: 1 mins 18 secs Dumping design to file qfn32samples_mcpu3_efb.dir/5_1.ncd. 0 connections routed; 996 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 2 mins 37 secs Starting iterative routing. For each routing iteration the number inside the parenthesis is the total time (in picoseconds) the design is failing the timing constraints. For each routing iteration the router will attempt to reduce this number until the number of routing iterations is completed or the value is 0 meaning the design has fully met the timing constraints. End of iteration 1 996 successful; 0 unrouted; (0) real time: 2 mins 44 secs Dumping design to file qfn32samples_mcpu3_efb.dir/5_1.ncd. Total CPU time 1 mins 30 secs Total REAL time: 2 mins 44 secs Completely routed. End of route. 996 routed (100.00%); 0 unrouted. Checking DRC ... No errors found. Timing score: 0 Total REAL time to completion: 2 mins 49 secs Dumping design to file qfn32samples_mcpu3_efb.dir/5_1.ncd. All signals are completely routed. par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.