PAR: Place And Route Diamond_1.4_Production (87). Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Fri Jul 06 14:22:44 2012 Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_udrv.p2t qfn32samples_udrv_map.ncd qfn32samples_udrv.dir qfn32samples_udrv.prf Preference file: qfn32samples_udrv.prf. Cost Table Summary Level/ Number Timing Run NCD Cost [ncd] Unrouted Score Time Status ---------- -------- -------- ----- ------------ 5_1 * 0 0 01:31 Complete * : Design saved. par done! Lattice Place and Route Report for Design "qfn32samples_udrv_map.ncd" Fri Jul 06 14:22:44 2012 Best Par Run PAR: Place And Route Diamond_1.4_Production (87). Command Line: Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_udrv.p2t qfn32samples_udrv_map.ncd qfn32samples_udrv.dir qfn32samples_udrv.prf Preference file: qfn32samples_udrv.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file qfn32samples_udrv_map.ncd. Design name: udrv NCD version: 3.2 Vendor: LATTICE Device: LCMXO2-256HC Package: QFN32 Performance: 4 Loading device for application par from file 'xo2c256.nph' in environment: Y:/Program_Files/lscc/diamond/1.4/ispfpga. Package Status: Advanced Version 1.34 Performance Hardware Data Status: Final) Version 22.4 License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 14/56 25% used 14/22 63% bonded IOLOGIC 3/56 5% used SLICE 125/128 97% used GSR 1/1 100% used Number of Signals: 421 Number of Connections: 1254 WARNING - par: The JTAG Port has been disabled in this project and JTAG pins will be configured as General Purpose IO. You have to use JTAGENB pin in hardware to change the personality of the port from JTAG pins to general purpose IO. This mux control pin is dedicated to selection of JTAG pins for GPIO use by user design. Reference MachXO2 Handbook for details on dual-function JTAG port. Pin Constraint Summary: 14 out of 14 pins locked (100% locked). The following 3 signals are selected to use the primary clock routing resources: i_clk4x (driver: clk_selector, clk load #: 4) CLK (driver: clkgen_impl/SLICE_12, clk load #: 82) SCK_c (driver: SCK, clk load #: 15) The following 1 signal is selected to use the DCM clock routing resources: i_clk4x (driver: clk_selector, clk load #: 4) WARNING - par: Signal "CLK_4X_c" is selected to use Primary clock resources; however its driver comp "CLK_4X" is located at "20", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it may suffer from excessive delay or skew. The following 2 signals are selected to use the secondary clock routing resources: crc16_impl/n985 (driver: SLICE_121, clk load #: 0, sr load #: 10, ce load #: 0) n3236 (driver: SLICE_140, clk load #: 0, sr load #: 9, ce load #: 1) Signal nCS_c is selected as Global Set/Reset. Starting Placer Phase 0. ....... Finished Placer Phase 0. REAL time: 33 secs Starting Placer Phase 1. .................... Placer score = 45476. Finished Placer Phase 1. REAL time: 1 mins 19 secs Starting Placer Phase 2. . Placer score = 45293 Finished Placer Phase 2. REAL time: 1 mins 19 secs Clock Report Global Clock Resources: CLK_PIN : 1 out of 8 (12%) General PIO: 1 out of 56 (1%) DCM : 1 out of 2 (50%) DCC : 0 out of 8 (0%) Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY "CLK" from Q0 on comp "clkgen_impl/SLICE_12" on site "R2C5C", clk load = 82 PRIMARY "SCK_c" from comp "SCK" on CLK_PIN site "11 (PB4A)", clk load = 15 PRIMARY DCM "i_clk4x", total # of clk loads = 4 "i_clk4x" from comp "clk_selector" on DCM site "DCM6" - DCM input "CLK_4X_c" from comp "CLK_4X" on PIO site "20 (PR5B)" - DCM input "GND_net" from F0 on comp "SLICE_111" on site "R4C9C" SECONDARY "crc16_impl/n985" from F1 on comp "SLICE_121" on site "R5C2C", clk load = 0, ce load = 0, sr load = 10 SECONDARY "n3236" from F1 on comp "SLICE_140" on site "R5C2D", clk load = 0, ce load = 1, sr load = 9 PRIMARY : 3 out of 8 (37%) SECONDARY: 2 out of 8 (25%) I/O Usage Summary (final): 14 out of 56 (25.0%) PIO sites used. 14 out of 22 (63.6%) bonded PIO sites used. Number of PIO comps: 14; differential: 0 Number of Vref pins used: 0 I/O Bank Usage Summary: +----------+--------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+--------------+------------+-----------+ | 0 | 4 / 9 ( 44%) | 2.5V | - | | 1 | 2 / 2 (100%) | 2.5V | - | | 2 | 8 / 9 ( 88%) | 2.5V | - | | 3 | 0 / 2 ( 0%) | - | - | +----------+--------------+------------+-----------+ Total placer CPU time: 37 secs Dumping design to file qfn32samples_udrv.dir/5_1.ncd. 0 connections routed; 1254 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 1 mins 22 secs Starting iterative routing. For each routing iteration the number inside the parenthesis is the total time (in picoseconds) the design is failing the timing constraints. For each routing iteration the router will attempt to reduce this number until the number of routing iterations is completed or the value is 0 meaning the design has fully met the timing constraints. End of iteration 1 1254 successful; 0 unrouted; (0) real time: 1 mins 26 secs Dumping design to file qfn32samples_udrv.dir/5_1.ncd. Total CPU time 40 secs Total REAL time: 1 mins 26 secs Completely routed. End of route. 1254 routed (100.00%); 0 unrouted. Checking DRC ... No errors found. Timing score: 0 Total REAL time to completion: 1 mins 31 secs Dumping design to file qfn32samples_udrv.dir/5_1.ncd. All signals are completely routed. par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.