-------------------------------------------------------------------------------- Lattice TRACE Report - Setup Mon Jun 25 15:00:54 2012 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design file: mcpu Device,speed: LCMXO2-256HC,4 Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "CLK" 36.000000 MHz ; 30 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.907ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 15.565ns (40.8% logic, 59.2% route), 11 logic levels. Constraint Details: 15.565ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets 27.777ns delay constraint less 11.139ns skew and 0.166ns DIN_SET requirement (totaling 16.472ns) by 0.907ns Physical Path Details: Data path sram_impl/mem1/SLICE_8 to SLICE_16: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6A.WCK to R5C6A.F0 sram_impl/mem1/SLICE_8 (from WE_mem) ROUTE 2 1.544 R5C6A.F0 to R5C8A.B0 mem_data_0 CTOF_DEL --- 0.495 R5C8A.B0 to R5C8A.F0 alu_impl/SLICE_87 ROUTE 2 0.976 R5C8A.F0 to R5C8C.A1 n52_adj_27 CTOF_DEL --- 0.495 R5C8C.A1 to R5C8C.F1 SLICE_97 ROUTE 2 0.635 R5C8C.F1 to R5C8D.D1 alu_impl/alu_impl/alu_lo/n1896 CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 15.565 (40.8% logic, 59.2% route), 11 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.452 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 2.331 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.495 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.747 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.721 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.241 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 2.194 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.495 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 1.088 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.495 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 1.880 R5C4A.F0 to R5C6A.WCK WE_mem -------- 15.949 (26.8% logic, 73.2% route), 7 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Passed: The following path meets requirements by 2.368ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 14.104ns (41.5% logic, 58.5% route), 10 logic levels. Constraint Details: 14.104ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets 27.777ns delay constraint less 11.139ns skew and 0.166ns DIN_SET requirement (totaling 16.472ns) by 2.368ns Physical Path Details: Data path sram_impl/mem1/SLICE_8 to SLICE_16: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6A.WCK to R5C6A.F0 sram_impl/mem1/SLICE_8 (from WE_mem) ROUTE 2 1.544 R5C6A.F0 to R5C8A.B0 mem_data_0 CTOF_DEL --- 0.495 R5C8A.B0 to R5C8A.F0 alu_impl/SLICE_87 ROUTE 2 0.976 R5C8A.F0 to R5C8C.A1 n52_adj_27 CTOF_DEL --- 0.495 R5C8C.A1 to R5C8C.F1 SLICE_97 ROUTE 2 0.635 R5C8C.F1 to R5C8D.D1 alu_impl/alu_impl/alu_lo/n1896 CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.632 R5C7C.F1 to R4C7A.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C7A.D1 to R4C7A.F1 SLICE_84 ROUTE 1 0.693 R4C7A.F1 to R4C7A.B0 n1996 CTOF_DEL --- 0.495 R4C7A.B0 to R4C7A.F0 SLICE_84 ROUTE 2 0.967 R4C7A.F0 to R4C5D.D0 F_5 CTOF_DEL --- 0.495 R4C5D.D0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 14.104 (41.5% logic, 58.5% route), 10 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.452 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 2.331 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.495 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.747 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.721 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.241 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 2.194 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.495 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 1.088 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.495 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 1.880 R5C4A.F0 to R5C6A.WCK WE_mem -------- 15.949 (26.8% logic, 73.2% route), 7 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Passed: The following path meets requirements by 2.572ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 13.900ns (42.1% logic, 57.9% route), 10 logic levels. Constraint Details: 13.900ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets 27.777ns delay constraint less 11.139ns skew and 0.166ns DIN_SET requirement (totaling 16.472ns) by 2.572ns Physical Path Details: Data path sram_impl/mem1/SLICE_8 to SLICE_16: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6A.WCK to R5C6A.F1 sram_impl/mem1/SLICE_8 (from WE_mem) ROUTE 2 0.972 R5C6A.F1 to R5C8D.D0 mem_data_1 CTOF_DEL --- 0.495 R5C8D.D0 to R5C8D.F0 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 1.013 R5C8D.F0 to R5C8D.B1 n62_adj_28 CTOF_DEL --- 0.495 R5C8D.B1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 13.900 (42.1% logic, 57.9% route), 10 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.452 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 2.331 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.495 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.747 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.721 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.241 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 2.194 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.495 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 1.088 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.495 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 1.880 R5C4A.F0 to R5C6A.WCK WE_mem -------- 15.949 (26.8% logic, 73.2% route), 7 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Passed: The following path meets requirements by 2.702ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 13.770ns (42.5% logic, 57.5% route), 10 logic levels. Constraint Details: 13.770ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets 27.777ns delay constraint less 11.139ns skew and 0.166ns DIN_SET requirement (totaling 16.472ns) by 2.702ns Physical Path Details: Data path sram_impl/mem1/SLICE_8 to SLICE_16: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6A.WCK to R5C6A.F0 sram_impl/mem1/SLICE_8 (from WE_mem) ROUTE 2 1.088 R5C6A.F0 to R4C8A.C1 mem_data_0 CTOF_DEL --- 0.495 R4C8A.C1 to R4C8A.F1 alu_impl/SLICE_86 ROUTE 3 0.767 R4C8A.F1 to R5C8D.C1 n1105 CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 13.770 (42.5% logic, 57.5% route), 10 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.452 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 2.331 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.495 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.747 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.721 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.241 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 2.194 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.495 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 1.088 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.495 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 1.880 R5C4A.F0 to R5C6A.WCK WE_mem -------- 15.949 (26.8% logic, 73.2% route), 7 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Passed: The following path meets requirements by 2.908ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem0/RAM0 (from WE_mem +) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 13.040ns (37.3% logic, 62.7% route), 8 logic levels. Constraint Details: 13.040ns physical path delay SLICE_5 to SLICE_16 meets 27.777ns delay constraint less 11.663ns skew and 0.166ns DIN_SET requirement (totaling 15.948ns) by 2.908ns Physical Path Details: Data path SLICE_5 to SLICE_16: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R4C5A.WCK to R4C5A.F0 SLICE_5 (from WE_mem) ROUTE 2 2.815 R4C5A.F0 to R4C7B.D0 mem_data_4 CTOF_DEL --- 0.495 R4C7B.D0 to R4C7B.F0 alu_impl/SLICE_103 ROUTE 2 1.032 R4C7B.F0 to R5C7C.B1 n52 CTOF_DEL --- 0.495 R5C7C.B1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 13.040 (37.3% logic, 62.7% route), 8 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.452 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 2.331 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.495 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.747 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.721 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.241 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 2.194 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.495 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 1.088 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.495 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 2.404 R5C4A.F0 to R4C5A.WCK WE_mem -------- 16.473 (25.9% logic, 74.1% route), 7 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Passed: The following path meets requirements by 2.947ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 13.525ns (43.3% logic, 56.7% route), 10 logic levels. Constraint Details: 13.525ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets 27.777ns delay constraint less 11.139ns skew and 0.166ns DIN_SET requirement (totaling 16.472ns) by 2.947ns Physical Path Details: Data path sram_impl/mem1/SLICE_8 to SLICE_16: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6A.WCK to R5C6A.F1 sram_impl/mem1/SLICE_8 (from WE_mem) ROUTE 2 0.637 R5C6A.F1 to R5C7D.D0 mem_data_1 CTOF_DEL --- 0.495 R5C7D.D0 to R5C7D.F0 SLICE_89 ROUTE 2 0.973 R5C7D.F0 to R5C8D.A1 n1106 CTOF_DEL --- 0.495 R5C8D.A1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 13.525 (43.3% logic, 56.7% route), 10 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.452 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 2.331 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.495 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.747 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.721 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.241 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 2.194 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.495 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 1.088 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.495 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 1.880 R5C4A.F0 to R5C6A.WCK WE_mem -------- 15.949 (26.8% logic, 73.2% route), 7 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Passed: The following path meets requirements by 3.117ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +) Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i7 (to CLK_c +) Delay: 13.355ns (43.8% logic, 56.2% route), 10 logic levels. Constraint Details: 13.355ns physical path delay sram_impl/mem1/SLICE_8 to alu_impl_I/alu_impl/alu_hi/SLICE_14 meets 27.777ns delay constraint less 11.139ns skew and 0.166ns DIN_SET requirement (totaling 16.472ns) by 3.117ns Physical Path Details: Data path sram_impl/mem1/SLICE_8 to alu_impl_I/alu_impl/alu_hi/SLICE_14: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6A.WCK to R5C6A.F0 sram_impl/mem1/SLICE_8 (from WE_mem) ROUTE 2 1.544 R5C6A.F0 to R5C8A.B0 mem_data_0 CTOF_DEL --- 0.495 R5C8A.B0 to R5C8A.F0 alu_impl/SLICE_87 ROUTE 2 0.976 R5C8A.F0 to R5C8C.A1 n52_adj_27 CTOF_DEL --- 0.495 R5C8C.A1 to R5C8C.F1 SLICE_97 ROUTE 2 0.635 R5C8C.F1 to R5C8D.D1 alu_impl/alu_impl/alu_lo/n1896 CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 0.445 R3C6B.F1 to R3C6B.C0 F_7 CTOF_DEL --- 0.495 R3C6B.C0 to R3C6B.F0 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 1 0.000 R3C6B.F0 to R3C6B.DI0 alu_impl_I/alu_impl/alu_hi/n1204 (to CLK_c) -------- 13.355 (43.8% logic, 56.2% route), 10 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.452 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 2.331 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.495 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.747 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.721 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.241 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 2.194 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.495 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 1.088 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.495 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 1.880 R5C4A.F0 to R5C6A.WCK WE_mem -------- 15.949 (26.8% logic, 73.2% route), 7 logic levels. Destination Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_14: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R3C6B.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Passed: The following path meets requirements by 3.312ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 13.160ns (40.7% logic, 59.3% route), 9 logic levels. Constraint Details: 13.160ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets 27.777ns delay constraint less 11.139ns skew and 0.166ns DIN_SET requirement (totaling 16.472ns) by 3.312ns Physical Path Details: Data path sram_impl/mem1/SLICE_8 to SLICE_16: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6A.WCK to R5C6A.F0 sram_impl/mem1/SLICE_8 (from WE_mem) ROUTE 2 1.544 R5C6A.F0 to R5C8A.B0 mem_data_0 CTOF_DEL --- 0.495 R5C8A.B0 to R5C8A.F0 alu_impl/SLICE_87 ROUTE 2 0.976 R5C8A.F0 to R5C8C.A1 n52_adj_27 CTOF_DEL --- 0.495 R5C8C.A1 to R5C8C.F1 SLICE_97 ROUTE 2 0.635 R5C8C.F1 to R5C8D.D1 alu_impl/alu_impl/alu_lo/n1896 CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 1.015 R4C8B.F1 to R4C7C.B1 n1902 CTOF_DEL --- 0.495 R4C7C.B1 to R4C7C.F1 alu_impl/SLICE_101 ROUTE 1 1.554 R4C7C.F1 to R4C7D.D0 n1978 CTOF_DEL --- 0.495 R4C7D.D0 to R4C7D.F0 SLICE_85 ROUTE 2 0.324 R4C7D.F0 to R4C7C.D0 F_4 CTOF_DEL --- 0.495 R4C7C.D0 to R4C7C.F0 alu_impl/SLICE_101 ROUTE 1 1.001 R4C7C.F0 to R4C8C.B0 alu_impl/n3421 CTOF_DEL --- 0.495 R4C8C.B0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 13.160 (40.7% logic, 59.3% route), 9 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.452 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 2.331 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.495 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.747 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.721 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.241 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 2.194 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.495 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 1.088 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.495 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 1.880 R5C4A.F0 to R5C6A.WCK WE_mem -------- 15.949 (26.8% logic, 73.2% route), 7 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Passed: The following path meets requirements by 3.401ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 13.071ns (37.2% logic, 62.8% route), 8 logic levels. Constraint Details: 13.071ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets 27.777ns delay constraint less 11.139ns skew and 0.166ns DIN_SET requirement (totaling 16.472ns) by 3.401ns Physical Path Details: Data path sram_impl/mem1/SLICE_8 to SLICE_16: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6A.WCK to R5C6A.F0 sram_impl/mem1/SLICE_8 (from WE_mem) ROUTE 2 1.544 R5C6A.F0 to R5C8A.B0 mem_data_0 CTOF_DEL --- 0.495 R5C8A.B0 to R5C8A.F0 alu_impl/SLICE_87 ROUTE 2 0.976 R5C8A.F0 to R5C8C.A1 n52_adj_27 CTOF_DEL --- 0.495 R5C8C.A1 to R5C8C.F1 SLICE_97 ROUTE 2 0.635 R5C8C.F1 to R5C8D.D1 alu_impl/alu_impl/alu_lo/n1896 CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 1.376 R4C8B.F1 to R5C7A.D0 n1902 CTOF_DEL --- 0.495 R5C7A.D0 to R5C7A.F0 SLICE_78 ROUTE 2 1.852 R5C7A.F0 to R4C5D.B0 F_3 CTOF_DEL --- 0.495 R4C5D.B0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 13.071 (37.2% logic, 62.8% route), 8 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.452 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 2.331 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.495 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.747 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.721 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.241 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 2.194 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.495 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 1.088 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.495 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 1.880 R5C4A.F0 to R5C6A.WCK WE_mem -------- 15.949 (26.8% logic, 73.2% route), 7 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Passed: The following path meets requirements by 3.486ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q sram_impl/mem1/RAM1 (from WE_mem +) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 12.986ns (41.3% logic, 58.7% route), 9 logic levels. Constraint Details: 12.986ns physical path delay sram_impl/mem1/SLICE_9 to SLICE_16 meets 27.777ns delay constraint less 11.139ns skew and 0.166ns DIN_SET requirement (totaling 16.472ns) by 3.486ns Physical Path Details: Data path sram_impl/mem1/SLICE_9 to SLICE_16: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 1.398 R5C6B.WCK to R5C6B.F0 sram_impl/mem1/SLICE_9 (from WE_mem) ROUTE 2 1.306 R5C6B.F0 to R4C8B.A0 mem_data_2 CTOF_DEL --- 0.495 R4C8B.A0 to R4C8B.F0 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 1.013 R4C8B.F0 to R4C8B.B1 n72_adj_29 CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 12.986 (41.3% logic, 58.7% route), 9 logic levels. Clock Skew Details: Source Clock Path CLK to sram_impl/mem1/SLICE_9: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C5A.CLK CLK_c REG_DEL --- 0.452 R4C5A.CLK to R4C5A.Q0 SLICE_5 ROUTE 28 2.331 R4C5A.Q0 to R2C3A.A1 r_addr_0 CTOF_DEL --- 0.495 R2C3A.A1 to R2C3A.F1 rom_impl/SLICE_26 ROUTE 1 0.747 R2C3A.F1 to R2C3A.C0 rom_impl/n3041 CTOOFX_DEL --- 0.721 R2C3A.C0 to R2C3A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R2C3A.OFX0 to R2C3A.FXB rom_impl/n3436 FXTOOFX_DE --- 0.241 R2C3A.FXB to R2C3A.OFX1 rom_impl/SLICE_26 ROUTE 4 2.194 R2C3A.OFX1 to R5C2D.A1 code_data_4 CTOF_DEL --- 0.495 R5C2D.A1 to R5C2D.F1 SLICE_69 ROUTE 2 1.088 R5C2D.F1 to R5C4A.C0 n9 CTOF_DEL --- 0.495 R5C4A.C0 to R5C4A.F0 SLICE_70 ROUTE 4 1.880 R5C4A.F0 to R5C6B.WCK WE_mem -------- 15.949 (26.8% logic, 73.2% route), 7 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 4.810 (28.5% logic, 71.5% route), 1 logic levels. Report: 37.216MHz is the maximum frequency for this preference. ================================================================================ Preference: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.500000 X ; 30 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 6.720ns (weighted slack = 10.079ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 20.891ns (32.8% logic, 67.2% route), 14 logic levels. Constraint Details: 20.891ns physical path delay SLICE_5 to SLICE_16 meets 27.777ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 27.611ns) by 6.720ns Physical Path Details: Data path SLICE_5 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5A.CLK to R4C5A.Q0 SLICE_5 (from CLK_c) ROUTE 28 2.767 R4C5A.Q0 to R2C5B.A0 r_addr_0 CTOOFX_DEL --- 0.721 R2C5B.A0 to R2C5B.OFX0 alu_impl/i2733/SLICE_40 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA alu_impl/n3438 FXTOOFX_DE --- 0.241 R2C5A.FXA to R2C5A.OFX1 alu_impl/i2734/SLICE_39 ROUTE 17 2.464 R2C5A.OFX1 to R5C6D.A0 code_data_7 CTOF_DEL --- 0.495 R5C6D.A0 to R5C6D.F0 SLICE_72 ROUTE 8 1.128 R5C6D.F0 to R5C8A.C0 n1921 CTOF_DEL --- 0.495 R5C8A.C0 to R5C8A.F0 alu_impl/SLICE_87 ROUTE 2 0.976 R5C8A.F0 to R5C8C.A1 n52_adj_27 CTOF_DEL --- 0.495 R5C8C.A1 to R5C8C.F1 SLICE_97 ROUTE 2 0.635 R5C8C.F1 to R5C8D.D1 alu_impl/alu_impl/alu_lo/n1896 CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 20.891 (32.8% logic, 67.2% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C5A.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 6.720ns (weighted slack = 10.079ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 20.891ns (32.8% logic, 67.2% route), 14 logic levels. Constraint Details: 20.891ns physical path delay SLICE_5 to SLICE_16 meets 27.777ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 27.611ns) by 6.720ns Physical Path Details: Data path SLICE_5 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5A.CLK to R4C5A.Q0 SLICE_5 (from CLK_c) ROUTE 28 2.767 R4C5A.Q0 to R2C5B.A1 r_addr_0 CTOOFX_DEL --- 0.721 R2C5B.A1 to R2C5B.OFX0 alu_impl/i2733/SLICE_40 ROUTE 1 0.000 R2C5B.OFX0 to R2C5A.FXA alu_impl/n3438 FXTOOFX_DE --- 0.241 R2C5A.FXA to R2C5A.OFX1 alu_impl/i2734/SLICE_39 ROUTE 17 2.464 R2C5A.OFX1 to R5C6D.A0 code_data_7 CTOF_DEL --- 0.495 R5C6D.A0 to R5C6D.F0 SLICE_72 ROUTE 8 1.128 R5C6D.F0 to R5C8A.C0 n1921 CTOF_DEL --- 0.495 R5C8A.C0 to R5C8A.F0 alu_impl/SLICE_87 ROUTE 2 0.976 R5C8A.F0 to R5C8C.A1 n52_adj_27 CTOF_DEL --- 0.495 R5C8C.A1 to R5C8C.F1 SLICE_97 ROUTE 2 0.635 R5C8C.F1 to R5C8D.D1 alu_impl/alu_impl/alu_lo/n1896 CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 20.891 (32.8% logic, 67.2% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C5A.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 6.956ns (weighted slack = 10.433ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 20.655ns (33.2% logic, 66.8% route), 14 logic levels. Constraint Details: 20.655ns physical path delay SLICE_5 to SLICE_16 meets 27.777ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 27.611ns) by 6.956ns Physical Path Details: Data path SLICE_5 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5A.CLK to R4C5A.Q0 SLICE_5 (from CLK_c) ROUTE 28 2.531 R4C5A.Q0 to R2C5A.B1 r_addr_0 CTOOFX_DEL --- 0.721 R2C5A.B1 to R2C5A.OFX0 alu_impl/i2734/SLICE_39 ROUTE 1 0.000 R2C5A.OFX0 to R2C5A.FXB alu_impl/n3439 FXTOOFX_DE --- 0.241 R2C5A.FXB to R2C5A.OFX1 alu_impl/i2734/SLICE_39 ROUTE 17 2.464 R2C5A.OFX1 to R5C6D.A0 code_data_7 CTOF_DEL --- 0.495 R5C6D.A0 to R5C6D.F0 SLICE_72 ROUTE 8 1.128 R5C6D.F0 to R5C8A.C0 n1921 CTOF_DEL --- 0.495 R5C8A.C0 to R5C8A.F0 alu_impl/SLICE_87 ROUTE 2 0.976 R5C8A.F0 to R5C8C.A1 n52_adj_27 CTOF_DEL --- 0.495 R5C8C.A1 to R5C8C.F1 SLICE_97 ROUTE 2 0.635 R5C8C.F1 to R5C8D.D1 alu_impl/alu_impl/alu_lo/n1896 CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 20.655 (33.2% logic, 66.8% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C5A.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 6.956ns (weighted slack = 10.433ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 20.655ns (33.2% logic, 66.8% route), 14 logic levels. Constraint Details: 20.655ns physical path delay SLICE_5 to SLICE_16 meets 27.777ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 27.611ns) by 6.956ns Physical Path Details: Data path SLICE_5 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5A.CLK to R4C5A.Q0 SLICE_5 (from CLK_c) ROUTE 28 2.531 R4C5A.Q0 to R2C5A.B0 r_addr_0 CTOOFX_DEL --- 0.721 R2C5A.B0 to R2C5A.OFX0 alu_impl/i2734/SLICE_39 ROUTE 1 0.000 R2C5A.OFX0 to R2C5A.FXB alu_impl/n3439 FXTOOFX_DE --- 0.241 R2C5A.FXB to R2C5A.OFX1 alu_impl/i2734/SLICE_39 ROUTE 17 2.464 R2C5A.OFX1 to R5C6D.A0 code_data_7 CTOF_DEL --- 0.495 R5C6D.A0 to R5C6D.F0 SLICE_72 ROUTE 8 1.128 R5C6D.F0 to R5C8A.C0 n1921 CTOF_DEL --- 0.495 R5C8A.C0 to R5C8A.F0 alu_impl/SLICE_87 ROUTE 2 0.976 R5C8A.F0 to R5C8C.A1 n52_adj_27 CTOF_DEL --- 0.495 R5C8C.A1 to R5C8C.F1 SLICE_97 ROUTE 2 0.635 R5C8C.F1 to R5C8D.D1 alu_impl/alu_impl/alu_lo/n1896 CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 20.655 (33.2% logic, 66.8% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C5A.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 7.295ns (weighted slack = 10.942ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 20.316ns (33.8% logic, 66.2% route), 14 logic levels. Constraint Details: 20.316ns physical path delay SLICE_25 to SLICE_16 meets 27.777ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 27.611ns) by 7.295ns Physical Path Details: Data path SLICE_25 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5D.CLK to R4C5D.Q0 SLICE_25 (from CLK_c) ROUTE 60 2.235 R4C5D.Q0 to R2C2C.B1 r_addr_4 CTOOFX_DEL --- 0.721 R2C2C.B1 to R2C2C.OFX0 rom_impl/SLICE_56 ROUTE 1 0.000 R2C2C.OFX0 to R2C2C.FXB rom_impl/mux_90_Mux_0_1_f5b FXTOOFX_DE --- 0.241 R2C2C.FXB to R2C2C.OFX1 rom_impl/SLICE_56 ROUTE 12 2.005 R2C2C.OFX1 to R5C6A.A0 code_data_0 CTOF_DEL --- 0.495 R5C6A.A0 to R5C6A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.544 R5C6A.F0 to R5C8A.B0 mem_data_0 CTOF_DEL --- 0.495 R5C8A.B0 to R5C8A.F0 alu_impl/SLICE_87 ROUTE 2 0.976 R5C8A.F0 to R5C8C.A1 n52_adj_27 CTOF_DEL --- 0.495 R5C8C.A1 to R5C8C.F1 SLICE_97 ROUTE 2 0.635 R5C8C.F1 to R5C8D.D1 alu_impl/alu_impl/alu_lo/n1896 CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 20.316 (33.8% logic, 66.2% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_25: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C5D.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 7.295ns (weighted slack = 10.942ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 20.316ns (33.8% logic, 66.2% route), 14 logic levels. Constraint Details: 20.316ns physical path delay SLICE_25 to SLICE_16 meets 27.777ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 27.611ns) by 7.295ns Physical Path Details: Data path SLICE_25 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5D.CLK to R4C5D.Q0 SLICE_25 (from CLK_c) ROUTE 60 2.235 R4C5D.Q0 to R2C2C.B0 r_addr_4 CTOOFX_DEL --- 0.721 R2C2C.B0 to R2C2C.OFX0 rom_impl/SLICE_56 ROUTE 1 0.000 R2C2C.OFX0 to R2C2C.FXB rom_impl/mux_90_Mux_0_1_f5b FXTOOFX_DE --- 0.241 R2C2C.FXB to R2C2C.OFX1 rom_impl/SLICE_56 ROUTE 12 2.005 R2C2C.OFX1 to R5C6A.A0 code_data_0 CTOF_DEL --- 0.495 R5C6A.A0 to R5C6A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.544 R5C6A.F0 to R5C8A.B0 mem_data_0 CTOF_DEL --- 0.495 R5C8A.B0 to R5C8A.F0 alu_impl/SLICE_87 ROUTE 2 0.976 R5C8A.F0 to R5C8C.A1 n52_adj_27 CTOF_DEL --- 0.495 R5C8C.A1 to R5C8C.F1 SLICE_97 ROUTE 2 0.635 R5C8C.F1 to R5C8D.D1 alu_impl/alu_impl/alu_lo/n1896 CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 20.316 (33.8% logic, 66.2% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_25: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C5D.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 7.391ns (weighted slack = 11.086ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i4 (from CLK_c -) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 20.220ns (33.9% logic, 66.1% route), 14 logic levels. Constraint Details: 20.220ns physical path delay SLICE_6 to SLICE_16 meets 27.777ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 27.611ns) by 7.391ns Physical Path Details: Data path SLICE_6 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5B.CLK to R4C5B.Q1 SLICE_6 (from CLK_c) ROUTE 67 2.299 R4C5B.Q1 to R2C2B.A1 r_addr_3 CTOOFX_DEL --- 0.721 R2C2B.A1 to R2C2B.OFX0 SLICE_43 ROUTE 1 0.000 R2C2B.OFX0 to R2C2A.FXA mux_90_Mux_2_0_f5a FXTOOFX_DE --- 0.241 R2C2A.FXA to R2C2A.OFX1 SLICE_44 ROUTE 12 1.845 R2C2A.OFX1 to R5C6A.C0 code_data_2 CTOF_DEL --- 0.495 R5C6A.C0 to R5C6A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.544 R5C6A.F0 to R5C8A.B0 mem_data_0 CTOF_DEL --- 0.495 R5C8A.B0 to R5C8A.F0 alu_impl/SLICE_87 ROUTE 2 0.976 R5C8A.F0 to R5C8C.A1 n52_adj_27 CTOF_DEL --- 0.495 R5C8C.A1 to R5C8C.F1 SLICE_97 ROUTE 2 0.635 R5C8C.F1 to R5C8D.D1 alu_impl/alu_impl/alu_lo/n1896 CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 20.220 (33.9% logic, 66.1% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C5B.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 7.391ns (weighted slack = 11.086ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i4 (from CLK_c -) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 20.220ns (33.9% logic, 66.1% route), 14 logic levels. Constraint Details: 20.220ns physical path delay SLICE_6 to SLICE_16 meets 27.777ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 27.611ns) by 7.391ns Physical Path Details: Data path SLICE_6 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5B.CLK to R4C5B.Q1 SLICE_6 (from CLK_c) ROUTE 67 2.299 R4C5B.Q1 to R2C2A.A1 r_addr_3 CTOOFX_DEL --- 0.721 R2C2A.A1 to R2C2A.OFX0 SLICE_44 ROUTE 1 0.000 R2C2A.OFX0 to R2C2A.FXB mux_90_Mux_2_1_f5b FXTOOFX_DE --- 0.241 R2C2A.FXB to R2C2A.OFX1 SLICE_44 ROUTE 12 1.845 R2C2A.OFX1 to R5C6A.C0 code_data_2 CTOF_DEL --- 0.495 R5C6A.C0 to R5C6A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.544 R5C6A.F0 to R5C8A.B0 mem_data_0 CTOF_DEL --- 0.495 R5C8A.B0 to R5C8A.F0 alu_impl/SLICE_87 ROUTE 2 0.976 R5C8A.F0 to R5C8C.A1 n52_adj_27 CTOF_DEL --- 0.495 R5C8C.A1 to R5C8C.F1 SLICE_97 ROUTE 2 0.635 R5C8C.F1 to R5C8D.D1 alu_impl/alu_impl/alu_lo/n1896 CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 20.220 (33.9% logic, 66.1% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C5B.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 7.391ns (weighted slack = 11.086ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i4 (from CLK_c -) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 20.220ns (33.9% logic, 66.1% route), 14 logic levels. Constraint Details: 20.220ns physical path delay SLICE_6 to SLICE_16 meets 27.777ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 27.611ns) by 7.391ns Physical Path Details: Data path SLICE_6 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5B.CLK to R4C5B.Q1 SLICE_6 (from CLK_c) ROUTE 67 2.299 R4C5B.Q1 to R2C2A.A0 r_addr_3 CTOOFX_DEL --- 0.721 R2C2A.A0 to R2C2A.OFX0 SLICE_44 ROUTE 1 0.000 R2C2A.OFX0 to R2C2A.FXB mux_90_Mux_2_1_f5b FXTOOFX_DE --- 0.241 R2C2A.FXB to R2C2A.OFX1 SLICE_44 ROUTE 12 1.845 R2C2A.OFX1 to R5C6A.C0 code_data_2 CTOF_DEL --- 0.495 R5C6A.C0 to R5C6A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.544 R5C6A.F0 to R5C8A.B0 mem_data_0 CTOF_DEL --- 0.495 R5C8A.B0 to R5C8A.F0 alu_impl/SLICE_87 ROUTE 2 0.976 R5C8A.F0 to R5C8C.A1 n52_adj_27 CTOF_DEL --- 0.495 R5C8C.A1 to R5C8C.F1 SLICE_97 ROUTE 2 0.635 R5C8C.F1 to R5C8D.D1 alu_impl/alu_impl/alu_lo/n1896 CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 20.220 (33.9% logic, 66.1% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C5B.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 7.391ns (weighted slack = 11.086ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i4 (from CLK_c -) Destination: FF Data in flags_i1 (to CLK_c +) Delay: 20.220ns (33.9% logic, 66.1% route), 14 logic levels. Constraint Details: 20.220ns physical path delay SLICE_6 to SLICE_16 meets 27.777ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 27.611ns) by 7.391ns Physical Path Details: Data path SLICE_6 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5B.CLK to R4C5B.Q1 SLICE_6 (from CLK_c) ROUTE 67 2.299 R4C5B.Q1 to R2C2B.A0 r_addr_3 CTOOFX_DEL --- 0.721 R2C2B.A0 to R2C2B.OFX0 SLICE_43 ROUTE 1 0.000 R2C2B.OFX0 to R2C2A.FXA mux_90_Mux_2_0_f5a FXTOOFX_DE --- 0.241 R2C2A.FXA to R2C2A.OFX1 SLICE_44 ROUTE 12 1.845 R2C2A.OFX1 to R5C6A.C0 code_data_2 CTOF_DEL --- 0.495 R5C6A.C0 to R5C6A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.544 R5C6A.F0 to R5C8A.B0 mem_data_0 CTOF_DEL --- 0.495 R5C8A.B0 to R5C8A.F0 alu_impl/SLICE_87 ROUTE 2 0.976 R5C8A.F0 to R5C8C.A1 n52_adj_27 CTOF_DEL --- 0.495 R5C8C.A1 to R5C8C.F1 SLICE_97 ROUTE 2 0.635 R5C8C.F1 to R5C8D.D1 alu_impl/alu_impl/alu_lo/n1896 CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 alu_impl/alu_impl/alu_lo/SLICE_88 ROUTE 2 0.753 R5C8D.F1 to R4C8B.C1 n1958 CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 3 0.979 R4C8B.F1 to R5C7C.D1 n1902 CTOF_DEL --- 0.495 R5C7C.D1 to R5C7C.F1 alu_impl/alu_impl/SLICE_91 ROUTE 2 0.967 R5C7C.F1 to R4C6B.D1 alu_impl/alu_impl/alu_hi/n1980 CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.445 R4C6B.F1 to R4C6B.C0 n1998 CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 alu_impl/alu_impl/alu_hi/SLICE_92 ROUTE 2 0.758 R4C6B.F0 to R3C6B.C1 n1986 CTOF_DEL --- 0.495 R3C6B.C1 to R3C6B.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 1.088 R3C6B.F1 to R4C5D.C0 F_7 CTOF_DEL --- 0.495 R4C5D.C0 to R4C5D.F0 SLICE_25 ROUTE 1 1.072 R4C5D.F0 to R4C8C.D0 alu_impl/n3427 CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_16 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 Z_out (to CLK_c) -------- 20.220 (33.9% logic, 66.1% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C5B.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 16 3.438 12.PADDI to R4C8C.CLK CLK_c -------- 3.438 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "CLK" 36.000000 MHz ; | 36.000 MHz| 37.216 MHz| 11 | | | MULTICYCLE FROM GROUP "code" TO GROUP | | | "akku" 1.500000 X ; | 27.777 ns| 21.057 ns| 14 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 3 clocks: Clock Domain: WE_mem Source: SLICE_70.F0 Loads: 4 No transfer within this clock domain is found Data transfers from: Clock Domain: CLK_c Source: CLK.PAD Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ; Transfers: 14 Clock Domain: CLK_c Source: CLK.PAD Loads: 16 Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ; Covered under: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.500000 X ; Data transfers from: Clock Domain: WE_mem Source: SLICE_70.F0 Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ; Transfers: 8 Clock Domain: O_STB_c Source: SLICE_69.F0 Loads: 8 No transfer within this clock domain is found Data transfers from: Clock Domain: CLK_c Source: CLK.PAD Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ; Transfers: 7 Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 31851 paths, 8 nets, and 891 connections (97.4% coverage)