Place & Route TRACE Report
Loading design for application trce from file qfn32samples_mcpu3.ncd.
Design name: mcpu
NCD version: 3.2
Vendor: LATTICE
Device: LCMXO2-256HC
Package: QFN32
Performance: 4
Loading device for application trce from file 'xo2c256.nph' in environment: Y:/Program_Files/lscc/diamond/1.4/ispfpga.
Package Status: Advanced Version 1.34
Performance Hardware Data Status: Final) Version 22.4
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond_1.4_Production (87)
Tue Jun 26 12:44:04 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_mcpu3.twr qfn32samples_mcpu3.ncd qfn32samples_mcpu3.prf
Design file: qfn32samples_mcpu3.ncd
Preference file: qfn32samples_mcpu3.prf
Device,speed: LCMXO2-256HC,4
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY PORT "CLK" 36.000000 MHz (0 errors) 1494 items scored, 0 timing errors detected.
Report: 40.182MHz is the maximum frequency for this preference.
MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.000000 X (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY PORT "CLK" 36.000000 MHz ;
1494 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 2.890ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 13.907ns (45.6% logic, 54.4% route), 11 logic levels.
Constraint Details:
13.907ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets
27.777ns delay constraint less
10.814ns skew and
0.166ns DIN_SET requirement (totaling 16.797ns) by 2.890ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R5C5A.WCK to R5C5A.F0 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 2 1.740 R5C5A.F0 to R3C4D.B0 mem_data_0
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.632 R2C4A.F1 to R3C4A.D1 F_7
CTOF_DEL --- 0.495 R3C4A.D1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
13.907 (45.6% logic, 54.4% route), 11 logic levels.
Clock Skew Details:
Source Clock Path CLK to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 1.653 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.495 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 1.004 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.721 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 1.977 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.495 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 1.413 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.495 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.976 R5C4D.F1 to R5C4B.A1 n9
CTOF_DEL --- 0.495 R5C4B.A1 to R5C4B.F1 SLICE_73
ROUTE 4 0.638 R5C4B.F1 to R5C5A.WCK WE_mem
--------
15.624 (29.0% logic, 71.0% route), 7 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
4.810 (28.5% logic, 71.5% route), 1 logic levels.
Passed: The following path meets requirements by 3.827ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 12.970ns (45.1% logic, 54.9% route), 10 logic levels.
Constraint Details:
12.970ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets
27.777ns delay constraint less
10.814ns skew and
0.166ns DIN_SET requirement (totaling 16.797ns) by 3.827ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R5C5A.WCK to R5C5A.F1 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 2 1.362 R5C5A.F1 to R4C4A.D0 mem_data_1
CTOF_DEL --- 0.495 R4C4A.D0 to R4C4A.F0 alu_impl/alu_impl/alu_lo/SLICE_100
ROUTE 2 1.015 R4C4A.F0 to R3C4B.B1 n6_adj_28
CTOF_DEL --- 0.495 R3C4B.B1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.632 R2C4A.F1 to R3C4A.D1 F_7
CTOF_DEL --- 0.495 R3C4A.D1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
12.970 (45.1% logic, 54.9% route), 10 logic levels.
Clock Skew Details:
Source Clock Path CLK to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 1.653 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.495 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 1.004 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.721 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 1.977 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.495 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 1.413 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.495 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.976 R5C4D.F1 to R5C4B.A1 n9
CTOF_DEL --- 0.495 R5C4B.A1 to R5C4B.F1 SLICE_73
ROUTE 4 0.638 R5C4B.F1 to R5C5A.WCK WE_mem
--------
15.624 (29.0% logic, 71.0% route), 7 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
4.810 (28.5% logic, 71.5% route), 1 logic levels.
Passed: The following path meets requirements by 3.877ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 12.920ns (45.3% logic, 54.7% route), 10 logic levels.
Constraint Details:
12.920ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets
27.777ns delay constraint less
10.814ns skew and
0.166ns DIN_SET requirement (totaling 16.797ns) by 3.877ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R5C5A.WCK to R5C5A.F0 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 2 1.343 R5C5A.F0 to R3C4B.B0 mem_data_0
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 3 0.984 R3C4B.F0 to R3C4B.A1 n1099
CTOF_DEL --- 0.495 R3C4B.A1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.632 R2C4A.F1 to R3C4A.D1 F_7
CTOF_DEL --- 0.495 R3C4A.D1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
12.920 (45.3% logic, 54.7% route), 10 logic levels.
Clock Skew Details:
Source Clock Path CLK to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 1.653 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.495 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 1.004 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.721 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 1.977 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.495 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 1.413 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.495 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.976 R5C4D.F1 to R5C4B.A1 n9
CTOF_DEL --- 0.495 R5C4B.A1 to R5C4B.F1 SLICE_73
ROUTE 4 0.638 R5C4B.F1 to R5C5A.WCK WE_mem
--------
15.624 (29.0% logic, 71.0% route), 7 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
4.810 (28.5% logic, 71.5% route), 1 logic levels.
Passed: The following path meets requirements by 3.901ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 12.896ns (45.4% logic, 54.6% route), 10 logic levels.
Constraint Details:
12.896ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets
27.777ns delay constraint less
10.814ns skew and
0.166ns DIN_SET requirement (totaling 16.797ns) by 3.901ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R5C5A.WCK to R5C5A.F0 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 2 1.740 R5C5A.F0 to R3C4D.B0 mem_data_0
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.632 R4C3A.F0 to R3C3C.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3C.D1 to R3C3C.F1 SLICE_86
ROUTE 1 0.436 R3C3C.F1 to R3C3C.C0 n1986
CTOF_DEL --- 0.495 R3C3C.C0 to R3C3C.F0 SLICE_86
ROUTE 2 0.993 R3C3C.F0 to R3C4A.A1 F_5
CTOF_DEL --- 0.495 R3C4A.A1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
12.896 (45.4% logic, 54.6% route), 10 logic levels.
Clock Skew Details:
Source Clock Path CLK to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 1.653 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.495 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 1.004 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.721 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 1.977 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.495 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 1.413 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.495 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.976 R5C4D.F1 to R5C4B.A1 n9
CTOF_DEL --- 0.495 R5C4B.A1 to R5C4B.F1 SLICE_73
ROUTE 4 0.638 R5C4B.F1 to R5C5A.WCK WE_mem
--------
15.624 (29.0% logic, 71.0% route), 7 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
4.810 (28.5% logic, 71.5% route), 1 logic levels.
Passed: The following path meets requirements by 4.059ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i7 (to CLK_c +)
Delay: 12.738ns (45.9% logic, 54.1% route), 10 logic levels.
Constraint Details:
12.738ns physical path delay sram_impl/mem1/SLICE_8 to alu_impl_I/alu_impl/alu_hi/SLICE_14 meets
27.777ns delay constraint less
10.814ns skew and
0.166ns DIN_SET requirement (totaling 16.797ns) by 4.059ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to alu_impl_I/alu_impl/alu_hi/SLICE_14:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R5C5A.WCK to R5C5A.F0 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 2 1.740 R5C5A.F0 to R3C4D.B0 mem_data_0
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.702 R2C4A.F1 to R2C4A.B0 F_7
CTOF_DEL --- 0.495 R2C4A.B0 to R2C4A.F0 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 1 0.000 R2C4A.F0 to R2C4A.DI0 alu_impl_I/alu_impl/alu_hi/n1198 (to CLK_c)
--------
12.738 (45.9% logic, 54.1% route), 10 logic levels.
Clock Skew Details:
Source Clock Path CLK to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 1.653 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.495 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 1.004 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.721 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 1.977 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.495 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 1.413 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.495 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.976 R5C4D.F1 to R5C4B.A1 n9
CTOF_DEL --- 0.495 R5C4B.A1 to R5C4B.F1 SLICE_73
ROUTE 4 0.638 R5C4B.F1 to R5C5A.WCK WE_mem
--------
15.624 (29.0% logic, 71.0% route), 7 logic levels.
Destination Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_14:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R2C4A.CLK CLK_c
--------
4.810 (28.5% logic, 71.5% route), 1 logic levels.
Passed: The following path meets requirements by 4.103ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 12.694ns (46.1% logic, 53.9% route), 10 logic levels.
Constraint Details:
12.694ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets
27.777ns delay constraint less
10.814ns skew and
0.166ns DIN_SET requirement (totaling 16.797ns) by 4.103ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R5C5A.WCK to R5C5A.F1 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 2 1.343 R5C5A.F1 to R4C4B.B0 mem_data_1
CTOF_DEL --- 0.495 R4C4B.B0 to R4C4B.F0 alu_impl/alu_impl/SLICE_97
ROUTE 2 0.758 R4C4B.F0 to R3C4B.C1 n62_adj_30
CTOF_DEL --- 0.495 R3C4B.C1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.632 R2C4A.F1 to R3C4A.D1 F_7
CTOF_DEL --- 0.495 R3C4A.D1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
12.694 (46.1% logic, 53.9% route), 10 logic levels.
Clock Skew Details:
Source Clock Path CLK to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 1.653 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.495 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 1.004 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.721 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 1.977 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.495 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 1.413 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.495 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.976 R5C4D.F1 to R5C4B.A1 n9
CTOF_DEL --- 0.495 R5C4B.A1 to R5C4B.F1 SLICE_73
ROUTE 4 0.638 R5C4B.F1 to R5C5A.WCK WE_mem
--------
15.624 (29.0% logic, 71.0% route), 7 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
4.810 (28.5% logic, 71.5% route), 1 logic levels.
Passed: The following path meets requirements by 4.329ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 12.468ns (43.0% logic, 57.0% route), 9 logic levels.
Constraint Details:
12.468ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets
27.777ns delay constraint less
10.814ns skew and
0.166ns DIN_SET requirement (totaling 16.797ns) by 4.329ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R5C5A.WCK to R5C5A.F0 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 2 1.740 R5C5A.F0 to R3C4D.B0 mem_data_0
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3B.D1 n1891
CTOF_DEL --- 0.495 R4C3B.D1 to R4C3B.F1 alu_impl/alu_impl/SLICE_66
ROUTE 1 0.315 R4C3B.F1 to R4C3D.D0 n1968
CTOF_DEL --- 0.495 R4C3D.D0 to R4C3D.F0 SLICE_87
ROUTE 2 1.590 R4C3D.F0 to R3C5D.C0 F_4
CTOF_DEL --- 0.495 R3C5D.C0 to R3C5D.F0 SLICE_98
ROUTE 1 0.967 R3C5D.F0 to R3C5A.A0 alu_impl/n3408
CTOF_DEL --- 0.495 R3C5A.A0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
12.468 (43.0% logic, 57.0% route), 9 logic levels.
Clock Skew Details:
Source Clock Path CLK to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 1.653 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.495 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 1.004 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.721 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 1.977 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.495 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 1.413 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.495 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.976 R5C4D.F1 to R5C4B.A1 n9
CTOF_DEL --- 0.495 R5C4B.A1 to R5C4B.F1 SLICE_73
ROUTE 4 0.638 R5C4B.F1 to R5C5A.WCK WE_mem
--------
15.624 (29.0% logic, 71.0% route), 7 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
4.810 (28.5% logic, 71.5% route), 1 logic levels.
Passed: The following path meets requirements by 4.656ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM1 (from WE_mem +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 12.141ns (44.1% logic, 55.9% route), 9 logic levels.
Constraint Details:
12.141ns physical path delay sram_impl/mem1/SLICE_9 to SLICE_16 meets
27.777ns delay constraint less
10.814ns skew and
0.166ns DIN_SET requirement (totaling 16.797ns) by 4.656ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_9 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R5C5B.WCK to R5C5B.F1 sram_impl/mem1/SLICE_9 (from WE_mem)
ROUTE 2 1.010 R5C5B.F1 to R5C4A.B0 mem_data_3
CTOF_DEL --- 0.495 R5C4A.B0 to R5C4A.F0 alu_impl/alu_impl/alu_lo/SLICE_88
ROUTE 2 0.635 R5C4A.F0 to R5C4A.D1 alu_impl/alu_impl/n3779
CTOF_DEL --- 0.495 R5C4A.D1 to R5C4A.F1 alu_impl/alu_impl/alu_lo/SLICE_88
ROUTE 2 1.817 R5C4A.F1 to R4C3A.A0 n1102
CTOF_DEL --- 0.495 R4C3A.A0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.632 R2C4A.F1 to R3C4A.D1 F_7
CTOF_DEL --- 0.495 R3C4A.D1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
12.141 (44.1% logic, 55.9% route), 9 logic levels.
Clock Skew Details:
Source Clock Path CLK to sram_impl/mem1/SLICE_9:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 1.653 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.495 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 1.004 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.721 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 1.977 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.495 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 1.413 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.495 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.976 R5C4D.F1 to R5C4B.A1 n9
CTOF_DEL --- 0.495 R5C4B.A1 to R5C4B.F1 SLICE_73
ROUTE 4 0.638 R5C4B.F1 to R5C5B.WCK WE_mem
--------
15.624 (29.0% logic, 71.0% route), 7 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
4.810 (28.5% logic, 71.5% route), 1 logic levels.
Passed: The following path meets requirements by 4.676ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in alu_impl_I/alu_impl/alu_hi/akku_i5 (to CLK_c +)
Delay: 12.121ns (44.2% logic, 55.8% route), 9 logic levels.
Constraint Details:
12.121ns physical path delay sram_impl/mem1/SLICE_8 to alu_impl_I/alu_impl/alu_hi/SLICE_12 meets
27.777ns delay constraint less
10.814ns skew and
0.166ns DIN_SET requirement (totaling 16.797ns) by 4.676ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to alu_impl_I/alu_impl/alu_hi/SLICE_12:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R5C5A.WCK to R5C5A.F0 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 2 1.740 R5C5A.F0 to R3C4D.B0 mem_data_0
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.632 R4C3A.F0 to R3C3C.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3C.D1 to R3C3C.F1 SLICE_86
ROUTE 1 0.436 R3C3C.F1 to R3C3C.C0 n1986
CTOF_DEL --- 0.495 R3C3C.C0 to R3C3C.F0 SLICE_86
ROUTE 2 1.457 R3C3C.F0 to R4C5D.B1 F_5
CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 alu_impl_I/alu_impl/alu_hi/SLICE_12
ROUTE 1 0.000 R4C5D.F1 to R4C5D.DI1 alu_impl_I/alu_impl/alu_hi/n3826 (to CLK_c)
--------
12.121 (44.2% logic, 55.8% route), 9 logic levels.
Clock Skew Details:
Source Clock Path CLK to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 1.653 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.495 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 1.004 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.721 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 1.977 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.495 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 1.413 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.495 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.976 R5C4D.F1 to R5C4B.A1 n9
CTOF_DEL --- 0.495 R5C4B.A1 to R5C4B.F1 SLICE_73
ROUTE 4 0.638 R5C4B.F1 to R5C5A.WCK WE_mem
--------
15.624 (29.0% logic, 71.0% route), 7 logic levels.
Destination Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_12:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R4C5D.CLK CLK_c
--------
4.810 (28.5% logic, 71.5% route), 1 logic levels.
Passed: The following path meets requirements by 4.683ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sram_impl/mem1/RAM0 (from WE_mem +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 12.114ns (40.1% logic, 59.9% route), 8 logic levels.
Constraint Details:
12.114ns physical path delay sram_impl/mem1/SLICE_8 to SLICE_16 meets
27.777ns delay constraint less
10.814ns skew and
0.166ns DIN_SET requirement (totaling 16.797ns) by 4.683ns
Physical Path Details:
Data path sram_impl/mem1/SLICE_8 to SLICE_16:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 1.398 R5C5A.WCK to R5C5A.F0 sram_impl/mem1/SLICE_8 (from WE_mem)
ROUTE 2 1.740 R5C5A.F0 to R3C4D.B0 mem_data_0
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 1.013 R4C4D.F1 to R4C4D.B0 n1891
CTOF_DEL --- 0.495 R4C4D.B0 to R4C4D.F0 SLICE_76
ROUTE 2 1.917 R4C4D.F0 to R3C4A.C1 F_3
CTOF_DEL --- 0.495 R3C4A.C1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
12.114 (40.1% logic, 59.9% route), 8 logic levels.
Clock Skew Details:
Source Clock Path CLK to sram_impl/mem1/SLICE_8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 1.653 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.495 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 1.004 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.721 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 1.977 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.495 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 1.413 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.495 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.976 R5C4D.F1 to R5C4B.A1 n9
CTOF_DEL --- 0.495 R5C4B.A1 to R5C4B.F1 SLICE_73
ROUTE 4 0.638 R5C4B.F1 to R5C5A.WCK WE_mem
--------
15.624 (29.0% logic, 71.0% route), 7 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.372 12.PAD to 12.PADDI CLK
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
4.810 (28.5% logic, 71.5% route), 1 logic levels.
Report: 40.182MHz is the maximum frequency for this preference.
================================================================================
Preference: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.000000 X ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 9.539ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i2 (from CLK_c +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 18.072ns (38.0% logic, 62.0% route), 14 logic levels.
Constraint Details:
18.072ns physical path delay SLICE_20 to SLICE_16 meets
27.777ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 27.611ns) by 9.539ns
Physical Path Details:
Data path SLICE_20 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8D.CLK to R3C8D.Q0 SLICE_20 (from CLK_c)
ROUTE 68 2.094 R3C8D.Q0 to R5C7D.D1 pc_2
CTOOFX_DEL --- 0.721 R5C7D.D1 to R5C7D.OFX0 SLICE_46
ROUTE 1 0.000 R5C7D.OFX0 to R5C7C.FXA mux_89_Mux_2_0_f5a
FXTOOFX_DE --- 0.241 R5C7C.FXA to R5C7C.OFX1 SLICE_47
ROUTE 12 1.560 R5C7C.OFX1 to R5C5A.C0 code_data_2
CTOF_DEL --- 0.495 R5C5A.C0 to R5C5A.F0 sram_impl/mem1/SLICE_8
ROUTE 2 1.740 R5C5A.F0 to R3C4D.B0 mem_data_0
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.632 R2C4A.F1 to R3C4A.D1 F_7
CTOF_DEL --- 0.495 R3C4A.D1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
18.072 (38.0% logic, 62.0% route), 14 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C8D.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.539ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i2 (from CLK_c +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 18.072ns (38.0% logic, 62.0% route), 14 logic levels.
Constraint Details:
18.072ns physical path delay SLICE_20 to SLICE_16 meets
27.777ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 27.611ns) by 9.539ns
Physical Path Details:
Data path SLICE_20 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8D.CLK to R3C8D.Q0 SLICE_20 (from CLK_c)
ROUTE 68 2.094 R3C8D.Q0 to R5C7D.D0 pc_2
CTOOFX_DEL --- 0.721 R5C7D.D0 to R5C7D.OFX0 SLICE_46
ROUTE 1 0.000 R5C7D.OFX0 to R5C7C.FXA mux_89_Mux_2_0_f5a
FXTOOFX_DE --- 0.241 R5C7C.FXA to R5C7C.OFX1 SLICE_47
ROUTE 12 1.560 R5C7C.OFX1 to R5C5A.C0 code_data_2
CTOF_DEL --- 0.495 R5C5A.C0 to R5C5A.F0 sram_impl/mem1/SLICE_8
ROUTE 2 1.740 R5C5A.F0 to R3C4D.B0 mem_data_0
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.632 R2C4A.F1 to R3C4A.D1 F_7
CTOF_DEL --- 0.495 R3C4A.D1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
18.072 (38.0% logic, 62.0% route), 14 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C8D.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.545ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from CLK_c +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 18.066ns (38.0% logic, 62.0% route), 14 logic levels.
Constraint Details:
18.066ns physical path delay SLICE_19 to SLICE_16 meets
27.777ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 27.611ns) by 9.545ns
Physical Path Details:
Data path SLICE_19 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_19 (from CLK_c)
ROUTE 29 1.902 R3C8B.Q0 to R4C7A.A1 pc_0
CTOOFX_DEL --- 0.721 R4C7A.A1 to R4C7A.OFX0 alu_impl_I/i2727/SLICE_29
ROUTE 1 0.000 R4C7A.OFX0 to R4C7A.FXB alu_impl_I/n3426
FXTOOFX_DE --- 0.241 R4C7A.FXB to R4C7A.OFX1 alu_impl_I/i2727/SLICE_29
ROUTE 17 2.339 R4C7A.OFX1 to R4C3C.B0 code_data_7
CTOF_DEL --- 0.495 R4C3C.B0 to R4C3C.F0 SLICE_75
ROUTE 8 1.147 R4C3C.F0 to R3C4D.C0 FS_2
CTOF_DEL --- 0.495 R3C4D.C0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.632 R2C4A.F1 to R3C4A.D1 F_7
CTOF_DEL --- 0.495 R3C4A.D1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
18.066 (38.0% logic, 62.0% route), 14 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C8B.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.545ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from CLK_c +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 18.066ns (38.0% logic, 62.0% route), 14 logic levels.
Constraint Details:
18.066ns physical path delay SLICE_19 to SLICE_16 meets
27.777ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 27.611ns) by 9.545ns
Physical Path Details:
Data path SLICE_19 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 SLICE_19 (from CLK_c)
ROUTE 29 1.902 R3C8B.Q0 to R4C7A.A0 pc_0
CTOOFX_DEL --- 0.721 R4C7A.A0 to R4C7A.OFX0 alu_impl_I/i2727/SLICE_29
ROUTE 1 0.000 R4C7A.OFX0 to R4C7A.FXB alu_impl_I/n3426
FXTOOFX_DE --- 0.241 R4C7A.FXB to R4C7A.OFX1 alu_impl_I/i2727/SLICE_29
ROUTE 17 2.339 R4C7A.OFX1 to R4C3C.B0 code_data_7
CTOF_DEL --- 0.495 R4C3C.B0 to R4C3C.F0 SLICE_75
ROUTE 8 1.147 R4C3C.F0 to R3C4D.C0 FS_2
CTOF_DEL --- 0.495 R3C4D.C0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.632 R2C4A.F1 to R3C4A.D1 F_7
CTOF_DEL --- 0.495 R3C4A.D1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
18.066 (38.0% logic, 62.0% route), 14 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C8B.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.667ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i2 (from CLK_c +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 17.944ns (38.2% logic, 61.8% route), 14 logic levels.
Constraint Details:
17.944ns physical path delay SLICE_20 to SLICE_16 meets
27.777ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 27.611ns) by 9.667ns
Physical Path Details:
Data path SLICE_20 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8D.CLK to R3C8D.Q0 SLICE_20 (from CLK_c)
ROUTE 68 1.966 R3C8D.Q0 to R5C7C.A1 pc_2
CTOOFX_DEL --- 0.721 R5C7C.A1 to R5C7C.OFX0 SLICE_47
ROUTE 1 0.000 R5C7C.OFX0 to R5C7C.FXB mux_89_Mux_2_1_f5b
FXTOOFX_DE --- 0.241 R5C7C.FXB to R5C7C.OFX1 SLICE_47
ROUTE 12 1.560 R5C7C.OFX1 to R5C5A.C0 code_data_2
CTOF_DEL --- 0.495 R5C5A.C0 to R5C5A.F0 sram_impl/mem1/SLICE_8
ROUTE 2 1.740 R5C5A.F0 to R3C4D.B0 mem_data_0
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.632 R2C4A.F1 to R3C4A.D1 F_7
CTOF_DEL --- 0.495 R3C4A.D1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
17.944 (38.2% logic, 61.8% route), 14 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C8D.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.667ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i2 (from CLK_c +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 17.944ns (38.2% logic, 61.8% route), 14 logic levels.
Constraint Details:
17.944ns physical path delay SLICE_20 to SLICE_16 meets
27.777ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 27.611ns) by 9.667ns
Physical Path Details:
Data path SLICE_20 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8D.CLK to R3C8D.Q0 SLICE_20 (from CLK_c)
ROUTE 68 1.966 R3C8D.Q0 to R5C7C.A0 pc_2
CTOOFX_DEL --- 0.721 R5C7C.A0 to R5C7C.OFX0 SLICE_47
ROUTE 1 0.000 R5C7C.OFX0 to R5C7C.FXB mux_89_Mux_2_1_f5b
FXTOOFX_DE --- 0.241 R5C7C.FXB to R5C7C.OFX1 SLICE_47
ROUTE 12 1.560 R5C7C.OFX1 to R5C5A.C0 code_data_2
CTOF_DEL --- 0.495 R5C5A.C0 to R5C5A.F0 sram_impl/mem1/SLICE_8
ROUTE 2 1.740 R5C5A.F0 to R3C4D.B0 mem_data_0
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.632 R2C4A.F1 to R3C4A.D1 F_7
CTOF_DEL --- 0.495 R3C4A.D1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
17.944 (38.2% logic, 61.8% route), 14 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C8D.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.732ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i1 (from CLK_c +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 17.879ns (38.4% logic, 61.6% route), 14 logic levels.
Constraint Details:
17.879ns physical path delay SLICE_19 to SLICE_16 meets
27.777ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 27.611ns) by 9.732ns
Physical Path Details:
Data path SLICE_19 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_19 (from CLK_c)
ROUTE 67 1.715 R3C8B.Q1 to R4C7A.C1 pc_1
CTOOFX_DEL --- 0.721 R4C7A.C1 to R4C7A.OFX0 alu_impl_I/i2727/SLICE_29
ROUTE 1 0.000 R4C7A.OFX0 to R4C7A.FXB alu_impl_I/n3426
FXTOOFX_DE --- 0.241 R4C7A.FXB to R4C7A.OFX1 alu_impl_I/i2727/SLICE_29
ROUTE 17 2.339 R4C7A.OFX1 to R4C3C.B0 code_data_7
CTOF_DEL --- 0.495 R4C3C.B0 to R4C3C.F0 SLICE_75
ROUTE 8 1.147 R4C3C.F0 to R3C4D.C0 FS_2
CTOF_DEL --- 0.495 R3C4D.C0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.632 R2C4A.F1 to R3C4A.D1 F_7
CTOF_DEL --- 0.495 R3C4A.D1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
17.879 (38.4% logic, 61.6% route), 14 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C8B.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.732ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i1 (from CLK_c +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 17.879ns (38.4% logic, 61.6% route), 14 logic levels.
Constraint Details:
17.879ns physical path delay SLICE_19 to SLICE_16 meets
27.777ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 27.611ns) by 9.732ns
Physical Path Details:
Data path SLICE_19 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q1 SLICE_19 (from CLK_c)
ROUTE 67 1.715 R3C8B.Q1 to R4C7A.C0 pc_1
CTOOFX_DEL --- 0.721 R4C7A.C0 to R4C7A.OFX0 alu_impl_I/i2727/SLICE_29
ROUTE 1 0.000 R4C7A.OFX0 to R4C7A.FXB alu_impl_I/n3426
FXTOOFX_DE --- 0.241 R4C7A.FXB to R4C7A.OFX1 alu_impl_I/i2727/SLICE_29
ROUTE 17 2.339 R4C7A.OFX1 to R4C3C.B0 code_data_7
CTOF_DEL --- 0.495 R4C3C.B0 to R4C3C.F0 SLICE_75
ROUTE 8 1.147 R4C3C.F0 to R3C4D.C0 FS_2
CTOF_DEL --- 0.495 R3C4D.C0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.632 R2C4A.F1 to R3C4A.D1 F_7
CTOF_DEL --- 0.495 R3C4A.D1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
17.879 (38.4% logic, 61.6% route), 14 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C8B.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.874ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from CLK_c +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 17.737ns (38.7% logic, 61.3% route), 14 logic levels.
Constraint Details:
17.737ns physical path delay SLICE_20 to SLICE_16 meets
27.777ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 27.611ns) by 9.874ns
Physical Path Details:
Data path SLICE_20 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8D.CLK to R3C8D.Q1 SLICE_20 (from CLK_c)
ROUTE 68 1.394 R3C8D.Q1 to R5C8C.A0 pc_3
CTOOFX_DEL --- 0.721 R5C8C.A0 to R5C8C.OFX0 SLICE_39
ROUTE 1 0.000 R5C8C.OFX0 to R5C8C.FXB mux_89_Mux_1_1_f5b
FXTOOFX_DE --- 0.241 R5C8C.FXB to R5C8C.OFX1 SLICE_39
ROUTE 12 1.925 R5C8C.OFX1 to R5C5A.B0 code_data_1
CTOF_DEL --- 0.495 R5C5A.B0 to R5C5A.F0 sram_impl/mem1/SLICE_8
ROUTE 2 1.740 R5C5A.F0 to R3C4D.B0 mem_data_0
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.632 R2C4A.F1 to R3C4A.D1 F_7
CTOF_DEL --- 0.495 R3C4A.D1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
17.737 (38.7% logic, 61.3% route), 14 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C8D.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.874ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from CLK_c +)
Destination: FF Data in flags_i1 (to CLK_c +)
Delay: 17.737ns (38.7% logic, 61.3% route), 14 logic levels.
Constraint Details:
17.737ns physical path delay SLICE_20 to SLICE_16 meets
27.777ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 27.611ns) by 9.874ns
Physical Path Details:
Data path SLICE_20 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C8D.CLK to R3C8D.Q1 SLICE_20 (from CLK_c)
ROUTE 68 1.394 R3C8D.Q1 to R5C8C.A1 pc_3
CTOOFX_DEL --- 0.721 R5C8C.A1 to R5C8C.OFX0 SLICE_39
ROUTE 1 0.000 R5C8C.OFX0 to R5C8C.FXB mux_89_Mux_1_1_f5b
FXTOOFX_DE --- 0.241 R5C8C.FXB to R5C8C.OFX1 SLICE_39
ROUTE 12 1.925 R5C8C.OFX1 to R5C5A.B0 code_data_1
CTOF_DEL --- 0.495 R5C5A.B0 to R5C5A.F0 sram_impl/mem1/SLICE_8
ROUTE 2 1.740 R5C5A.F0 to R3C4D.B0 mem_data_0
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 3 0.453 R3C4D.F0 to R3C4D.C1 n52_adj_29
CTOF_DEL --- 0.495 R3C4D.C1 to R3C4D.F1 alu_impl/alu_impl/alu_lo/SLICE_89
ROUTE 1 0.626 R3C4D.F1 to R3C4B.D1 alu_impl/alu_impl/alu_lo/n1885
CTOF_DEL --- 0.495 R3C4B.D1 to R3C4B.F1 alu_impl/alu_impl/alu_lo/SLICE_90
ROUTE 2 0.758 R3C4B.F1 to R4C4D.C1 n3395
CTOF_DEL --- 0.495 R4C4D.C1 to R4C4D.F1 SLICE_76
ROUTE 3 0.661 R4C4D.F1 to R4C3A.D0 n1891
CTOF_DEL --- 0.495 R4C3A.D0 to R4C3A.F0 alu_impl/alu_impl/alu_hi/SLICE_92
ROUTE 2 0.654 R4C3A.F0 to R3C3D.D1 alu_impl/alu_impl/alu_hi/n1970
CTOF_DEL --- 0.495 R3C3D.D1 to R3C3D.F1 SLICE_85
ROUTE 2 0.654 R3C3D.F1 to R3C4A.D0 n1988
CTOF_DEL --- 0.495 R3C4A.D0 to R3C4A.F0 alu_impl/SLICE_99
ROUTE 2 0.637 R3C4A.F0 to R2C4A.D1 n1976
CTOF_DEL --- 0.495 R2C4A.D1 to R2C4A.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14
ROUTE 2 0.632 R2C4A.F1 to R3C4A.D1 F_7
CTOF_DEL --- 0.495 R3C4A.D1 to R3C4A.F1 alu_impl/SLICE_99
ROUTE 1 0.744 R3C4A.F1 to R3C5A.C0 alu_impl/n3414
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_16
ROUTE 1 0.000 R3C5A.F0 to R3C5A.DI0 Z_out (to CLK_c)
--------
17.737 (38.7% logic, 61.3% route), 14 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C8D.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 13 3.438 12.PADDI to R3C5A.CLK CLK_c
--------
3.438 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "CLK" 36.000000 MHz ; | 36.000 MHz| 40.182 MHz| 11
| | |
MULTICYCLE FROM GROUP "code" TO GROUP | | |
"akku" 1.000000 X ; | 27.777 ns| 18.238 ns| 14
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 3 clocks:
Clock Domain: O_STB_c Source: SLICE_70.F0 Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: CLK_c Source: CLK.PAD
Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ; Transfers: 8
Clock Domain: CLK_c Source: CLK.PAD Loads: 13
Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ;
Covered under: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.000000 X ;
Data transfers from:
Clock Domain: WE_mem Source: SLICE_73.F1
Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ; Transfers: 8
Clock Domain: WE_mem Source: SLICE_73.F1 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: CLK_c Source: CLK.PAD
Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ; Transfers: 14
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 31153 paths, 8 nets, and 878 connections (97.2% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond_1.4_Production (87)
Tue Jun 26 12:44:07 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_mcpu3.twr qfn32samples_mcpu3.ncd qfn32samples_mcpu3.prf
Design file: qfn32samples_mcpu3.ncd
Preference file: qfn32samples_mcpu3.prf
Device,speed: LCMXO2-256HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY PORT "CLK" 36.000000 MHz (320 errors)
1494 items scored, 320 timing errors detected.
MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.000000 X (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "CLK" 36.000000 MHz ;
1494 items scored, 320 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 3.829ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i3 (from CLK_c +)
Destination: FF Data in r_oport_i3 (to O_STB_c +)
Delay: 0.437ns (30.0% logic, 70.0% route), 1 logic levels.
Constraint Details:
0.437ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_11 to O_PORT_3_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.302ns skew requirement (totaling 4.266ns) by 3.829ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_lo/SLICE_11 to O_PORT_3_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C5C.CLK to R4C5C.Q1 alu_impl_I/alu_impl/alu_lo/SLICE_11 (from CLK_c)
ROUTE 9 0.306 R4C5C.Q1 to IOL_R5B.OPOS akku_3 (to O_STB_c)
--------
0.437 (30.0% logic, 70.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK to alu_impl_I/alu_impl/alu_lo/SLICE_11:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R4C5C.CLK CLK_c
--------
1.623 (27.0% logic, 73.0% route), 1 logic levels.
Destination Clock Path CLK to O_PORT_3_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.151 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 0.591 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.174 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 0.317 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.267 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 0.639 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.174 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 0.463 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.174 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.426 R5C4D.F1 to R5C2D.B0 n9
CTOF_DEL --- 0.174 R5C2D.B0 to R5C2D.F0 SLICE_70
ROUTE 9 0.752 R5C2D.F0 to IOL_R5B.CLK O_STB_c
--------
5.925 (26.2% logic, 73.8% route), 7 logic levels.
Error: The following path exceeds requirements by 3.825ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i5 (from CLK_c +)
Destination: FF Data in r_oport_i5 (to O_STB_c +)
Delay: 0.441ns (29.7% logic, 70.3% route), 1 logic levels.
Constraint Details:
0.441ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_12 to O_PORT_5_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.302ns skew requirement (totaling 4.266ns) by 3.825ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_hi/SLICE_12 to O_PORT_5_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C5D.CLK to R4C5D.Q1 alu_impl_I/alu_impl/alu_hi/SLICE_12 (from CLK_c)
ROUTE 8 0.310 R4C5D.Q1 to IOL_B2C.OPOS akku_5 (to O_STB_c)
--------
0.441 (29.7% logic, 70.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_12:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R4C5D.CLK CLK_c
--------
1.623 (27.0% logic, 73.0% route), 1 logic levels.
Destination Clock Path CLK to O_PORT_5_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.151 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 0.591 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.174 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 0.317 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.267 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 0.639 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.174 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 0.463 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.174 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.426 R5C4D.F1 to R5C2D.B0 n9
CTOF_DEL --- 0.174 R5C2D.B0 to R5C2D.F0 SLICE_70
ROUTE 9 0.752 R5C2D.F0 to IOL_B2C.CLK O_STB_c
--------
5.925 (26.2% logic, 73.8% route), 7 logic levels.
Error: The following path exceeds requirements by 3.751ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i4 (from CLK_c +)
Destination: FF Data in r_oport_i4 (to O_STB_c +)
Delay: 0.515ns (25.4% logic, 74.6% route), 1 logic levels.
Constraint Details:
0.515ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_12 to O_PORT_4_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.302ns skew requirement (totaling 4.266ns) by 3.751ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_hi/SLICE_12 to O_PORT_4_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C5D.CLK to R4C5D.Q0 alu_impl_I/alu_impl/alu_hi/SLICE_12 (from CLK_c)
ROUTE 8 0.384 R4C5D.Q0 to IOL_B2D.OPOS akku_4 (to O_STB_c)
--------
0.515 (25.4% logic, 74.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_12:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R4C5D.CLK CLK_c
--------
1.623 (27.0% logic, 73.0% route), 1 logic levels.
Destination Clock Path CLK to O_PORT_4_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.151 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 0.591 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.174 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 0.317 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.267 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 0.639 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.174 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 0.463 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.174 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.426 R5C4D.F1 to R5C2D.B0 n9
CTOF_DEL --- 0.174 R5C2D.B0 to R5C2D.F0 SLICE_70
ROUTE 9 0.752 R5C2D.F0 to IOL_B2D.CLK O_STB_c
--------
5.925 (26.2% logic, 73.8% route), 7 logic levels.
Error: The following path exceeds requirements by 3.715ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i7 (from CLK_c +)
Destination: FF Data in sram_impl/mem0/RAM1 (to WE_mem +)
FF sram_impl/mem0/RAM1
Delay: 0.454ns (28.9% logic, 71.1% route), 2 logic levels.
Constraint Details:
0.454ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_14 to sram_impl/mem0/SLICE_6 exceeds
0.129ns WD_HLD and
0.000ns delay constraint less
-4.040ns skew requirement (totaling 4.169ns) by 3.715ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_hi/SLICE_14 to sram_impl/mem0/SLICE_6:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R2C4A.CLK to R2C4A.Q0 alu_impl_I/alu_impl/alu_hi/SLICE_14 (from CLK_c)
ROUTE 8 0.323 R2C4A.Q0 to R5C3C.D1 akku_7
ZERO_DEL --- 0.000 R5C3C.D1 to R5C3C.WDO3 sram_impl/mem0/SLICE_4
ROUTE 1 0.000 R5C3C.WDO3 to R5C3B.WD1 sram_impl/mem0/WD3_INT (to WE_mem)
--------
0.454 (28.9% logic, 71.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_14:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R2C4A.CLK CLK_c
--------
1.623 (27.0% logic, 73.0% route), 1 logic levels.
Destination Clock Path CLK to sram_impl/mem0/SLICE_6:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.151 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 0.591 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.174 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 0.317 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.267 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 0.639 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.174 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 0.463 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.174 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.319 R5C4D.F1 to R5C4B.A1 n9
CTOF_DEL --- 0.174 R5C4B.A1 to R5C4B.F1 SLICE_73
ROUTE 4 0.597 R5C4B.F1 to R5C3B.WCK WE_mem
--------
5.663 (27.4% logic, 72.6% route), 7 logic levels.
Error: The following path exceeds requirements by 3.676ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i1 (from CLK_c +)
Destination: FF Data in r_oport_i1 (to O_STB_c +)
Delay: 0.590ns (22.2% logic, 77.8% route), 1 logic levels.
Constraint Details:
0.590ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_10 to O_PORT_1_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.302ns skew requirement (totaling 4.266ns) by 3.676ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_lo/SLICE_10 to O_PORT_1_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C5B.CLK to R3C5B.Q1 alu_impl_I/alu_impl/alu_lo/SLICE_10 (from CLK_c)
ROUTE 8 0.459 R3C5B.Q1 to IOL_T9D.OPOS akku_1 (to O_STB_c)
--------
0.590 (22.2% logic, 77.8% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R3C5B.CLK CLK_c
--------
1.623 (27.0% logic, 73.0% route), 1 logic levels.
Destination Clock Path CLK to O_PORT_1_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.151 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 0.591 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.174 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 0.317 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.267 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 0.639 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.174 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 0.463 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.174 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.426 R5C4D.F1 to R5C2D.B0 n9
CTOF_DEL --- 0.174 R5C2D.B0 to R5C2D.F0 SLICE_70
ROUTE 9 0.752 R5C2D.F0 to IOL_T9D.CLK O_STB_c
--------
5.925 (26.2% logic, 73.8% route), 7 logic levels.
Error: The following path exceeds requirements by 3.647ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i2 (from CLK_c +)
Destination: FF Data in r_oport_i2 (to O_STB_c +)
Delay: 0.619ns (21.2% logic, 78.8% route), 1 logic levels.
Constraint Details:
0.619ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_11 to O_PORT_2_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.302ns skew requirement (totaling 4.266ns) by 3.647ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_lo/SLICE_11 to O_PORT_2_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R4C5C.CLK to R4C5C.Q0 alu_impl_I/alu_impl/alu_lo/SLICE_11 (from CLK_c)
ROUTE 8 0.488 R4C5C.Q0 to IOL_R5A.OPOS akku_2 (to O_STB_c)
--------
0.619 (21.2% logic, 78.8% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK to alu_impl_I/alu_impl/alu_lo/SLICE_11:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R4C5C.CLK CLK_c
--------
1.623 (27.0% logic, 73.0% route), 1 logic levels.
Destination Clock Path CLK to O_PORT_2_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.151 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 0.591 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.174 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 0.317 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.267 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 0.639 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.174 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 0.463 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.174 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.426 R5C4D.F1 to R5C2D.B0 n9
CTOF_DEL --- 0.174 R5C2D.B0 to R5C2D.F0 SLICE_70
ROUTE 9 0.752 R5C2D.F0 to IOL_R5A.CLK O_STB_c
--------
5.925 (26.2% logic, 73.8% route), 7 logic levels.
Error: The following path exceeds requirements by 3.602ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i6 (from CLK_c +)
Destination: FF Data in sram_impl/mem0/RAM1 (to WE_mem +)
FF sram_impl/mem0/RAM1
Delay: 0.567ns (23.1% logic, 76.9% route), 2 logic levels.
Constraint Details:
0.567ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_13 to sram_impl/mem0/SLICE_6 exceeds
0.129ns WD_HLD and
0.000ns delay constraint less
-4.040ns skew requirement (totaling 4.169ns) by 3.602ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_hi/SLICE_13 to sram_impl/mem0/SLICE_6:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C5C.CLK to R3C5C.Q0 alu_impl_I/alu_impl/alu_hi/SLICE_13 (from CLK_c)
ROUTE 8 0.436 R3C5C.Q0 to R5C3C.C1 akku_6
ZERO_DEL --- 0.000 R5C3C.C1 to R5C3C.WDO2 sram_impl/mem0/SLICE_4
ROUTE 1 0.000 R5C3C.WDO2 to R5C3B.WD0 sram_impl/mem0/WD2_INT (to WE_mem)
--------
0.567 (23.1% logic, 76.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_13:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R3C5C.CLK CLK_c
--------
1.623 (27.0% logic, 73.0% route), 1 logic levels.
Destination Clock Path CLK to sram_impl/mem0/SLICE_6:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.151 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 0.591 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.174 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 0.317 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.267 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 0.639 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.174 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 0.463 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.174 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.319 R5C4D.F1 to R5C4B.A1 n9
CTOF_DEL --- 0.174 R5C4B.A1 to R5C4B.F1 SLICE_73
ROUTE 4 0.597 R5C4B.F1 to R5C3B.WCK WE_mem
--------
5.663 (27.4% logic, 72.6% route), 7 logic levels.
Error: The following path exceeds requirements by 3.564ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i0 (from CLK_c +)
Destination: FF Data in r_oport_i0 (to O_STB_c +)
Delay: 0.702ns (18.7% logic, 81.3% route), 1 logic levels.
Constraint Details:
0.702ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_10 to O_PORT_0_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.302ns skew requirement (totaling 4.266ns) by 3.564ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_lo/SLICE_10 to O_PORT_0_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C5B.CLK to R3C5B.Q0 alu_impl_I/alu_impl/alu_lo/SLICE_10 (from CLK_c)
ROUTE 7 0.571 R3C5B.Q0 to IOL_T9B.OPOS akku_0 (to O_STB_c)
--------
0.702 (18.7% logic, 81.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R3C5B.CLK CLK_c
--------
1.623 (27.0% logic, 73.0% route), 1 logic levels.
Destination Clock Path CLK to O_PORT_0_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.151 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 0.591 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.174 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 0.317 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.267 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 0.639 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.174 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 0.463 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.174 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.426 R5C4D.F1 to R5C2D.B0 n9
CTOF_DEL --- 0.174 R5C2D.B0 to R5C2D.F0 SLICE_70
ROUTE 9 0.752 R5C2D.F0 to IOL_T9B.CLK O_STB_c
--------
5.925 (26.2% logic, 73.8% route), 7 logic levels.
Error: The following path exceeds requirements by 3.564ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i7 (from CLK_c +)
Destination: FF Data in r_oport_i7 (to O_STB_c +)
Delay: 0.702ns (18.7% logic, 81.3% route), 1 logic levels.
Constraint Details:
0.702ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_14 to O_PORT_7_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.302ns skew requirement (totaling 4.266ns) by 3.564ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_hi/SLICE_14 to O_PORT_7_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R2C4A.CLK to R2C4A.Q0 alu_impl_I/alu_impl/alu_hi/SLICE_14 (from CLK_c)
ROUTE 8 0.571 R2C4A.Q0 to IOL_L5D.OPOS akku_7 (to O_STB_c)
--------
0.702 (18.7% logic, 81.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_14:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R2C4A.CLK CLK_c
--------
1.623 (27.0% logic, 73.0% route), 1 logic levels.
Destination Clock Path CLK to O_PORT_7_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.151 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 0.591 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.174 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 0.317 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.267 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 0.639 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.174 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 0.463 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.174 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.426 R5C4D.F1 to R5C2D.B0 n9
CTOF_DEL --- 0.174 R5C2D.B0 to R5C2D.F0 SLICE_70
ROUTE 9 0.752 R5C2D.F0 to IOL_L5D.CLK O_STB_c
--------
5.925 (26.2% logic, 73.8% route), 7 logic levels.
Error: The following path exceeds requirements by 3.563ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i6 (from CLK_c +)
Destination: FF Data in r_oport_i6 (to O_STB_c +)
Delay: 0.703ns (18.6% logic, 81.4% route), 1 logic levels.
Constraint Details:
0.703ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_13 to O_PORT_6_MGIOL exceeds
-0.036ns DO_HLD and
0.000ns delay constraint less
-4.302ns skew requirement (totaling 4.266ns) by 3.563ns
Physical Path Details:
Data path alu_impl_I/alu_impl/alu_hi/SLICE_13 to O_PORT_6_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C5C.CLK to R3C5C.Q0 alu_impl_I/alu_impl/alu_hi/SLICE_13 (from CLK_c)
ROUTE 8 0.572 R3C5C.Q0 to IOL_B2A.OPOS akku_6 (to O_STB_c)
--------
0.703 (18.6% logic, 81.4% route), 1 logic levels.
Clock Skew Details:
Source Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_13:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R3C5C.CLK CLK_c
--------
1.623 (27.0% logic, 73.0% route), 1 logic levels.
Destination Clock Path CLK to O_PORT_6_MGIOL:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.439 12.PAD to 12.PADDI CLK
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
REG_DEL --- 0.151 R3C8B.CLK to R3C8B.Q0 SLICE_19
ROUTE 29 0.591 R3C8B.Q0 to R4C9D.C1 pc_0
CTOF_DEL --- 0.174 R4C9D.C1 to R4C9D.F1 SLICE_93
ROUTE 1 0.317 R4C9D.F1 to R4C9A.B0 n30
CTOOFX_DEL --- 0.267 R4C9A.B0 to R4C9A.OFX0 mux_86_Mux_6_i63/SLICE_27
ROUTE 4 0.639 R4C9A.OFX0 to R5C4D.B0 code_data_6
CTOF_DEL --- 0.174 R5C4D.B0 to R5C4D.F0 SLICE_72
ROUTE 1 0.463 R5C4D.F0 to R5C4D.A1 n6
CTOF_DEL --- 0.174 R5C4D.A1 to R5C4D.F1 SLICE_72
ROUTE 2 0.426 R5C4D.F1 to R5C2D.B0 n9
CTOF_DEL --- 0.174 R5C2D.B0 to R5C2D.F0 SLICE_70
ROUTE 9 0.752 R5C2D.F0 to IOL_B2A.CLK O_STB_c
--------
5.925 (26.2% logic, 73.8% route), 7 logic levels.
================================================================================
Preference: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.000000 X ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.070ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i1 (from CLK_c +)
Destination: FF Data in flags_i0 (to CLK_c +)
Delay: 1.057ns (47.7% logic, 52.3% route), 4 logic levels.
Constraint Details:
1.057ns physical path delay SLICE_19 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.070ns
Physical Path Details:
Data path SLICE_19 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8B.CLK to R3C8B.Q1 SLICE_19 (from CLK_c)
ROUTE 67 0.224 R3C8B.Q1 to R2C7D.D1 pc_1
CTOOFX_DEL --- 0.153 R2C7D.D1 to R2C7D.OFX0 alu_impl_I/SLICE_60
ROUTE 1 0.000 R2C7D.OFX0 to R2C7C.FXA alu_impl_I/mux_89_Mux_9_0_f5a
FXTOOFX_DE --- 0.067 R2C7C.FXA to R2C7C.OFX1 alu_impl_I/SLICE_61
ROUTE 20 0.329 R2C7C.OFX1 to R2C4C.A0 int_c_adj_27
CTOOFX_DEL --- 0.153 R2C4C.A0 to R2C4C.OFX0 SLICE_15
ROUTE 1 0.000 R2C4C.OFX0 to R2C4C.DI0 n187 (to CLK_c)
--------
1.057 (47.7% logic, 52.3% route), 4 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R2C4C.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.070ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i1 (from CLK_c +)
Destination: FF Data in flags_i0 (to CLK_c +)
Delay: 1.057ns (47.7% logic, 52.3% route), 4 logic levels.
Constraint Details:
1.057ns physical path delay SLICE_19 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.070ns
Physical Path Details:
Data path SLICE_19 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8B.CLK to R3C8B.Q1 SLICE_19 (from CLK_c)
ROUTE 67 0.224 R3C8B.Q1 to R2C7D.D0 pc_1
CTOOFX_DEL --- 0.153 R2C7D.D0 to R2C7D.OFX0 alu_impl_I/SLICE_60
ROUTE 1 0.000 R2C7D.OFX0 to R2C7C.FXA alu_impl_I/mux_89_Mux_9_0_f5a
FXTOOFX_DE --- 0.067 R2C7C.FXA to R2C7C.OFX1 alu_impl_I/SLICE_61
ROUTE 20 0.329 R2C7C.OFX1 to R2C4C.A0 int_c_adj_27
CTOOFX_DEL --- 0.153 R2C4C.A0 to R2C4C.OFX0 SLICE_15
ROUTE 1 0.000 R2C4C.OFX0 to R2C4C.DI0 n187 (to CLK_c)
--------
1.057 (47.7% logic, 52.3% route), 4 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R2C4C.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.075ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i1 (from CLK_c +)
Destination: FF Data in flags_i0 (to CLK_c +)
Delay: 1.062ns (47.5% logic, 52.5% route), 4 logic levels.
Constraint Details:
1.062ns physical path delay SLICE_19 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.075ns
Physical Path Details:
Data path SLICE_19 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8B.CLK to R3C8B.Q1 SLICE_19 (from CLK_c)
ROUTE 67 0.229 R3C8B.Q1 to R2C7C.D1 pc_1
CTOOFX_DEL --- 0.153 R2C7C.D1 to R2C7C.OFX0 alu_impl_I/SLICE_61
ROUTE 1 0.000 R2C7C.OFX0 to R2C7C.FXB alu_impl_I/mux_89_Mux_9_1_f5b
FXTOOFX_DE --- 0.067 R2C7C.FXB to R2C7C.OFX1 alu_impl_I/SLICE_61
ROUTE 20 0.329 R2C7C.OFX1 to R2C4C.A0 int_c_adj_27
CTOOFX_DEL --- 0.153 R2C4C.A0 to R2C4C.OFX0 SLICE_15
ROUTE 1 0.000 R2C4C.OFX0 to R2C4C.DI0 n187 (to CLK_c)
--------
1.062 (47.5% logic, 52.5% route), 4 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R2C4C.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.075ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i1 (from CLK_c +)
Destination: FF Data in flags_i0 (to CLK_c +)
Delay: 1.062ns (47.5% logic, 52.5% route), 4 logic levels.
Constraint Details:
1.062ns physical path delay SLICE_19 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.075ns
Physical Path Details:
Data path SLICE_19 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8B.CLK to R3C8B.Q1 SLICE_19 (from CLK_c)
ROUTE 67 0.229 R3C8B.Q1 to R2C7C.D0 pc_1
CTOOFX_DEL --- 0.153 R2C7C.D0 to R2C7C.OFX0 alu_impl_I/SLICE_61
ROUTE 1 0.000 R2C7C.OFX0 to R2C7C.FXB alu_impl_I/mux_89_Mux_9_1_f5b
FXTOOFX_DE --- 0.067 R2C7C.FXB to R2C7C.OFX1 alu_impl_I/SLICE_61
ROUTE 20 0.329 R2C7C.OFX1 to R2C4C.A0 int_c_adj_27
CTOOFX_DEL --- 0.153 R2C4C.A0 to R2C4C.OFX0 SLICE_15
ROUTE 1 0.000 R2C4C.OFX0 to R2C4C.DI0 n187 (to CLK_c)
--------
1.062 (47.5% logic, 52.5% route), 4 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R2C4C.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.083ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from CLK_c +)
Destination: FF Data in flags_i0 (to CLK_c +)
Delay: 1.070ns (47.1% logic, 52.9% route), 4 logic levels.
Constraint Details:
1.070ns physical path delay SLICE_20 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.083ns
Physical Path Details:
Data path SLICE_20 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8D.CLK to R3C8D.Q1 SLICE_20 (from CLK_c)
ROUTE 68 0.237 R3C8D.Q1 to R2C7C.C1 pc_3
CTOOFX_DEL --- 0.153 R2C7C.C1 to R2C7C.OFX0 alu_impl_I/SLICE_61
ROUTE 1 0.000 R2C7C.OFX0 to R2C7C.FXB alu_impl_I/mux_89_Mux_9_1_f5b
FXTOOFX_DE --- 0.067 R2C7C.FXB to R2C7C.OFX1 alu_impl_I/SLICE_61
ROUTE 20 0.329 R2C7C.OFX1 to R2C4C.A0 int_c_adj_27
CTOOFX_DEL --- 0.153 R2C4C.A0 to R2C4C.OFX0 SLICE_15
ROUTE 1 0.000 R2C4C.OFX0 to R2C4C.DI0 n187 (to CLK_c)
--------
1.070 (47.1% logic, 52.9% route), 4 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R3C8D.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R2C4C.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.083ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i3 (from CLK_c +)
Destination: FF Data in flags_i0 (to CLK_c +)
Delay: 1.070ns (47.1% logic, 52.9% route), 4 logic levels.
Constraint Details:
1.070ns physical path delay SLICE_20 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.083ns
Physical Path Details:
Data path SLICE_20 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8D.CLK to R3C8D.Q1 SLICE_20 (from CLK_c)
ROUTE 68 0.237 R3C8D.Q1 to R2C7C.C0 pc_3
CTOOFX_DEL --- 0.153 R2C7C.C0 to R2C7C.OFX0 alu_impl_I/SLICE_61
ROUTE 1 0.000 R2C7C.OFX0 to R2C7C.FXB alu_impl_I/mux_89_Mux_9_1_f5b
FXTOOFX_DE --- 0.067 R2C7C.FXB to R2C7C.OFX1 alu_impl_I/SLICE_61
ROUTE 20 0.329 R2C7C.OFX1 to R2C4C.A0 int_c_adj_27
CTOOFX_DEL --- 0.153 R2C4C.A0 to R2C4C.OFX0 SLICE_15
ROUTE 1 0.000 R2C4C.OFX0 to R2C4C.DI0 n187 (to CLK_c)
--------
1.070 (47.1% logic, 52.9% route), 4 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R3C8D.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R2C4C.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.095ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i0 (from CLK_c +)
Destination: FF Data in flags_i0 (to CLK_c +)
Delay: 1.082ns (34.8% logic, 65.2% route), 3 logic levels.
Constraint Details:
1.082ns physical path delay SLICE_19 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.095ns
Physical Path Details:
Data path SLICE_19 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8B.CLK to R3C8B.Q0 SLICE_19 (from CLK_c)
ROUTE 29 0.376 R3C8B.Q0 to R2C7C.M1 pc_0
MTOOFX_DEL --- 0.093 R2C7C.M1 to R2C7C.OFX1 alu_impl_I/SLICE_61
ROUTE 20 0.329 R2C7C.OFX1 to R2C4C.A0 int_c_adj_27
CTOOFX_DEL --- 0.153 R2C4C.A0 to R2C4C.OFX0 SLICE_15
ROUTE 1 0.000 R2C4C.OFX0 to R2C4C.DI0 n187 (to CLK_c)
--------
1.082 (34.8% logic, 65.2% route), 3 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R2C4C.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.108ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i1 (from CLK_c +)
Destination: FF Data in alu_impl_I/alu_impl/alu_lo/akku_i0 (to CLK_c +)
Delay: 1.095ns (50.1% logic, 49.9% route), 5 logic levels.
Constraint Details:
1.095ns physical path delay SLICE_19 to alu_impl_I/alu_impl/alu_lo/SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.108ns
Physical Path Details:
Data path SLICE_19 to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8B.CLK to R3C8B.Q1 SLICE_19 (from CLK_c)
ROUTE 67 0.235 R3C8B.Q1 to R4C7B.C1 pc_1
CTOOFX_DEL --- 0.153 R4C7B.C1 to R4C7B.OFX0 alu_impl_I/i2726/SLICE_30
ROUTE 1 0.000 R4C7B.OFX0 to R4C7A.FXA alu_impl_I/n3425
FXTOOFX_DE --- 0.067 R4C7A.FXA to R4C7A.OFX1 alu_impl_I/i2727/SLICE_29
ROUTE 17 0.254 R4C7A.OFX1 to R3C5A.C1 code_data_7
CTOF_DEL --- 0.099 R3C5A.C1 to R3C5A.F1 SLICE_16
ROUTE 2 0.057 R3C5A.F1 to R3C5B.C0 F_0
CTOF_DEL --- 0.099 R3C5B.C0 to R3C5B.F0 alu_impl_I/alu_impl/alu_lo/SLICE_10
ROUTE 1 0.000 R3C5B.F0 to R3C5B.DI0 alu_impl_I/alu_impl/alu_lo/n3805 (to CLK_c)
--------
1.095 (50.1% logic, 49.9% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R3C5B.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.108ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i1 (from CLK_c +)
Destination: FF Data in alu_impl_I/alu_impl/alu_lo/akku_i0 (to CLK_c +)
Delay: 1.095ns (50.1% logic, 49.9% route), 5 logic levels.
Constraint Details:
1.095ns physical path delay SLICE_19 to alu_impl_I/alu_impl/alu_lo/SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.108ns
Physical Path Details:
Data path SLICE_19 to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8B.CLK to R3C8B.Q1 SLICE_19 (from CLK_c)
ROUTE 67 0.235 R3C8B.Q1 to R4C7B.C0 pc_1
CTOOFX_DEL --- 0.153 R4C7B.C0 to R4C7B.OFX0 alu_impl_I/i2726/SLICE_30
ROUTE 1 0.000 R4C7B.OFX0 to R4C7A.FXA alu_impl_I/n3425
FXTOOFX_DE --- 0.067 R4C7A.FXA to R4C7A.OFX1 alu_impl_I/i2727/SLICE_29
ROUTE 17 0.254 R4C7A.OFX1 to R3C5A.C1 code_data_7
CTOF_DEL --- 0.099 R3C5A.C1 to R3C5A.F1 SLICE_16
ROUTE 2 0.057 R3C5A.F1 to R3C5B.C0 F_0
CTOF_DEL --- 0.099 R3C5B.C0 to R3C5B.F0 alu_impl_I/alu_impl/alu_lo/SLICE_10
ROUTE 1 0.000 R3C5B.F0 to R3C5B.DI0 alu_impl_I/alu_impl/alu_lo/n3805 (to CLK_c)
--------
1.095 (50.1% logic, 49.9% route), 5 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R3C8B.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R3C5B.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.130ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q rom_impl/pc_i5 (from CLK_c +)
Destination: FF Data in alu_impl_I/alu_impl/alu_lo/akku_i0 (to CLK_c +)
Delay: 1.117ns (37.8% logic, 62.2% route), 4 logic levels.
Constraint Details:
1.117ns physical path delay SLICE_21 to alu_impl_I/alu_impl/alu_lo/SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 1.130ns
Physical Path Details:
Data path SLICE_21 to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C8C.CLK to R3C8C.Q1 SLICE_21 (from CLK_c)
ROUTE 31 0.384 R3C8C.Q1 to R4C7A.M1 pc_5
MTOOFX_DEL --- 0.093 R4C7A.M1 to R4C7A.OFX1 alu_impl_I/i2727/SLICE_29
ROUTE 17 0.254 R4C7A.OFX1 to R3C5A.C1 code_data_7
CTOF_DEL --- 0.099 R3C5A.C1 to R3C5A.F1 SLICE_16
ROUTE 2 0.057 R3C5A.F1 to R3C5B.C0 F_0
CTOF_DEL --- 0.099 R3C5B.C0 to R3C5B.F0 alu_impl_I/alu_impl/alu_lo/SLICE_10
ROUTE 1 0.000 R3C5B.F0 to R3C5B.DI0 alu_impl_I/alu_impl/alu_lo/n3805 (to CLK_c)
--------
1.117 (37.8% logic, 62.2% route), 4 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R3C8C.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to alu_impl_I/alu_impl/alu_lo/SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 13 1.184 12.PADDI to R3C5B.CLK CLK_c
--------
1.184 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "CLK" 36.000000 MHz ; | -| -| 1 *
| | |
MULTICYCLE FROM GROUP "code" TO GROUP | | |
"akku" 1.000000 X ; | -| -| 4
| | |
----------------------------------------------------------------------------
1 preference(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
code_data_3 | 12| 76| 23.75%
| | |
code_data_2 | 12| 76| 23.75%
| | |
code_data_0 | 12| 76| 23.75%
| | |
code_data_1 | 12| 76| 23.75%
| | |
pc_4 | 61| 64| 20.00%
| | |
pc_3 | 68| 64| 20.00%
| | |
pc_2 | 68| 64| 20.00%
| | |
pc_1 | 67| 64| 20.00%
| | |
sram_impl/mem1/AD3_INT | 2| 38| 11.88%
| | |
sram_impl/mem1/AD2_INT | 2| 38| 11.88%
| | |
sram_impl/mem1/AD1_INT | 2| 38| 11.88%
| | |
sram_impl/mem1/AD0_INT | 2| 38| 11.88%
| | |
sram_impl/mem0/AD3_INT | 2| 38| 11.88%
| | |
sram_impl/mem0/AD2_INT | 2| 38| 11.88%
| | |
sram_impl/mem0/AD1_INT | 2| 38| 11.88%
| | |
sram_impl/mem0/AD0_INT | 2| 38| 11.88%
| | |
mux_89_Mux_3_1_f5b | 1| 36| 11.25%
| | |
mux_89_Mux_3_0_f5a | 1| 36| 11.25%
| | |
mux_89_Mux_0_1_f5b | 1| 36| 11.25%
| | |
mux_89_Mux_0_0_f5a | 1| 36| 11.25%
| | |
mux_89_Mux_2_1_f5b | 1| 36| 11.25%
| | |
mux_89_Mux_2_0_f5a | 1| 36| 11.25%
| | |
mux_89_Mux_1_1_f5b | 1| 36| 11.25%
| | |
mux_89_Mux_1_0_f5a | 1| 36| 11.25%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 3 clocks:
Clock Domain: O_STB_c Source: SLICE_70.F0 Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: CLK_c Source: CLK.PAD
Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ; Transfers: 8
Clock Domain: CLK_c Source: CLK.PAD Loads: 13
Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ;
Covered under: MULTICYCLE FROM GROUP "code" TO GROUP "akku" 1.000000 X ;
Data transfers from:
Clock Domain: WE_mem Source: SLICE_73.F1
Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ; Transfers: 8
Clock Domain: WE_mem Source: SLICE_73.F1 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: CLK_c Source: CLK.PAD
Covered under: FREQUENCY PORT "CLK" 36.000000 MHz ; Transfers: 14
Timing summary (Hold):
---------------
Timing errors: 320 Score: 946135
Cumulative negative slack: 946135
Constraints cover 31153 paths, 8 nets, and 878 connections (97.2% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 320 (hold)
Score: 0 (setup), 946135 (hold)
Cumulative negative slack: 946135 (0+946135)
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