PAR: Place And Route Diamond_1.4_Production (87). Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Mon Jun 25 18:29:29 2012 Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_mcpu_efb.p2t qfn32samples_mcpu_efb_map.ncd qfn32samples_mcpu_efb.dir qfn32samples_mcpu_efb.prf Preference file: qfn32samples_mcpu_efb.prf. Cost Table Summary Level/ Number Timing Run NCD Cost [ncd] Unrouted Score Time Status ---------- -------- -------- ----- ------------ 5_1 * 0 0 01:33 Complete * : Design saved. par done! Lattice Place and Route Report for Design "qfn32samples_mcpu_efb_map.ncd" Mon Jun 25 18:29:29 2012 Best Par Run PAR: Place And Route Diamond_1.4_Production (87). Command Line: Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_mcpu_efb.p2t qfn32samples_mcpu_efb_map.ncd qfn32samples_mcpu_efb.dir qfn32samples_mcpu_efb.prf Preference file: qfn32samples_mcpu_efb.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file qfn32samples_mcpu_efb_map.ncd. Design name: mcpu NCD version: 3.2 Vendor: LATTICE Device: LCMXO2-256HC Package: QFN32 Performance: 4 Loading device for application par from file 'xo2c256.nph' in environment: Y:/Program_Files/lscc/diamond/1.4/ispfpga. Package Status: Advanced Version 1.34 Performance Hardware Data Status: Final) Version 22.4 License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 13/56 23% used 13/22 59% bonded IOLOGIC 8/56 14% used SLICE 64/128 50% used GSR 1/1 100% used EFB 1/1 100% used Number of Signals: 191 Number of Connections: 644 Pin Constraint Summary: 13 out of 13 pins locked (100% locked). The following 1 signal is selected to use the primary clock routing resources: master_clk (driver: SLICE_22, clk load #: 13) The following 2 signals are selected to use the secondary clock routing resources: CLK_3X_c (driver: CLK_3X, clk load #: 8, sr load #: 0, ce load #: 0) O_STB_c (driver: SLICE_59, clk load #: 8, sr load #: 0, ce load #: 0) WARNING - par: Signal "CLK_3X_c" is selected to use Secondary clock resources; however its driver comp "CLK_3X" is located at "12", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it may suffer from excessive delay or skew. Signal RST_NEG is selected as Global Set/Reset. Starting Placer Phase 0. ....... Finished Placer Phase 0. REAL time: 32 secs Starting Placer Phase 1. .................. Placer score = 23586. Finished Placer Phase 1. REAL time: 1 mins 14 secs Starting Placer Phase 2. . Placer score = 23442 Finished Placer Phase 2. REAL time: 1 mins 16 secs Clock Report Global Clock Resources: CLK_PIN : 0 out of 8 (0%) General PIO: 1 out of 56 (1%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY "master_clk" from Q0 on comp "SLICE_22" on site "R2C5C", clk load = 13 SECONDARY "CLK_3X_c" from comp "CLK_3X" on PIO site "12 (PB4B)", clk load = 8, ce load = 0, sr load = 0 SECONDARY "O_STB_c" from F1 on comp "SLICE_59" on site "R5C2A", clk load = 8, ce load = 0, sr load = 0 PRIMARY : 1 out of 8 (12%) SECONDARY: 2 out of 8 (25%) I/O Usage Summary (final): 13 out of 56 (23.2%) PIO sites used. 13 out of 22 (59.1%) bonded PIO sites used. Number of PIO comps: 13; differential: 0 Number of Vref pins used: 0 I/O Bank Usage Summary: +----------+--------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+--------------+------------+-----------+ | 0 | 4 / 9 ( 44%) | 2.5V | - | | 1 | 2 / 2 (100%) | 2.5V | - | | 2 | 6 / 9 ( 66%) | 2.5V | - | | 3 | 1 / 2 ( 50%) | 2.5V | - | +----------+--------------+------------+-----------+ Total placer CPU time: 41 secs Dumping design to file qfn32samples_mcpu_efb.dir/5_1.ncd. 0 connections routed; 644 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 1 mins 22 secs Starting iterative routing. For each routing iteration the number inside the parenthesis is the total time (in picoseconds) the design is failing the timing constraints. For each routing iteration the router will attempt to reduce this number until the number of routing iterations is completed or the value is 0 meaning the design has fully met the timing constraints. End of iteration 1 644 successful; 0 unrouted; (0) real time: 1 mins 25 secs Dumping design to file qfn32samples_mcpu_efb.dir/5_1.ncd. Total CPU time 45 secs Total REAL time: 1 mins 26 secs Completely routed. End of route. 644 routed (100.00%); 0 unrouted. Checking DRC ... No errors found. Timing score: 0 Total REAL time to completion: 1 mins 33 secs Dumping design to file qfn32samples_mcpu_efb.dir/5_1.ncd. All signals are completely routed. par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.