Place & Route TRACE Report

Loading design for application trce from file qfn32samples_udrv.ncd.
Design name: udrv
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-256HC
Package:     QFN32
Performance: 4
Loading device for application trce from file 'xo2c256.nph' in environment: Y:/Program_Files/lscc/diamond/1.4/ispfpga.
Package Status:                     Advanced       Version 1.34
Performance Hardware Data Status:   Final)         Version 22.4
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond_1.4_Production (87)
Fri Jul 06 14:24:27 2012

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_udrv.twr qfn32samples_udrv.ncd qfn32samples_udrv.prf 
Design file:     qfn32samples_udrv.ncd
Preference file: qfn32samples_udrv.prf
Device,speed:    LCMXO2-256HC,4
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY PORT "SCK" 16.000000 MHz (0 errors)
  • 65 items scored, 0 timing errors detected. Report: 130.822MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "CLK_4X" 60.000000 MHz (0 errors)
  • 1800 items scored, 0 timing errors detected. Report: 64.177MHz is the maximum frequency for this preference.
  • MULTICYCLE TO PORT "DP" 20.000000 ns (0 errors)
  • 2 items scored, 0 timing errors detected.
  • MULTICYCLE TO PORT "DM" 20.000000 ns (0 errors)
  • 2 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "SCK" 16.000000 MHz ; 65 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 27.428ns (weighted slack = 54.856ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_count_341__i1 (from SCK_c -) Destination: FF Data in spi_impl/i_data_ack_36 (to SCK_c +) Delay: 3.548ns (26.7% logic, 73.3% route), 2 logic levels. Constraint Details: 3.548ns physical path delay spi_impl/SLICE_112 to spi_impl/SLICE_168 meets 31.250ns delay constraint less 0.000ns skew and 0.274ns LSR_SET requirement (totaling 30.976ns) by 27.428ns Physical Path Details: Data path spi_impl/SLICE_112 to spi_impl/SLICE_168: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C9D.CLK to R4C9D.Q0 spi_impl/SLICE_112 (from SCK_c) ROUTE 6 1.532 R4C9D.Q0 to R5C9A.C1 spi_impl/r_count_1 CTOF_DEL --- 0.495 R5C9A.C1 to R5C9A.F1 spi_impl/SLICE_30 ROUTE 1 1.069 R5C9A.F1 to R4C9B.LSR spi_impl/n5 (to SCK_c) -------- 3.548 (26.7% logic, 73.3% route), 2 logic levels. Clock Skew Details: Source Clock Path SCK to spi_impl/SLICE_112: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R4C9D.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to spi_impl/SLICE_168: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R4C9B.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 27.505ns (weighted slack = 55.010ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_mosi_35 (from SCK_c +) Destination: FF Data in spi_impl/spi_out_i0_i0 (to SCK_c -) Delay: 3.224ns (17.9% logic, 82.1% route), 1 logic levels. Constraint Details: 3.224ns physical path delay MOSI_MGIOL to SLICE_170 meets 31.250ns delay constraint less 0.173ns skew and 0.348ns M_SET requirement (totaling 30.729ns) by 27.505ns Physical Path Details: Data path MOSI_MGIOL to SLICE_170: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_B2D.CLK to IOL_B2D.IN MOSI_MGIOL (from SCK_c) ROUTE 2 2.647 IOL_B2D.IN to R3C5C.M0 spi_impl/r_mosi (to SCK_c) -------- 3.224 (17.9% logic, 82.1% route), 1 logic levels. Clock Skew Details: Source Clock Path SCK to MOSI_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 15 2.139 11.PADDI to IOL_B2D.CLK SCK_c -------- 2.139 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to SLICE_170: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R3C5C.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 27.917ns (weighted slack = 55.834ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_count_341__i2 (from SCK_c -) Destination: FF Data in spi_impl/i_data_ack_36 (to SCK_c +) Delay: 3.059ns (31.0% logic, 69.0% route), 2 logic levels. Constraint Details: 3.059ns physical path delay spi_impl/SLICE_112 to spi_impl/SLICE_168 meets 31.250ns delay constraint less 0.000ns skew and 0.274ns LSR_SET requirement (totaling 30.976ns) by 27.917ns Physical Path Details: Data path spi_impl/SLICE_112 to spi_impl/SLICE_168: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C9D.CLK to R4C9D.Q1 spi_impl/SLICE_112 (from SCK_c) ROUTE 5 1.043 R4C9D.Q1 to R5C9A.B1 spi_impl/r_count_2 CTOF_DEL --- 0.495 R5C9A.B1 to R5C9A.F1 spi_impl/SLICE_30 ROUTE 1 1.069 R5C9A.F1 to R4C9B.LSR spi_impl/n5 (to SCK_c) -------- 3.059 (31.0% logic, 69.0% route), 2 logic levels. Clock Skew Details: Source Clock Path SCK to spi_impl/SLICE_112: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R4C9D.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to spi_impl/SLICE_168: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R4C9B.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 27.932ns (weighted slack = 55.864ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_mosi_35 (from SCK_c +) Destination: FF Data in spi_impl/r_spi_i0 (to SCK_c -) Delay: 2.797ns (20.6% logic, 79.4% route), 1 logic levels. Constraint Details: 2.797ns physical path delay MOSI_MGIOL to SLICE_113 meets 31.250ns delay constraint less 0.173ns skew and 0.348ns M_SET requirement (totaling 30.729ns) by 27.932ns Physical Path Details: Data path MOSI_MGIOL to SLICE_113: Name Fanout Delay (ns) Site Resource C2INP_DEL --- 0.577 IOL_B2D.CLK to IOL_B2D.IN MOSI_MGIOL (from SCK_c) ROUTE 2 2.220 IOL_B2D.IN to R3C6B.M0 spi_impl/r_mosi (to SCK_c) -------- 2.797 (20.6% logic, 79.4% route), 1 logic levels. Clock Skew Details: Source Clock Path SCK to MOSI_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 15 2.139 11.PADDI to IOL_B2D.CLK SCK_c -------- 2.139 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to SLICE_113: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R3C6B.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 27.954ns (weighted slack = 55.908ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_count_341__i0 (from SCK_c -) Destination: FF Data in spi_impl/i_data_ack_36 (to SCK_c +) Delay: 3.022ns (31.3% logic, 68.7% route), 2 logic levels. Constraint Details: 3.022ns physical path delay SLICE_111 to spi_impl/SLICE_168 meets 31.250ns delay constraint less 0.000ns skew and 0.274ns LSR_SET requirement (totaling 30.976ns) by 27.954ns Physical Path Details: Data path SLICE_111 to spi_impl/SLICE_168: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C9C.CLK to R4C9C.Q0 SLICE_111 (from SCK_c) ROUTE 7 1.006 R4C9C.Q0 to R5C9A.A1 spi_impl/r_count_0 CTOF_DEL --- 0.495 R5C9A.A1 to R5C9A.F1 spi_impl/SLICE_30 ROUTE 1 1.069 R5C9A.F1 to R4C9B.LSR spi_impl/n5 (to SCK_c) -------- 3.022 (31.3% logic, 68.7% route), 2 logic levels. Clock Skew Details: Source Clock Path SCK to SLICE_111: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R4C9C.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to spi_impl/SLICE_168: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R4C9B.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 57.864ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_count_341__i1 (from SCK_c -) Destination: FF Data in spi_impl/o_data_rdy_39 (to SCK_c -) Delay: 4.329ns (33.3% logic, 66.7% route), 3 logic levels. Constraint Details: 4.329ns physical path delay spi_impl/SLICE_112 to spi_impl/SLICE_30 meets 62.500ns delay constraint less 0.000ns skew and 0.307ns CE_SET requirement (totaling 62.193ns) by 57.864ns Physical Path Details: Data path spi_impl/SLICE_112 to spi_impl/SLICE_30: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C9D.CLK to R4C9D.Q0 spi_impl/SLICE_112 (from SCK_c) ROUTE 6 1.532 R4C9D.Q0 to R5C9A.C0 spi_impl/r_count_1 CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 spi_impl/SLICE_30 ROUTE 2 0.702 R5C9A.F0 to R5C9B.B1 spi_impl/n1875 CTOF_DEL --- 0.495 R5C9B.B1 to R5C9B.F1 SLICE_110 ROUTE 1 0.653 R5C9B.F1 to R5C9A.CE spi_impl/n990 (to SCK_c) -------- 4.329 (33.3% logic, 66.7% route), 3 logic levels. Clock Skew Details: Source Clock Path SCK to spi_impl/SLICE_112: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R4C9D.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to spi_impl/SLICE_30: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R5C9A.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.253ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_count_341__i0 (from SCK_c -) Destination: FF Data in spi_impl/r_spi_i1 (to SCK_c -) Delay: 4.081ns (35.3% logic, 64.7% route), 3 logic levels. Constraint Details: 4.081ns physical path delay SLICE_111 to spi_impl/SLICE_114 meets 62.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 62.334ns) by 58.253ns Physical Path Details: Data path SLICE_111 to spi_impl/SLICE_114: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C9C.CLK to R4C9C.Q0 SLICE_111 (from SCK_c) ROUTE 7 1.060 R4C9C.Q0 to R4C9A.B1 spi_impl/r_count_0 CTOF_DEL --- 0.495 R4C9A.B1 to R4C9A.F1 spi_impl/SLICE_117 ROUTE 8 1.579 R4C9A.F1 to R4C5D.B0 spi_impl/n5_adj_3 CTOF_DEL --- 0.495 R4C5D.B0 to R4C5D.F0 spi_impl/SLICE_114 ROUTE 1 0.000 R4C5D.F0 to R4C5D.DI0 spi_impl/n25 (to SCK_c) -------- 4.081 (35.3% logic, 64.7% route), 3 logic levels. Clock Skew Details: Source Clock Path SCK to SLICE_111: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R4C9C.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to spi_impl/SLICE_114: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R4C5D.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.253ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_count_341__i0 (from SCK_c -) Destination: FF Data in spi_impl/r_spi_i2 (to SCK_c -) Delay: 4.081ns (35.3% logic, 64.7% route), 3 logic levels. Constraint Details: 4.081ns physical path delay SLICE_111 to spi_impl/SLICE_114 meets 62.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 62.334ns) by 58.253ns Physical Path Details: Data path SLICE_111 to spi_impl/SLICE_114: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C9C.CLK to R4C9C.Q0 SLICE_111 (from SCK_c) ROUTE 7 1.060 R4C9C.Q0 to R4C9A.B1 spi_impl/r_count_0 CTOF_DEL --- 0.495 R4C9A.B1 to R4C9A.F1 spi_impl/SLICE_117 ROUTE 8 1.579 R4C9A.F1 to R4C5D.B1 spi_impl/n5_adj_3 CTOF_DEL --- 0.495 R4C5D.B1 to R4C5D.F1 spi_impl/SLICE_114 ROUTE 1 0.000 R4C5D.F1 to R4C5D.DI1 spi_impl/n24 (to SCK_c) -------- 4.081 (35.3% logic, 64.7% route), 3 logic levels. Clock Skew Details: Source Clock Path SCK to SLICE_111: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R4C9C.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to spi_impl/SLICE_114: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R4C5D.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.253ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_count_341__i0 (from SCK_c -) Destination: FF Data in spi_impl/r_spi_i4 (to SCK_c -) Delay: 4.081ns (35.3% logic, 64.7% route), 3 logic levels. Constraint Details: 4.081ns physical path delay SLICE_111 to spi_impl/SLICE_115 meets 62.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 62.334ns) by 58.253ns Physical Path Details: Data path SLICE_111 to spi_impl/SLICE_115: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C9C.CLK to R4C9C.Q0 SLICE_111 (from SCK_c) ROUTE 7 1.060 R4C9C.Q0 to R4C9A.B1 spi_impl/r_count_0 CTOF_DEL --- 0.495 R4C9A.B1 to R4C9A.F1 spi_impl/SLICE_117 ROUTE 8 1.579 R4C9A.F1 to R4C5A.B1 spi_impl/n5_adj_3 CTOF_DEL --- 0.495 R4C5A.B1 to R4C5A.F1 spi_impl/SLICE_115 ROUTE 1 0.000 R4C5A.F1 to R4C5A.DI1 spi_impl/n22 (to SCK_c) -------- 4.081 (35.3% logic, 64.7% route), 3 logic levels. Clock Skew Details: Source Clock Path SCK to SLICE_111: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R4C9C.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to spi_impl/SLICE_115: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R4C5A.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 58.253ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_count_341__i0 (from SCK_c -) Destination: FF Data in spi_impl/r_spi_i3 (to SCK_c -) Delay: 4.081ns (35.3% logic, 64.7% route), 3 logic levels. Constraint Details: 4.081ns physical path delay SLICE_111 to spi_impl/SLICE_115 meets 62.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 62.334ns) by 58.253ns Physical Path Details: Data path SLICE_111 to spi_impl/SLICE_115: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C9C.CLK to R4C9C.Q0 SLICE_111 (from SCK_c) ROUTE 7 1.060 R4C9C.Q0 to R4C9A.B1 spi_impl/r_count_0 CTOF_DEL --- 0.495 R4C9A.B1 to R4C9A.F1 spi_impl/SLICE_117 ROUTE 8 1.579 R4C9A.F1 to R4C5A.B0 spi_impl/n5_adj_3 CTOF_DEL --- 0.495 R4C5A.B0 to R4C5A.F0 spi_impl/SLICE_115 ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 spi_impl/n23 (to SCK_c) -------- 4.081 (35.3% logic, 64.7% route), 3 logic levels. Clock Skew Details: Source Clock Path SCK to SLICE_111: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R4C9C.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to spi_impl/SLICE_115: Name Fanout Delay (ns) Site Resource ROUTE 15 1.966 11.PADDI to R4C5A.CLK SCK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Report: 130.822MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "CLK_4X" 60.000000 MHz ; 1800 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.542ns (weighted slack = 1.084ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q r_sync_req1_97 (from CLK -) Destination: FF Data in clkgen_impl/r_done_24 (to i_clk4x +) Delay: 4.222ns (22.4% logic, 77.6% route), 2 logic levels. Constraint Details: 4.222ns physical path delay SLICE_11 to SLICE_149 meets 8.333ns delay constraint less 3.295ns skew and 0.274ns LSR_SET requirement (totaling 4.764ns) by 0.542ns Physical Path Details: Data path SLICE_11 to SLICE_149: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C6B.CLK to R4C6B.Q1 SLICE_11 (from CLK) ROUTE 2 1.457 R4C6B.Q1 to R3C5C.B0 r_sync_req1 CTOF_DEL --- 0.495 R3C5C.B0 to R3C5C.F0 SLICE_170 ROUTE 2 1.818 R3C5C.F0 to R3C6D.LSR clkgen_impl/SYNC_REQ (to i_clk4x) -------- 4.222 (22.4% logic, 77.6% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK_4X to SLICE_11: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 20.PAD to 20.PADDI CLK_4X ROUTE 1 2.590 20.PADDI to DCM6.CLK0 CLK_4X_c MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector ROUTE 4 0.851 DCM6.DCMOUT to R2C5C.CLK i_clk4x REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 clkgen_impl/SLICE_12 ROUTE 93 2.843 R2C5C.Q0 to R4C6B.CLK CLK -------- 8.108 (22.5% logic, 77.5% route), 3 logic levels. Destination Clock Path CLK_4X to SLICE_149: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 20.PAD to 20.PADDI CLK_4X ROUTE 1 2.590 20.PADDI to DCM6.CLK0 CLK_4X_c MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector ROUTE 4 0.851 DCM6.DCMOUT to R3C6D.CLK i_clk4x -------- 4.813 (28.5% logic, 71.5% route), 2 logic levels. Passed: The following path meets requirements by 0.855ns (weighted slack = 1.710ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q fifo_impl/o_rdy_46 (from CLK -) Destination: FF Data in sender_impl/send_stat_i2 (to CLK +) Delay: 7.204ns (40.6% logic, 59.4% route), 6 logic levels. Constraint Details: 7.204ns physical path delay SLICE_17 to sender_impl/SLICE_98 meets 8.333ns delay constraint less 0.000ns skew and 0.274ns LSR_SET requirement (totaling 8.059ns) by 0.855ns Physical Path Details: Data path SLICE_17 to sender_impl/SLICE_98: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C7B.CLK to R4C7B.Q0 SLICE_17 (from CLK) ROUTE 6 1.299 R4C7B.Q0 to R4C2C.C0 O_DATA_RDY CTOF_DEL --- 0.495 R4C2C.C0 to R4C2C.F0 SLICE_132 ROUTE 5 0.469 R4C2C.F0 to R4C2C.C1 n95 CTOF_DEL --- 0.495 R4C2C.C1 to R4C2C.F1 SLICE_132 ROUTE 3 0.658 R4C2C.F1 to R3C2B.D0 n113_adj_6 CTOF_DEL --- 0.495 R3C2B.D0 to R3C2B.F0 sender_impl/SLICE_142 ROUTE 2 0.753 R3C2B.F0 to R3C3C.C1 sender_impl/n977 CTOF_DEL --- 0.495 R3C3C.C1 to R3C3C.F1 SLICE_120 ROUTE 2 0.445 R3C3C.F1 to R3C3C.C0 sender_impl/n2944 CTOF_DEL --- 0.495 R3C3C.C0 to R3C3C.F0 SLICE_120 ROUTE 1 0.653 R3C3C.F0 to R3C3D.LSR sender_impl/n3095 (to CLK) -------- 7.204 (40.6% logic, 59.4% route), 6 logic levels. Clock Skew Details: Source Clock Path clkgen_impl/SLICE_12 to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 93 2.843 R2C5C.Q0 to R4C7B.CLK CLK -------- 2.843 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clkgen_impl/SLICE_12 to sender_impl/SLICE_98: Name Fanout Delay (ns) Site Resource ROUTE 93 2.843 R2C5C.Q0 to R3C3D.CLK CLK -------- 2.843 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.872ns (weighted slack = 1.744ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q r_sync_req1_97 (from CLK -) Destination: FF Data in clkgen_impl/clk_ph_335__i1 (to i_clk4x +) Delay: 4.000ns (36.0% logic, 64.0% route), 3 logic levels. Constraint Details: 4.000ns physical path delay SLICE_11 to clkgen_impl/SLICE_12 meets 8.333ns delay constraint less 3.295ns skew and 0.166ns DIN_SET requirement (totaling 4.872ns) by 0.872ns Physical Path Details: Data path SLICE_11 to clkgen_impl/SLICE_12: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C6B.CLK to R4C6B.Q1 SLICE_11 (from CLK) ROUTE 2 1.932 R4C6B.Q1 to R2C5C.A1 r_sync_req1 CTOF_DEL --- 0.495 R2C5C.A1 to R2C5C.F1 clkgen_impl/SLICE_12 ROUTE 1 0.626 R2C5C.F1 to R2C5C.D0 clkgen_impl/n821 CTOF_DEL --- 0.495 R2C5C.D0 to R2C5C.F0 clkgen_impl/SLICE_12 ROUTE 1 0.000 R2C5C.F0 to R2C5C.DI0 clkgen_impl/n15 (to i_clk4x) -------- 4.000 (36.0% logic, 64.0% route), 3 logic levels. Clock Skew Details: Source Clock Path CLK_4X to SLICE_11: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 20.PAD to 20.PADDI CLK_4X ROUTE 1 2.590 20.PADDI to DCM6.CLK0 CLK_4X_c MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector ROUTE 4 0.851 DCM6.DCMOUT to R2C5C.CLK i_clk4x REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 clkgen_impl/SLICE_12 ROUTE 93 2.843 R2C5C.Q0 to R4C6B.CLK CLK -------- 8.108 (22.5% logic, 77.5% route), 3 logic levels. Destination Clock Path CLK_4X to clkgen_impl/SLICE_12: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 20.PAD to 20.PADDI CLK_4X ROUTE 1 2.590 20.PADDI to DCM6.CLK0 CLK_4X_c MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector ROUTE 4 0.851 DCM6.DCMOUT to R2C5C.CLK i_clk4x -------- 4.813 (28.5% logic, 71.5% route), 2 logic levels. Passed: The following path meets requirements by 0.886ns (weighted slack = 1.772ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q r_sync_req_99 (from CLK -) Destination: FF Data in clkgen_impl/r_done_24 (to i_clk4x +) Delay: 3.878ns (24.4% logic, 75.6% route), 2 logic levels. Constraint Details: 3.878ns physical path delay SLICE_144 to SLICE_149 meets 8.333ns delay constraint less 3.295ns skew and 0.274ns LSR_SET requirement (totaling 4.764ns) by 0.886ns Physical Path Details: Data path SLICE_144 to SLICE_149: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C4D.CLK to R2C4D.Q0 SLICE_144 (from CLK) ROUTE 4 1.113 R2C4D.Q0 to R3C5C.C0 r_sync_req CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 SLICE_170 ROUTE 2 1.818 R3C5C.F0 to R3C6D.LSR clkgen_impl/SYNC_REQ (to i_clk4x) -------- 3.878 (24.4% logic, 75.6% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK_4X to SLICE_144: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 20.PAD to 20.PADDI CLK_4X ROUTE 1 2.590 20.PADDI to DCM6.CLK0 CLK_4X_c MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector ROUTE 4 0.851 DCM6.DCMOUT to R2C5C.CLK i_clk4x REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 clkgen_impl/SLICE_12 ROUTE 93 2.843 R2C5C.Q0 to R2C4D.CLK CLK -------- 8.108 (22.5% logic, 77.5% route), 3 logic levels. Destination Clock Path CLK_4X to SLICE_149: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 20.PAD to 20.PADDI CLK_4X ROUTE 1 2.590 20.PADDI to DCM6.CLK0 CLK_4X_c MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector ROUTE 4 0.851 DCM6.DCMOUT to R3C6D.CLK i_clk4x -------- 4.813 (28.5% logic, 71.5% route), 2 logic levels. Passed: The following path meets requirements by 0.892ns (weighted slack = 1.784ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q r_sync_req1_97 (from CLK -) Destination: FF Data in clkgen_impl/clk_ph_335__i0 (to i_clk4x +) Delay: 3.980ns (36.2% logic, 63.8% route), 3 logic levels. Constraint Details: 3.980ns physical path delay SLICE_11 to clkgen_impl/SLICE_33 meets 8.333ns delay constraint less 3.295ns skew and 0.166ns DIN_SET requirement (totaling 4.872ns) by 0.892ns Physical Path Details: Data path SLICE_11 to clkgen_impl/SLICE_33: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C6B.CLK to R4C6B.Q1 SLICE_11 (from CLK) ROUTE 2 1.457 R4C6B.Q1 to R3C5C.B0 r_sync_req1 CTOF_DEL --- 0.495 R3C5C.B0 to R3C5C.F0 SLICE_170 ROUTE 2 1.081 R3C5C.F0 to R2C6B.D0 clkgen_impl/SYNC_REQ CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 clkgen_impl/SLICE_33 ROUTE 1 0.000 R2C6B.F0 to R2C6B.DI0 clkgen_impl/n16 (to i_clk4x) -------- 3.980 (36.2% logic, 63.8% route), 3 logic levels. Clock Skew Details: Source Clock Path CLK_4X to SLICE_11: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 20.PAD to 20.PADDI CLK_4X ROUTE 1 2.590 20.PADDI to DCM6.CLK0 CLK_4X_c MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector ROUTE 4 0.851 DCM6.DCMOUT to R2C5C.CLK i_clk4x REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 clkgen_impl/SLICE_12 ROUTE 93 2.843 R2C5C.Q0 to R4C6B.CLK CLK -------- 8.108 (22.5% logic, 77.5% route), 3 logic levels. Destination Clock Path CLK_4X to clkgen_impl/SLICE_33: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 20.PAD to 20.PADDI CLK_4X ROUTE 1 2.590 20.PADDI to DCM6.CLK0 CLK_4X_c MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector ROUTE 4 0.851 DCM6.DCMOUT to R2C6B.CLK i_clk4x -------- 4.813 (28.5% logic, 71.5% route), 2 logic levels. Passed: The following path meets requirements by 0.906ns (weighted slack = 1.812ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q fifo_impl/o_rdy_46 (from CLK -) Destination: FF Data in sender_impl/data_count_i2 (to CLK +) Delay: 7.153ns (34.0% logic, 66.0% route), 5 logic levels. Constraint Details: 7.153ns physical path delay SLICE_17 to sender_impl/SLICE_102 meets 8.333ns delay constraint less 0.000ns skew and 0.274ns LSR_SET requirement (totaling 8.059ns) by 0.906ns Physical Path Details: Data path SLICE_17 to sender_impl/SLICE_102: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C7B.CLK to R4C7B.Q0 SLICE_17 (from CLK) ROUTE 6 1.473 R4C7B.Q0 to R5C3A.D0 O_DATA_RDY CTOF_DEL --- 0.495 R5C3A.D0 to R5C3A.F0 SLICE_127 ROUTE 4 0.651 R5C3A.F0 to R5C3A.D1 S_DATA_RDY CTOF_DEL --- 0.495 R5C3A.D1 to R5C3A.F1 SLICE_127 ROUTE 5 0.753 R5C3A.F1 to R4C3B.C0 sender_impl/n289 CTOF_DEL --- 0.495 R4C3B.C0 to R4C3B.F0 SLICE_122 ROUTE 4 0.453 R4C3B.F0 to R4C3B.C1 sender_impl/n1007 CTOF_DEL --- 0.495 R4C3B.C1 to R4C3B.F1 SLICE_122 ROUTE 3 1.391 R4C3B.F1 to R5C2B.LSR sender_impl/n1997 (to CLK) -------- 7.153 (34.0% logic, 66.0% route), 5 logic levels. Clock Skew Details: Source Clock Path clkgen_impl/SLICE_12 to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 93 2.843 R2C5C.Q0 to R4C7B.CLK CLK -------- 2.843 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clkgen_impl/SLICE_12 to sender_impl/SLICE_102: Name Fanout Delay (ns) Site Resource ROUTE 93 2.843 R2C5C.Q0 to R5C2B.CLK CLK -------- 2.843 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 1.204ns (weighted slack = 2.408ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q fifo_impl/o_rdy_46 (from CLK -) Destination: FF Data in sender_impl/data_count_i1 (to CLK +) FF sender_impl/data_count_i0 Delay: 6.855ns (35.5% logic, 64.5% route), 5 logic levels. Constraint Details: 6.855ns physical path delay SLICE_17 to sender_impl/SLICE_101 meets 8.333ns delay constraint less 0.000ns skew and 0.274ns LSR_SET requirement (totaling 8.059ns) by 1.204ns Physical Path Details: Data path SLICE_17 to sender_impl/SLICE_101: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C7B.CLK to R4C7B.Q0 SLICE_17 (from CLK) ROUTE 6 1.473 R4C7B.Q0 to R5C3A.D0 O_DATA_RDY CTOF_DEL --- 0.495 R5C3A.D0 to R5C3A.F0 SLICE_127 ROUTE 4 0.651 R5C3A.F0 to R5C3A.D1 S_DATA_RDY CTOF_DEL --- 0.495 R5C3A.D1 to R5C3A.F1 SLICE_127 ROUTE 5 0.753 R5C3A.F1 to R4C3B.C0 sender_impl/n289 CTOF_DEL --- 0.495 R4C3B.C0 to R4C3B.F0 SLICE_122 ROUTE 4 0.453 R4C3B.F0 to R4C3B.C1 sender_impl/n1007 CTOF_DEL --- 0.495 R4C3B.C1 to R4C3B.F1 SLICE_122 ROUTE 3 1.093 R4C3B.F1 to R4C2B.LSR sender_impl/n1997 (to CLK) -------- 6.855 (35.5% logic, 64.5% route), 5 logic levels. Clock Skew Details: Source Clock Path clkgen_impl/SLICE_12 to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 93 2.843 R2C5C.Q0 to R4C7B.CLK CLK -------- 2.843 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clkgen_impl/SLICE_12 to sender_impl/SLICE_101: Name Fanout Delay (ns) Site Resource ROUTE 93 2.843 R2C5C.Q0 to R4C2B.CLK CLK -------- 2.843 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 1.204ns (weighted slack = 2.408ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q fifo_impl/o_rdy_46 (from CLK -) Destination: FF Data in sender_impl/data_count_i3 (to CLK +) Delay: 6.855ns (35.5% logic, 64.5% route), 5 logic levels. Constraint Details: 6.855ns physical path delay SLICE_17 to sender_impl/SLICE_103 meets 8.333ns delay constraint less 0.000ns skew and 0.274ns LSR_SET requirement (totaling 8.059ns) by 1.204ns Physical Path Details: Data path SLICE_17 to sender_impl/SLICE_103: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C7B.CLK to R4C7B.Q0 SLICE_17 (from CLK) ROUTE 6 1.473 R4C7B.Q0 to R5C3A.D0 O_DATA_RDY CTOF_DEL --- 0.495 R5C3A.D0 to R5C3A.F0 SLICE_127 ROUTE 4 0.651 R5C3A.F0 to R5C3A.D1 S_DATA_RDY CTOF_DEL --- 0.495 R5C3A.D1 to R5C3A.F1 SLICE_127 ROUTE 5 0.753 R5C3A.F1 to R4C3B.C0 sender_impl/n289 CTOF_DEL --- 0.495 R4C3B.C0 to R4C3B.F0 SLICE_122 ROUTE 4 0.453 R4C3B.F0 to R4C3B.C1 sender_impl/n1007 CTOF_DEL --- 0.495 R4C3B.C1 to R4C3B.F1 SLICE_122 ROUTE 3 1.093 R4C3B.F1 to R4C2A.LSR sender_impl/n1997 (to CLK) -------- 6.855 (35.5% logic, 64.5% route), 5 logic levels. Clock Skew Details: Source Clock Path clkgen_impl/SLICE_12 to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 93 2.843 R2C5C.Q0 to R4C7B.CLK CLK -------- 2.843 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clkgen_impl/SLICE_12 to sender_impl/SLICE_103: Name Fanout Delay (ns) Site Resource ROUTE 93 2.843 R2C5C.Q0 to R4C2A.CLK CLK -------- 2.843 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 1.236ns (weighted slack = 2.472ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q r_sync_req_99 (from CLK -) Destination: FF Data in clkgen_impl/clk_ph_335__i0 (to i_clk4x +) Delay: 3.636ns (39.7% logic, 60.3% route), 3 logic levels. Constraint Details: 3.636ns physical path delay SLICE_144 to clkgen_impl/SLICE_33 meets 8.333ns delay constraint less 3.295ns skew and 0.166ns DIN_SET requirement (totaling 4.872ns) by 1.236ns Physical Path Details: Data path SLICE_144 to clkgen_impl/SLICE_33: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C4D.CLK to R2C4D.Q0 SLICE_144 (from CLK) ROUTE 4 1.113 R2C4D.Q0 to R3C5C.C0 r_sync_req CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 SLICE_170 ROUTE 2 1.081 R3C5C.F0 to R2C6B.D0 clkgen_impl/SYNC_REQ CTOF_DEL --- 0.495 R2C6B.D0 to R2C6B.F0 clkgen_impl/SLICE_33 ROUTE 1 0.000 R2C6B.F0 to R2C6B.DI0 clkgen_impl/n16 (to i_clk4x) -------- 3.636 (39.7% logic, 60.3% route), 3 logic levels. Clock Skew Details: Source Clock Path CLK_4X to SLICE_144: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 20.PAD to 20.PADDI CLK_4X ROUTE 1 2.590 20.PADDI to DCM6.CLK0 CLK_4X_c MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector ROUTE 4 0.851 DCM6.DCMOUT to R2C5C.CLK i_clk4x REG_DEL --- 0.452 R2C5C.CLK to R2C5C.Q0 clkgen_impl/SLICE_12 ROUTE 93 2.843 R2C5C.Q0 to R2C4D.CLK CLK -------- 8.108 (22.5% logic, 77.5% route), 3 logic levels. Destination Clock Path CLK_4X to clkgen_impl/SLICE_33: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.372 20.PAD to 20.PADDI CLK_4X ROUTE 1 2.590 20.PADDI to DCM6.CLK0 CLK_4X_c MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector ROUTE 4 0.851 DCM6.DCMOUT to R2C6B.CLK i_clk4x -------- 4.813 (28.5% logic, 71.5% route), 2 logic levels. Passed: The following path meets requirements by 1.482ns (weighted slack = 2.964ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q fifo_impl/o_addr_337__i2 (from CLK -) Destination: FF Data in sender_impl/use_crc16_143 (to CLK +) Delay: 6.577ns (29.5% logic, 70.5% route), 4 logic levels. Constraint Details: 6.577ns physical path delay fifo_impl/SLICE_68 to SLICE_118 meets 8.333ns delay constraint less 0.000ns skew and 0.274ns LSR_SET requirement (totaling 8.059ns) by 1.482ns Physical Path Details: Data path fifo_impl/SLICE_68 to SLICE_118: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R3C8B.CLK to R3C8B.Q0 fifo_impl/SLICE_68 (from CLK) ROUTE 21 1.602 R3C8B.Q0 to R5C6A.C0 fifo_impl/o_addr_2 CTOF_DEL --- 0.495 R5C6A.C0 to R5C6A.F0 fifo_impl/mem3/SLICE_1 ROUTE 1 0.958 R5C6A.F0 to R4C5B.D1 n466 CTOF_DEL --- 0.495 R4C5B.D1 to R4C5B.F1 SLICE_131 ROUTE 3 1.095 R4C5B.F1 to R5C3C.C1 RECV_DATA_0 CTOF_DEL --- 0.495 R5C3C.C1 to R5C3C.F1 SLICE_143 ROUTE 1 0.985 R5C3C.F1 to R5C5B.LSR sender_impl/n1075 (to CLK) -------- 6.577 (29.5% logic, 70.5% route), 4 logic levels. Clock Skew Details: Source Clock Path clkgen_impl/SLICE_12 to fifo_impl/SLICE_68: Name Fanout Delay (ns) Site Resource ROUTE 93 2.843 R2C5C.Q0 to R3C8B.CLK CLK -------- 2.843 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clkgen_impl/SLICE_12 to SLICE_118: Name Fanout Delay (ns) Site Resource ROUTE 93 2.843 R2C5C.Q0 to R5C5B.CLK CLK -------- 2.843 (0.0% logic, 100.0% route), 0 logic levels. Report: 64.177MHz is the maximum frequency for this preference. ================================================================================ Preference: MULTICYCLE TO PORT "DP" 20.000000 ns ; 2 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 13.743ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q sender_impl/r_dp_145 (from CLK +) Destination: Port Pad DP Delay: 6.257ns (62.3% logic, 37.7% route), 2 logic levels. Constraint Details: 6.257ns physical path delay sender_impl/SLICE_16 to DP meets 20.000ns delay constraint by 13.743ns Physical Path Details: Data path sender_impl/SLICE_16 to DP: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R3C3A.CLK to R3C3A.Q0 sender_impl/SLICE_16 (from CLK) ROUTE 3 2.357 R3C3A.Q0 to 27.PADDO DPW DOPAD_DEL --- 3.448 27.PADDO to 27.PAD DP -------- 6.257 (62.3% logic, 37.7% route), 2 logic levels. Passed: The following path meets requirements by 14.620ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q sender_impl/r_oe_133 (from CLK +) Destination: Port Pad DP Delay: 5.380ns (95.8% logic, 4.2% route), 2 logic levels. Constraint Details: 5.380ns physical path delay DP_MGIOL to DP meets 20.000ns delay constraint by 14.620ns Physical Path Details: Data path DP_MGIOL to DP: Name Fanout Delay (ns) Site Resource C2OUT_DEL --- 0.500 IOL_T8D.CLK to IOL_T8D.IOLTO DP_MGIOL (from CLK) ROUTE 1 0.224 IOL_T8D.IOLTO to 27.IOLTO n659 TOTS_DEL --- 4.656 27.IOLTO to 27.PAD DP -------- 5.380 (95.8% logic, 4.2% route), 2 logic levels. Report: 6.257ns is the minimum delay for this preference. ================================================================================ Preference: MULTICYCLE TO PORT "DM" 20.000000 ns ; 2 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 13.880ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q sender_impl/r_dm_146 (from CLK +) Destination: Port Pad DM Delay: 6.120ns (63.7% logic, 36.3% route), 2 logic levels. Constraint Details: 6.120ns physical path delay sender_impl/SLICE_142 to DM meets 20.000ns delay constraint by 13.880ns Physical Path Details: Data path sender_impl/SLICE_142 to DM: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R3C2B.CLK to R3C2B.Q0 sender_impl/SLICE_142 (from CLK) ROUTE 1 2.220 R3C2B.Q0 to 28.PADDO DMW DOPAD_DEL --- 3.448 28.PADDO to 28.PAD DM -------- 6.120 (63.7% logic, 36.3% route), 2 logic levels. Passed: The following path meets requirements by 14.620ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q sender_impl/r_oe_133$r0 (from CLK +) Destination: Port Pad DM Delay: 5.380ns (95.8% logic, 4.2% route), 2 logic levels. Constraint Details: 5.380ns physical path delay DM_MGIOL to DM meets 20.000ns delay constraint by 14.620ns Physical Path Details: Data path DM_MGIOL to DM: Name Fanout Delay (ns) Site Resource C2OUT_DEL --- 0.500 IOL_T8C.CLK to IOL_T8C.IOLTO DM_MGIOL (from CLK) ROUTE 1 0.224 IOL_T8C.IOLTO to 28.IOLTO n659$n0 TOTS_DEL --- 4.656 28.IOLTO to 28.PAD DM -------- 5.380 (95.8% logic, 4.2% route), 2 logic levels. Report: 6.120ns is the minimum delay for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "SCK" 16.000000 MHz ; | 16.000 MHz| 130.822 MHz| 2 | | | FREQUENCY PORT "CLK_4X" 60.000000 MHz ; | 60.000 MHz| 64.177 MHz| 2 | | | MULTICYCLE TO PORT "DP" 20.000000 ns ; | 20.000 ns| 6.257 ns| 2 | | | MULTICYCLE TO PORT "DM" 20.000000 ns ; | 20.000 ns| 6.120 ns| 2 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 3 clocks: Clock Domain: CLK Source: clkgen_impl/SLICE_12.Q0 Loads: 93 Covered under: FREQUENCY PORT "CLK_4X" 60.000000 MHz ; Data transfers from: Clock Domain: SCK_c Source: SCK.PAD Not reported because source and destination domains are unrelated. Clock Domain: i_clk4x Source: clk_selector.DCMOUT Covered under: FREQUENCY PORT "CLK_4X" 60.000000 MHz ; Transfers: 1 Clock Domain: SCK_c Source: SCK.PAD Loads: 15 Covered under: FREQUENCY PORT "SCK" 16.000000 MHz ; Data transfers from: Clock Domain: CLK Source: clkgen_impl/SLICE_12.Q0 Not reported because source and destination domains are unrelated. Clock Domain: i_clk4x Source: clk_selector.DCMOUT Loads: 4 Covered under: FREQUENCY PORT "CLK_4X" 60.000000 MHz ; Data transfers from: Clock Domain: CLK Source: clkgen_impl/SLICE_12.Q0 Covered under: FREQUENCY PORT "CLK_4X" 60.000000 MHz ; Transfers: 2 Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1875 paths, 4 nets, and 1132 connections (90.3% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond_1.4_Production (87) Fri Jul 06 14:24:30 2012 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_udrv.twr qfn32samples_udrv.ncd qfn32samples_udrv.prf Design file: qfn32samples_udrv.ncd Preference file: qfn32samples_udrv.prf Device,speed: LCMXO2-256HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY PORT "SCK" 16.000000 MHz (0 errors)
  • 65 items scored, 0 timing errors detected.
  • FREQUENCY PORT "CLK_4X" 60.000000 MHz (0 errors)
  • 1800 items scored, 0 timing errors detected.
  • MULTICYCLE TO PORT "DP" 20.000000 ns (0 errors)
  • 2 items scored, 0 timing errors detected.
  • MULTICYCLE TO PORT "DM" 20.000000 ns (0 errors)
  • 2 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "SCK" 16.000000 MHz ; 65 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_spi_i1 (from SCK_c -) Destination: FF Data in spi_impl/spi_out_i0_i2 (to SCK_c -) Delay: 0.285ns (46.0% logic, 54.0% route), 1 logic levels. Constraint Details: 0.285ns physical path delay spi_impl/SLICE_114 to SLICE_171 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path spi_impl/SLICE_114 to SLICE_171: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C5D.CLK to R4C5D.Q0 spi_impl/SLICE_114 (from SCK_c) ROUTE 2 0.154 R4C5D.Q0 to R4C5C.M0 spi_impl/r_spi_1 (to SCK_c) -------- 0.285 (46.0% logic, 54.0% route), 1 logic levels. Clock Skew Details: Source Clock Path SCK to spi_impl/SLICE_114: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C5D.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to SLICE_171: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C5C.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.346ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_count_341__i0 (from SCK_c -) Destination: FF Data in spi_impl/r_count_341__i0 (to SCK_c -) Delay: 0.287ns (45.6% logic, 54.4% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_111 to SLICE_111 meets -0.059ns LSR_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.059ns) by 0.346ns Physical Path Details: Data path SLICE_111 to SLICE_111: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C9C.CLK to R4C9C.Q0 SLICE_111 (from SCK_c) ROUTE 7 0.156 R4C9C.Q0 to R4C9C.LSR spi_impl/r_count_0 (to SCK_c) -------- 0.287 (45.6% logic, 54.4% route), 1 logic levels. Clock Skew Details: Source Clock Path SCK to SLICE_111: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C9C.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to SLICE_111: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C9C.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.373ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_count_341__i2 (from SCK_c -) Destination: FF Data in spi_impl/r_count_341__i2 (to SCK_c -) Delay: 0.360ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.360ns physical path delay spi_impl/SLICE_112 to spi_impl/SLICE_112 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.373ns Physical Path Details: Data path spi_impl/SLICE_112 to spi_impl/SLICE_112: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C9D.CLK to R4C9D.Q1 spi_impl/SLICE_112 (from SCK_c) ROUTE 5 0.130 R4C9D.Q1 to R4C9D.A1 spi_impl/r_count_2 CTOF_DEL --- 0.099 R4C9D.A1 to R4C9D.F1 spi_impl/SLICE_112 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 spi_impl/n19 (to SCK_c) -------- 0.360 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path SCK to spi_impl/SLICE_112: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C9D.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to spi_impl/SLICE_112: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C9D.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.374ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_count_341__i1 (from SCK_c -) Destination: FF Data in spi_impl/r_count_341__i1 (to SCK_c -) Delay: 0.361ns (63.7% logic, 36.3% route), 2 logic levels. Constraint Details: 0.361ns physical path delay spi_impl/SLICE_112 to spi_impl/SLICE_112 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.374ns Physical Path Details: Data path spi_impl/SLICE_112 to spi_impl/SLICE_112: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C9D.CLK to R4C9D.Q0 spi_impl/SLICE_112 (from SCK_c) ROUTE 6 0.131 R4C9D.Q0 to R4C9D.A0 spi_impl/r_count_1 CTOF_DEL --- 0.099 R4C9D.A0 to R4C9D.F0 spi_impl/SLICE_112 ROUTE 1 0.000 R4C9D.F0 to R4C9D.DI0 spi_impl/n20 (to SCK_c) -------- 0.361 (63.7% logic, 36.3% route), 2 logic levels. Clock Skew Details: Source Clock Path SCK to spi_impl/SLICE_112: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C9D.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to spi_impl/SLICE_112: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C9D.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.375ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_spi_i3 (from SCK_c -) Destination: FF Data in spi_impl/r_spi_i4 (to SCK_c -) Delay: 0.362ns (63.5% logic, 36.5% route), 2 logic levels. Constraint Details: 0.362ns physical path delay spi_impl/SLICE_115 to spi_impl/SLICE_115 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.375ns Physical Path Details: Data path spi_impl/SLICE_115 to spi_impl/SLICE_115: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C5A.CLK to R4C5A.Q0 spi_impl/SLICE_115 (from SCK_c) ROUTE 2 0.132 R4C5A.Q0 to R4C5A.D1 spi_impl/r_spi_3 CTOF_DEL --- 0.099 R4C5A.D1 to R4C5A.F1 spi_impl/SLICE_115 ROUTE 1 0.000 R4C5A.F1 to R4C5A.DI1 spi_impl/n22 (to SCK_c) -------- 0.362 (63.5% logic, 36.5% route), 2 logic levels. Clock Skew Details: Source Clock Path SCK to spi_impl/SLICE_115: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C5A.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to spi_impl/SLICE_115: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C5A.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.375ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_spi_i2 (from SCK_c -) Destination: FF Data in spi_impl/r_spi_i3 (to SCK_c -) Delay: 0.362ns (63.5% logic, 36.5% route), 2 logic levels. Constraint Details: 0.362ns physical path delay spi_impl/SLICE_114 to spi_impl/SLICE_115 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.375ns Physical Path Details: Data path spi_impl/SLICE_114 to spi_impl/SLICE_115: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C5D.CLK to R4C5D.Q1 spi_impl/SLICE_114 (from SCK_c) ROUTE 2 0.132 R4C5D.Q1 to R4C5A.D0 spi_impl/r_spi_2 CTOF_DEL --- 0.099 R4C5A.D0 to R4C5A.F0 spi_impl/SLICE_115 ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 spi_impl/n23 (to SCK_c) -------- 0.362 (63.5% logic, 36.5% route), 2 logic levels. Clock Skew Details: Source Clock Path SCK to spi_impl/SLICE_114: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C5D.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to spi_impl/SLICE_115: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C5A.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.378ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_spi_i5 (from SCK_c -) Destination: FF Data in spi_impl/r_spi_i6 (to SCK_c -) Delay: 0.365ns (63.0% logic, 37.0% route), 2 logic levels. Constraint Details: 0.365ns physical path delay spi_impl/SLICE_116 to spi_impl/SLICE_116 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.378ns Physical Path Details: Data path spi_impl/SLICE_116 to spi_impl/SLICE_116: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C7D.CLK to R4C7D.Q0 spi_impl/SLICE_116 (from SCK_c) ROUTE 2 0.135 R4C7D.Q0 to R4C7D.C1 spi_impl/r_spi_5 CTOF_DEL --- 0.099 R4C7D.C1 to R4C7D.F1 spi_impl/SLICE_116 ROUTE 1 0.000 R4C7D.F1 to R4C7D.DI1 spi_impl/n20_adj_5 (to SCK_c) -------- 0.365 (63.0% logic, 37.0% route), 2 logic levels. Clock Skew Details: Source Clock Path SCK to spi_impl/SLICE_116: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C7D.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to spi_impl/SLICE_116: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C7D.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.385ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_count_341__i1 (from SCK_c -) Destination: FF Data in spi_impl/r_count_341__i2 (to SCK_c -) Delay: 0.372ns (61.8% logic, 38.2% route), 2 logic levels. Constraint Details: 0.372ns physical path delay spi_impl/SLICE_112 to spi_impl/SLICE_112 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.385ns Physical Path Details: Data path spi_impl/SLICE_112 to spi_impl/SLICE_112: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C9D.CLK to R4C9D.Q0 spi_impl/SLICE_112 (from SCK_c) ROUTE 6 0.142 R4C9D.Q0 to R4C9D.C1 spi_impl/r_count_1 CTOF_DEL --- 0.099 R4C9D.C1 to R4C9D.F1 spi_impl/SLICE_112 ROUTE 1 0.000 R4C9D.F1 to R4C9D.DI1 spi_impl/n19 (to SCK_c) -------- 0.372 (61.8% logic, 38.2% route), 2 logic levels. Clock Skew Details: Source Clock Path SCK to spi_impl/SLICE_112: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C9D.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to spi_impl/SLICE_112: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C9D.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.412ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_spi_i6 (from SCK_c -) Destination: FF Data in spi_impl/spi_out_i0_i7 (to SCK_c -) Delay: 0.393ns (33.3% logic, 66.7% route), 1 logic levels. Constraint Details: 0.393ns physical path delay spi_impl/SLICE_116 to SLICE_133 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.412ns Physical Path Details: Data path spi_impl/SLICE_116 to SLICE_133: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C7D.CLK to R4C7D.Q1 spi_impl/SLICE_116 (from SCK_c) ROUTE 2 0.262 R4C7D.Q1 to R3C7B.M1 spi_impl/r_spi_6 (to SCK_c) -------- 0.393 (33.3% logic, 66.7% route), 1 logic levels. Clock Skew Details: Source Clock Path SCK to spi_impl/SLICE_116: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C7D.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to SLICE_133: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R3C7B.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.453ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q spi_impl/r_spi_i1 (from SCK_c -) Destination: FF Data in spi_impl/r_spi_i2 (to SCK_c -) Delay: 0.440ns (52.3% logic, 47.7% route), 2 logic levels. Constraint Details: 0.440ns physical path delay spi_impl/SLICE_114 to spi_impl/SLICE_114 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.453ns Physical Path Details: Data path spi_impl/SLICE_114 to spi_impl/SLICE_114: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C5D.CLK to R4C5D.Q0 spi_impl/SLICE_114 (from SCK_c) ROUTE 2 0.210 R4C5D.Q0 to R4C5D.A1 spi_impl/r_spi_1 CTOF_DEL --- 0.099 R4C5D.A1 to R4C5D.F1 spi_impl/SLICE_114 ROUTE 1 0.000 R4C5D.F1 to R4C5D.DI1 spi_impl/n24 (to SCK_c) -------- 0.440 (52.3% logic, 47.7% route), 2 logic levels. Clock Skew Details: Source Clock Path SCK to spi_impl/SLICE_114: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C5D.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path SCK to spi_impl/SLICE_114: Name Fanout Delay (ns) Site Resource ROUTE 15 0.615 11.PADDI to R4C5D.CLK SCK_c -------- 0.615 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: FREQUENCY PORT "CLK_4X" 60.000000 MHz ; 1800 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.221ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q fifo_impl/i_addr_i0_i3 (from CLK -) Destination: FF Data in fifo_impl/mem2/RAM0 (to CLK -) FF fifo_impl/mem2/RAM0 Delay: 0.350ns (37.4% logic, 62.6% route), 2 logic levels. Constraint Details: 0.350ns physical path delay fifo_impl/SLICE_64 to SLICE_10 meets 0.129ns WAD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.221ns Physical Path Details: Data path fifo_impl/SLICE_64 to SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C7D.CLK to R2C7D.Q0 fifo_impl/SLICE_64 (from CLK) ROUTE 8 0.219 R2C7D.Q0 to R4C6C.D0 fifo_impl/i_addr_3 ZERO_DEL --- 0.000 R4C6C.D0 to R4C6C.WADO3 fifo_impl/mem2/SLICE_9 ROUTE 2 0.000 R4C6C.WADO3 to R4C6A.WAD3 fifo_impl/mem2/WAD3_INT (to CLK) -------- 0.350 (37.4% logic, 62.6% route), 2 logic levels. Clock Skew Details: Source Clock Path clkgen_impl/SLICE_12 to fifo_impl/SLICE_64: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R2C7D.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clkgen_impl/SLICE_12 to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R4C6A.WCK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.221ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q fifo_impl/i_addr_i0_i3 (from CLK -) Destination: FF Data in fifo_impl/mem2/RAM1 (to CLK -) FF fifo_impl/mem2/RAM1 Delay: 0.350ns (37.4% logic, 62.6% route), 2 logic levels. Constraint Details: 0.350ns physical path delay fifo_impl/SLICE_64 to SLICE_11 meets 0.129ns WAD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.221ns Physical Path Details: Data path fifo_impl/SLICE_64 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C7D.CLK to R2C7D.Q0 fifo_impl/SLICE_64 (from CLK) ROUTE 8 0.219 R2C7D.Q0 to R4C6C.D0 fifo_impl/i_addr_3 ZERO_DEL --- 0.000 R4C6C.D0 to R4C6C.WADO3 fifo_impl/mem2/SLICE_9 ROUTE 2 0.000 R4C6C.WADO3 to R4C6B.WAD3 fifo_impl/mem2/WAD3_INT (to CLK) -------- 0.350 (37.4% logic, 62.6% route), 2 logic levels. Clock Skew Details: Source Clock Path clkgen_impl/SLICE_12 to fifo_impl/SLICE_64: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R2C7D.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clkgen_impl/SLICE_12 to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R4C6B.WCK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.299ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q crc5s_impl/r_crc_i1 (from CLK -) Destination: FF Data in crc5s_impl/r_crc_i0 (to CLK -) Delay: 0.280ns (46.8% logic, 53.2% route), 1 logic levels. Constraint Details: 0.280ns physical path delay SLICE_146 to SLICE_146 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.299ns Physical Path Details: Data path SLICE_146 to SLICE_146: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C8B.CLK to R4C8B.Q1 SLICE_146 (from CLK) ROUTE 1 0.149 R4C8B.Q1 to R4C8B.M0 crc5s_impl/r_crc_1 (to CLK) -------- 0.280 (46.8% logic, 53.2% route), 1 logic levels. Clock Skew Details: Source Clock Path clkgen_impl/SLICE_12 to SLICE_146: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R4C8B.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clkgen_impl/SLICE_12 to SLICE_146: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R4C8B.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.299ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q crc5s_impl/r_crc_i2 (from CLK -) Destination: FF Data in crc5s_impl/r_crc_i1 (to CLK -) Delay: 0.280ns (46.8% logic, 53.2% route), 1 logic levels. Constraint Details: 0.280ns physical path delay crc5s_impl/SLICE_51 to SLICE_146 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.299ns Physical Path Details: Data path crc5s_impl/SLICE_51 to SLICE_146: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C8C.CLK to R4C8C.Q0 crc5s_impl/SLICE_51 (from CLK) ROUTE 1 0.149 R4C8C.Q0 to R4C8B.M1 crc5s_impl/r_crc_2 (to CLK) -------- 0.280 (46.8% logic, 53.2% route), 1 logic levels. Clock Skew Details: Source Clock Path clkgen_impl/SLICE_12 to crc5s_impl/SLICE_51: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R4C8C.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clkgen_impl/SLICE_12 to SLICE_146: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R4C8B.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.299ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q crc5r_impl/r_crc_i4 (from CLK -) Destination: FF Data in crc5r_impl/r_crc_i3 (to CLK -) Delay: 0.280ns (46.8% logic, 53.2% route), 1 logic levels. Constraint Details: 0.280ns physical path delay crc5r_impl/SLICE_49 to SLICE_147 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.299ns Physical Path Details: Data path crc5r_impl/SLICE_49 to SLICE_147: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C8A.CLK to R2C8A.Q0 crc5r_impl/SLICE_49 (from CLK) ROUTE 1 0.149 R2C8A.Q0 to R2C8D.M0 crc5r_impl/r_crc_4 (to CLK) -------- 0.280 (46.8% logic, 53.2% route), 1 logic levels. Clock Skew Details: Source Clock Path clkgen_impl/SLICE_12 to crc5r_impl/SLICE_49: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R2C8A.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clkgen_impl/SLICE_12 to SLICE_147: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R2C8D.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.301ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q crc16_impl/r_crc_i6 (from CLK -) Destination: FF Data in crc16_impl/r_crc_i5 (to CLK -) Delay: 0.282ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.282ns physical path delay SLICE_145 to SLICE_145 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.301ns Physical Path Details: Data path SLICE_145 to SLICE_145: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C7A.CLK to R3C7A.Q1 SLICE_145 (from CLK) ROUTE 2 0.151 R3C7A.Q1 to R3C7A.M0 crc16_impl/r_crc_6 (to CLK) -------- 0.282 (46.5% logic, 53.5% route), 1 logic levels. Clock Skew Details: Source Clock Path clkgen_impl/SLICE_12 to SLICE_145: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R3C7A.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clkgen_impl/SLICE_12 to SLICE_145: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R3C7A.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.301ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q crc16_impl/r_crc_i12 (from CLK -) Destination: FF Data in crc16_impl/r_crc_i11 (to CLK -) Delay: 0.282ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.282ns physical path delay SLICE_153 to SLICE_153 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.301ns Physical Path Details: Data path SLICE_153 to SLICE_153: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C8A.CLK to R4C8A.Q1 SLICE_153 (from CLK) ROUTE 2 0.151 R4C8A.Q1 to R4C8A.M0 crc16_impl/r_crc_12 (to CLK) -------- 0.282 (46.5% logic, 53.5% route), 1 logic levels. Clock Skew Details: Source Clock Path clkgen_impl/SLICE_12 to SLICE_153: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R4C8A.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clkgen_impl/SLICE_12 to SLICE_153: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R4C8A.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.301ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q reciever_impl/r_data__i3 (from CLK +) Destination: FF Data in reciever_impl/r_data__i2 (to CLK +) Delay: 0.282ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.282ns physical path delay SLICE_155 to SLICE_154 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.301ns Physical Path Details: Data path SLICE_155 to SLICE_154: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C3A.CLK to R4C3A.Q0 SLICE_155 (from CLK) ROUTE 2 0.151 R4C3A.Q0 to R4C3D.M1 reciever_impl/r_data_3 (to CLK) -------- 0.282 (46.5% logic, 53.5% route), 1 logic levels. Clock Skew Details: Source Clock Path clkgen_impl/SLICE_12 to SLICE_155: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R4C3A.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clkgen_impl/SLICE_12 to SLICE_154: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R4C3D.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.301ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q reciever_impl/r_data__i4 (from CLK +) Destination: FF Data in reciever_impl/r_data__i3 (to CLK +) Delay: 0.282ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.282ns physical path delay SLICE_155 to SLICE_155 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.301ns Physical Path Details: Data path SLICE_155 to SLICE_155: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C3A.CLK to R4C3A.Q1 SLICE_155 (from CLK) ROUTE 2 0.151 R4C3A.Q1 to R4C3A.M0 reciever_impl/r_data_4 (to CLK) -------- 0.282 (46.5% logic, 53.5% route), 1 logic levels. Clock Skew Details: Source Clock Path clkgen_impl/SLICE_12 to SLICE_155: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R4C3A.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clkgen_impl/SLICE_12 to SLICE_155: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R4C3A.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.301ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q crc16_impl/r_crc_i4 (from CLK -) Destination: FF Data in crc16_impl/r_crc_i3 (to CLK -) Delay: 0.282ns (46.5% logic, 53.5% route), 1 logic levels. Constraint Details: 0.282ns physical path delay SLICE_157 to SLICE_157 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.301ns Physical Path Details: Data path SLICE_157 to SLICE_157: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C8A.CLK to R3C8A.Q1 SLICE_157 (from CLK) ROUTE 2 0.151 R3C8A.Q1 to R3C8A.M0 crc16_impl/r_crc_4 (to CLK) -------- 0.282 (46.5% logic, 53.5% route), 1 logic levels. Clock Skew Details: Source Clock Path clkgen_impl/SLICE_12 to SLICE_157: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R3C8A.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clkgen_impl/SLICE_12 to SLICE_157: Name Fanout Delay (ns) Site Resource ROUTE 93 0.997 R2C5C.Q0 to R3C8A.CLK CLK -------- 0.997 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: MULTICYCLE TO PORT "DP" 20.000000 ns ; 2 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 1.048ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q sender_impl/r_oe_133 (from CLK +) Destination: Port Pad DP Delay: 1.048ns (94.7% logic, 5.3% route), 2 logic levels. Constraint Details: 1.048ns physical path delay DP_MGIOL to DP meets 0.000ns delay constraint by 1.048ns Physical Path Details: Data path DP_MGIOL to DP: Name Fanout Delay (ns) Site Resource C2OUT_DEL --- 0.150 IOL_T8D.CLK to IOL_T8D.IOLTO DP_MGIOL (from CLK) ROUTE 1 0.056 IOL_T8D.IOLTO to 27.IOLTO n659 TOTS_DEL --- 0.842 27.IOLTO to 27.PAD DP -------- 1.048 (94.7% logic, 5.3% route), 2 logic levels. Passed: The following path meets requirements by 1.662ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q sender_impl/r_dp_145 (from CLK +) Destination: Port Pad DP Delay: 1.662ns (65.5% logic, 34.5% route), 2 logic levels. Constraint Details: 1.662ns physical path delay sender_impl/SLICE_16 to DP meets 0.000ns delay constraint by 1.662ns Physical Path Details: Data path sender_impl/SLICE_16 to DP: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C3A.CLK to R3C3A.Q0 sender_impl/SLICE_16 (from CLK) ROUTE 3 0.573 R3C3A.Q0 to 27.PADDO DPW DOPAD_DEL --- 0.958 27.PADDO to 27.PAD DP -------- 1.662 (65.5% logic, 34.5% route), 2 logic levels. ================================================================================ Preference: MULTICYCLE TO PORT "DM" 20.000000 ns ; 2 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 1.048ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q sender_impl/r_oe_133$r0 (from CLK +) Destination: Port Pad DM Delay: 1.048ns (94.7% logic, 5.3% route), 2 logic levels. Constraint Details: 1.048ns physical path delay DM_MGIOL to DM meets 0.000ns delay constraint by 1.048ns Physical Path Details: Data path DM_MGIOL to DM: Name Fanout Delay (ns) Site Resource C2OUT_DEL --- 0.150 IOL_T8C.CLK to IOL_T8C.IOLTO DM_MGIOL (from CLK) ROUTE 1 0.056 IOL_T8C.IOLTO to 28.IOLTO n659$n0 TOTS_DEL --- 0.842 28.IOLTO to 28.PAD DM -------- 1.048 (94.7% logic, 5.3% route), 2 logic levels. Passed: The following path meets requirements by 1.635ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q sender_impl/r_dm_146 (from CLK +) Destination: Port Pad DM Delay: 1.635ns (66.6% logic, 33.4% route), 2 logic levels. Constraint Details: 1.635ns physical path delay sender_impl/SLICE_142 to DM meets 0.000ns delay constraint by 1.635ns Physical Path Details: Data path sender_impl/SLICE_142 to DM: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C2B.CLK to R3C2B.Q0 sender_impl/SLICE_142 (from CLK) ROUTE 1 0.546 R3C2B.Q0 to 28.PADDO DMW DOPAD_DEL --- 0.958 28.PADDO to 28.PAD DM -------- 1.635 (66.6% logic, 33.4% route), 2 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "SCK" 16.000000 MHz ; | -| -| 1 | | | FREQUENCY PORT "CLK_4X" 60.000000 MHz ; | -| -| 2 | | | MULTICYCLE TO PORT "DP" 20.000000 ns ; | -| -| 2 | | | MULTICYCLE TO PORT "DM" 20.000000 ns ; | -| -| 2 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 3 clocks: Clock Domain: CLK Source: clkgen_impl/SLICE_12.Q0 Loads: 93 Covered under: FREQUENCY PORT "CLK_4X" 60.000000 MHz ; Data transfers from: Clock Domain: SCK_c Source: SCK.PAD Not reported because source and destination domains are unrelated. Clock Domain: i_clk4x Source: clk_selector.DCMOUT Covered under: FREQUENCY PORT "CLK_4X" 60.000000 MHz ; Transfers: 1 Clock Domain: SCK_c Source: SCK.PAD Loads: 15 Covered under: FREQUENCY PORT "SCK" 16.000000 MHz ; Data transfers from: Clock Domain: CLK Source: clkgen_impl/SLICE_12.Q0 Not reported because source and destination domains are unrelated. Clock Domain: i_clk4x Source: clk_selector.DCMOUT Loads: 4 Covered under: FREQUENCY PORT "CLK_4X" 60.000000 MHz ; Data transfers from: Clock Domain: CLK Source: clkgen_impl/SLICE_12.Q0 Covered under: FREQUENCY PORT "CLK_4X" 60.000000 MHz ; Transfers: 2 Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1875 paths, 4 nets, and 1132 connections (90.3% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------