Place & Route TRACE Report

Loading design for application trce from file qfn32samples_mcpu2.ncd.
Design name: mcpu
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-256HC
Package:     TQFP100
Performance: 4
Loading device for application trce from file 'xo2c256.nph' in environment: C:/lscc/diamond/1.4/ispfpga.
Package Status:                     Final          Version 1.34
Performance Hardware Data Status:   Final)         Version 22.4
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond_1.4_Production (87)
Sun Jun 24 11:33:48 2012

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_mcpu2.twr qfn32samples_mcpu2.ncd qfn32samples_mcpu2.prf 
Design file:     qfn32samples_mcpu2.ncd
Preference file: qfn32samples_mcpu2.prf
Device,speed:    LCMXO2-256HC,4
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY PORT "CLK" 200.000000 MHz (4096 errors)
  • 4096 items scored, 4096 timing errors detected. Warning: 45.521MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "CLK" 200.000000 MHz ; 4096 items scored, 4096 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 8.484ns (weighted slack = -16.968ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 10.818ns (40.1% logic, 59.9% route), 9 logic levels. Constraint Details: 10.818ns physical path delay SLICE_13 to SLICE_19 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 8.484ns Physical Path Details: Data path SLICE_13 to SLICE_19: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R3C6A.CLK to R3C6A.Q1 SLICE_13 (from CLK_c) ROUTE 45 1.561 R3C6A.Q1 to R3C5C.B1 r_addr_1 CTOOFX_DEL --- 0.721 R3C5C.B1 to R3C5C.OFX0 rom_impl/SLICE_52 ROUTE 1 0.000 R3C5C.OFX0 to R3C5C.FXB rom_impl/mux_45_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R3C5C.FXB to R3C5C.OFX1 rom_impl/SLICE_52 ROUTE 11 1.532 R3C5C.OFX1 to R3C7A.B0 n767 CTOF_DEL --- 0.495 R3C7A.B0 to R3C7A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 1.854 R3C7A.F0 to R2C6A.B0 mem_data_0 C0TOFCO_DE --- 1.023 R2C6A.B0 to R2C6A.FCO SLICE_2 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1212 FCITOFCO_D --- 0.162 R2C6B.FCI to R2C6B.FCO SLICE_1 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1213 FCITOFCO_D --- 0.162 R2C6C.FCI to R2C6C.FCO SLICE_0 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1214 FCITOF0_DE --- 0.585 R2C6D.FCI to R2C6D.F0 SLICE_5 ROUTE 1 1.535 R2C6D.F0 to R3C6D.B1 n742 CTOF_DEL --- 0.495 R3C6D.B1 to R3C6D.F1 SLICE_19 ROUTE 1 0.000 R3C6D.F1 to R3C6D.DI1 n116 (to CLK_c) -------- 10.818 (40.1% logic, 59.9% route), 9 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6D.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 8.484ns (weighted slack = -16.968ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 10.818ns (40.1% logic, 59.9% route), 9 logic levels. Constraint Details: 10.818ns physical path delay SLICE_13 to SLICE_19 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 8.484ns Physical Path Details: Data path SLICE_13 to SLICE_19: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R3C6A.CLK to R3C6A.Q1 SLICE_13 (from CLK_c) ROUTE 45 1.561 R3C6A.Q1 to R3C5C.B0 r_addr_1 CTOOFX_DEL --- 0.721 R3C5C.B0 to R3C5C.OFX0 rom_impl/SLICE_52 ROUTE 1 0.000 R3C5C.OFX0 to R3C5C.FXB rom_impl/mux_45_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R3C5C.FXB to R3C5C.OFX1 rom_impl/SLICE_52 ROUTE 11 1.532 R3C5C.OFX1 to R3C7A.B0 n767 CTOF_DEL --- 0.495 R3C7A.B0 to R3C7A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 1.854 R3C7A.F0 to R2C6A.B0 mem_data_0 C0TOFCO_DE --- 1.023 R2C6A.B0 to R2C6A.FCO SLICE_2 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1212 FCITOFCO_D --- 0.162 R2C6B.FCI to R2C6B.FCO SLICE_1 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1213 FCITOFCO_D --- 0.162 R2C6C.FCI to R2C6C.FCO SLICE_0 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1214 FCITOF0_DE --- 0.585 R2C6D.FCI to R2C6D.F0 SLICE_5 ROUTE 1 1.535 R2C6D.F0 to R3C6D.B1 n742 CTOF_DEL --- 0.495 R3C6D.B1 to R3C6D.F1 SLICE_19 ROUTE 1 0.000 R3C6D.F1 to R3C6D.DI1 n116 (to CLK_c) -------- 10.818 (40.1% logic, 59.9% route), 9 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6D.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 8.458ns (weighted slack = -16.916ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 10.792ns (40.2% logic, 59.8% route), 9 logic levels. Constraint Details: 10.792ns physical path delay SLICE_13 to SLICE_19 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 8.458ns Physical Path Details: Data path SLICE_13 to SLICE_19: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R3C6A.CLK to R3C6A.Q0 SLICE_13 (from CLK_c) ROUTE 27 1.941 R3C6A.Q0 to R3C8D.A1 r_addr_0 CTOOFX_DEL --- 0.721 R3C8D.A1 to R3C8D.OFX0 i729/SLICE_37 ROUTE 1 0.000 R3C8D.OFX0 to R3C8C.FXA n1330 FXTOOFX_DE --- 0.241 R3C8C.FXA to R3C8C.OFX1 i730/SLICE_33 ROUTE 12 1.126 R3C8C.OFX1 to R3C7A.D0 n765 CTOF_DEL --- 0.495 R3C7A.D0 to R3C7A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 1.854 R3C7A.F0 to R2C6A.B0 mem_data_0 C0TOFCO_DE --- 1.023 R2C6A.B0 to R2C6A.FCO SLICE_2 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1212 FCITOFCO_D --- 0.162 R2C6B.FCI to R2C6B.FCO SLICE_1 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1213 FCITOFCO_D --- 0.162 R2C6C.FCI to R2C6C.FCO SLICE_0 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1214 FCITOF0_DE --- 0.585 R2C6D.FCI to R2C6D.F0 SLICE_5 ROUTE 1 1.535 R2C6D.F0 to R3C6D.B1 n742 CTOF_DEL --- 0.495 R3C6D.B1 to R3C6D.F1 SLICE_19 ROUTE 1 0.000 R3C6D.F1 to R3C6D.DI1 n116 (to CLK_c) -------- 10.792 (40.2% logic, 59.8% route), 9 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6D.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 8.458ns (weighted slack = -16.916ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 10.792ns (40.2% logic, 59.8% route), 9 logic levels. Constraint Details: 10.792ns physical path delay SLICE_13 to SLICE_19 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 8.458ns Physical Path Details: Data path SLICE_13 to SLICE_19: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R3C6A.CLK to R3C6A.Q0 SLICE_13 (from CLK_c) ROUTE 27 1.941 R3C6A.Q0 to R3C8D.A0 r_addr_0 CTOOFX_DEL --- 0.721 R3C8D.A0 to R3C8D.OFX0 i729/SLICE_37 ROUTE 1 0.000 R3C8D.OFX0 to R3C8C.FXA n1330 FXTOOFX_DE --- 0.241 R3C8C.FXA to R3C8C.OFX1 i730/SLICE_33 ROUTE 12 1.126 R3C8C.OFX1 to R3C7A.D0 n765 CTOF_DEL --- 0.495 R3C7A.D0 to R3C7A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 1.854 R3C7A.F0 to R2C6A.B0 mem_data_0 C0TOFCO_DE --- 1.023 R2C6A.B0 to R2C6A.FCO SLICE_2 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1212 FCITOFCO_D --- 0.162 R2C6B.FCI to R2C6B.FCO SLICE_1 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1213 FCITOFCO_D --- 0.162 R2C6C.FCI to R2C6C.FCO SLICE_0 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1214 FCITOF0_DE --- 0.585 R2C6D.FCI to R2C6D.F0 SLICE_5 ROUTE 1 1.535 R2C6D.F0 to R3C6D.B1 n742 CTOF_DEL --- 0.495 R3C6D.B1 to R3C6D.F1 SLICE_19 ROUTE 1 0.000 R3C6D.F1 to R3C6D.DI1 n116 (to CLK_c) -------- 10.792 (40.2% logic, 59.8% route), 9 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6D.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 8.454ns (weighted slack = -16.908ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 10.788ns (40.2% logic, 59.8% route), 9 logic levels. Constraint Details: 10.788ns physical path delay SLICE_13 to SLICE_19 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 8.454ns Physical Path Details: Data path SLICE_13 to SLICE_19: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R3C6A.CLK to R3C6A.Q1 SLICE_13 (from CLK_c) ROUTE 45 1.561 R3C6A.Q1 to R3C5A.B1 r_addr_1 CTOOFX_DEL --- 0.721 R3C5A.B1 to R3C5A.OFX0 rom_impl/SLICE_42 ROUTE 1 0.000 R3C5A.OFX0 to R3C5A.FXB rom_impl/mux_45_Mux_0_1_f5b FXTOOFX_DE --- 0.241 R3C5A.FXB to R3C5A.OFX1 rom_impl/SLICE_42 ROUTE 11 1.502 R3C5A.OFX1 to R3C7A.A0 O_ADDR_c CTOF_DEL --- 0.495 R3C7A.A0 to R3C7A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 1.854 R3C7A.F0 to R2C6A.B0 mem_data_0 C0TOFCO_DE --- 1.023 R2C6A.B0 to R2C6A.FCO SLICE_2 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1212 FCITOFCO_D --- 0.162 R2C6B.FCI to R2C6B.FCO SLICE_1 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1213 FCITOFCO_D --- 0.162 R2C6C.FCI to R2C6C.FCO SLICE_0 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1214 FCITOF0_DE --- 0.585 R2C6D.FCI to R2C6D.F0 SLICE_5 ROUTE 1 1.535 R2C6D.F0 to R3C6D.B1 n742 CTOF_DEL --- 0.495 R3C6D.B1 to R3C6D.F1 SLICE_19 ROUTE 1 0.000 R3C6D.F1 to R3C6D.DI1 n116 (to CLK_c) -------- 10.788 (40.2% logic, 59.8% route), 9 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6D.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 8.454ns (weighted slack = -16.908ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 10.788ns (40.2% logic, 59.8% route), 9 logic levels. Constraint Details: 10.788ns physical path delay SLICE_13 to SLICE_19 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 8.454ns Physical Path Details: Data path SLICE_13 to SLICE_19: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R3C6A.CLK to R3C6A.Q1 SLICE_13 (from CLK_c) ROUTE 45 1.561 R3C6A.Q1 to R3C5A.B0 r_addr_1 CTOOFX_DEL --- 0.721 R3C5A.B0 to R3C5A.OFX0 rom_impl/SLICE_42 ROUTE 1 0.000 R3C5A.OFX0 to R3C5A.FXB rom_impl/mux_45_Mux_0_1_f5b FXTOOFX_DE --- 0.241 R3C5A.FXB to R3C5A.OFX1 rom_impl/SLICE_42 ROUTE 11 1.502 R3C5A.OFX1 to R3C7A.A0 O_ADDR_c CTOF_DEL --- 0.495 R3C7A.A0 to R3C7A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 1.854 R3C7A.F0 to R2C6A.B0 mem_data_0 C0TOFCO_DE --- 1.023 R2C6A.B0 to R2C6A.FCO SLICE_2 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1212 FCITOFCO_D --- 0.162 R2C6B.FCI to R2C6B.FCO SLICE_1 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1213 FCITOFCO_D --- 0.162 R2C6C.FCI to R2C6C.FCO SLICE_0 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1214 FCITOF0_DE --- 0.585 R2C6D.FCI to R2C6D.F0 SLICE_5 ROUTE 1 1.535 R2C6D.F0 to R3C6D.B1 n742 CTOF_DEL --- 0.495 R3C6D.B1 to R3C6D.F1 SLICE_19 ROUTE 1 0.000 R3C6D.F1 to R3C6D.DI1 n116 (to CLK_c) -------- 10.788 (40.2% logic, 59.8% route), 9 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6D.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 8.432ns (weighted slack = -16.864ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 10.766ns (40.3% logic, 59.7% route), 9 logic levels. Constraint Details: 10.766ns physical path delay SLICE_13 to SLICE_19 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 8.432ns Physical Path Details: Data path SLICE_13 to SLICE_19: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R3C6A.CLK to R3C6A.Q0 SLICE_13 (from CLK_c) ROUTE 27 1.915 R3C6A.Q0 to R3C8C.A1 r_addr_0 CTOOFX_DEL --- 0.721 R3C8C.A1 to R3C8C.OFX0 i730/SLICE_33 ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.FXB n1331 FXTOOFX_DE --- 0.241 R3C8C.FXB to R3C8C.OFX1 i730/SLICE_33 ROUTE 12 1.126 R3C8C.OFX1 to R3C7A.D0 n765 CTOF_DEL --- 0.495 R3C7A.D0 to R3C7A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 1.854 R3C7A.F0 to R2C6A.B0 mem_data_0 C0TOFCO_DE --- 1.023 R2C6A.B0 to R2C6A.FCO SLICE_2 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1212 FCITOFCO_D --- 0.162 R2C6B.FCI to R2C6B.FCO SLICE_1 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1213 FCITOFCO_D --- 0.162 R2C6C.FCI to R2C6C.FCO SLICE_0 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1214 FCITOF0_DE --- 0.585 R2C6D.FCI to R2C6D.F0 SLICE_5 ROUTE 1 1.535 R2C6D.F0 to R3C6D.B1 n742 CTOF_DEL --- 0.495 R3C6D.B1 to R3C6D.F1 SLICE_19 ROUTE 1 0.000 R3C6D.F1 to R3C6D.DI1 n116 (to CLK_c) -------- 10.766 (40.3% logic, 59.7% route), 9 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6D.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 8.432ns (weighted slack = -16.864ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 10.766ns (40.3% logic, 59.7% route), 9 logic levels. Constraint Details: 10.766ns physical path delay SLICE_13 to SLICE_19 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 8.432ns Physical Path Details: Data path SLICE_13 to SLICE_19: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R3C6A.CLK to R3C6A.Q0 SLICE_13 (from CLK_c) ROUTE 27 1.915 R3C6A.Q0 to R3C8C.A0 r_addr_0 CTOOFX_DEL --- 0.721 R3C8C.A0 to R3C8C.OFX0 i730/SLICE_33 ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.FXB n1331 FXTOOFX_DE --- 0.241 R3C8C.FXB to R3C8C.OFX1 i730/SLICE_33 ROUTE 12 1.126 R3C8C.OFX1 to R3C7A.D0 n765 CTOF_DEL --- 0.495 R3C7A.D0 to R3C7A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 1.854 R3C7A.F0 to R2C6A.B0 mem_data_0 C0TOFCO_DE --- 1.023 R2C6A.B0 to R2C6A.FCO SLICE_2 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1212 FCITOFCO_D --- 0.162 R2C6B.FCI to R2C6B.FCO SLICE_1 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1213 FCITOFCO_D --- 0.162 R2C6C.FCI to R2C6C.FCO SLICE_0 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1214 FCITOF0_DE --- 0.585 R2C6D.FCI to R2C6D.F0 SLICE_5 ROUTE 1 1.535 R2C6D.F0 to R3C6D.B1 n742 CTOF_DEL --- 0.495 R3C6D.B1 to R3C6D.F1 SLICE_19 ROUTE 1 0.000 R3C6D.F1 to R3C6D.DI1 n116 (to CLK_c) -------- 10.766 (40.3% logic, 59.7% route), 9 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6D.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 8.356ns (weighted slack = -16.712ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i6 (from CLK_c -) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 10.690ns (37.3% logic, 62.7% route), 9 logic levels. Constraint Details: 10.690ns physical path delay rom_impl/SLICE_29 to SLICE_19 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 8.356ns Physical Path Details: Data path rom_impl/SLICE_29 to SLICE_19: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R3C7D.CLK to R3C7D.Q1 rom_impl/SLICE_29 (from CLK_c) ROUTE 18 1.808 R3C7D.Q1 to R3C5A.M0 r_addr_5 MTOOFX_DEL --- 0.376 R3C5A.M0 to R3C5A.OFX0 rom_impl/SLICE_42 ROUTE 1 0.000 R3C5A.OFX0 to R3C5A.FXB rom_impl/mux_45_Mux_0_1_f5b FXTOOFX_DE --- 0.241 R3C5A.FXB to R3C5A.OFX1 rom_impl/SLICE_42 ROUTE 11 1.502 R3C5A.OFX1 to R3C7A.A0 O_ADDR_c CTOF_DEL --- 0.495 R3C7A.A0 to R3C7A.F0 sram_impl/mem1/SLICE_10 ROUTE 2 1.854 R3C7A.F0 to R2C6A.B0 mem_data_0 C0TOFCO_DE --- 1.023 R2C6A.B0 to R2C6A.FCO SLICE_2 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1212 FCITOFCO_D --- 0.162 R2C6B.FCI to R2C6B.FCO SLICE_1 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1213 FCITOFCO_D --- 0.162 R2C6C.FCI to R2C6C.FCO SLICE_0 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1214 FCITOF0_DE --- 0.585 R2C6D.FCI to R2C6D.F0 SLICE_5 ROUTE 1 1.535 R2C6D.F0 to R3C6D.B1 n742 CTOF_DEL --- 0.495 R3C6D.B1 to R3C6D.F1 SLICE_19 ROUTE 1 0.000 R3C6D.F1 to R3C6D.DI1 n116 (to CLK_c) -------- 10.690 (37.3% logic, 62.7% route), 9 logic levels. Clock Skew Details: Source Clock Path CLK to rom_impl/SLICE_29: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C7D.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6D.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 8.354ns (weighted slack = -16.708ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in akku_i7 (to CLK_c +) Delay: 10.688ns (39.1% logic, 60.9% route), 8 logic levels. Constraint Details: 10.688ns physical path delay SLICE_13 to SLICE_19 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 8.354ns Physical Path Details: Data path SLICE_13 to SLICE_19: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R3C6A.CLK to R3C6A.Q1 SLICE_13 (from CLK_c) ROUTE 45 1.561 R3C6A.Q1 to R3C5C.B1 r_addr_1 CTOOFX_DEL --- 0.721 R3C5C.B1 to R3C5C.OFX0 rom_impl/SLICE_52 ROUTE 1 0.000 R3C5C.OFX0 to R3C5C.FXB rom_impl/mux_45_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R3C5C.FXB to R3C5C.OFX1 rom_impl/SLICE_52 ROUTE 11 1.532 R3C5C.OFX1 to R3C7B.B0 n767 CTOF_DEL --- 0.495 R3C7B.B0 to R3C7B.F0 sram_impl/mem1/SLICE_11 ROUTE 2 1.886 R3C7B.F0 to R2C6B.B0 mem_data_2 C0TOFCO_DE --- 1.023 R2C6B.B0 to R2C6B.FCO SLICE_1 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1213 FCITOFCO_D --- 0.162 R2C6C.FCI to R2C6C.FCO SLICE_0 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1214 FCITOF0_DE --- 0.585 R2C6D.FCI to R2C6D.F0 SLICE_5 ROUTE 1 1.535 R2C6D.F0 to R3C6D.B1 n742 CTOF_DEL --- 0.495 R3C6D.B1 to R3C6D.F1 SLICE_19 ROUTE 1 0.000 R3C6D.F1 to R3C6D.DI1 n116 (to CLK_c) -------- 10.688 (39.1% logic, 60.9% route), 8 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6D.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Warning: 45.521MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "CLK" 200.000000 MHz ; | 200.000 MHz| 45.521 MHz| 9 * | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- n1213 | 1| 1540| 37.60% | | | n1214 | 1| 1386| 33.84% | | | n1212 | 1| 1078| 26.32% | | | n765 | 12| 988| 24.12% | | | n766 | 11| 969| 23.66% | | | n767 | 11| 969| 23.66% | | | O_ADDR_c | 11| 969| 23.66% | | | r_addr_1 | 45| 850| 20.75% | | | r_addr_2 | 44| 850| 20.75% | | | r_addr_3 | 45| 850| 20.75% | | | r_addr_4 | 37| 736| 17.97% | | | mem_data_0 | 2| 693| 16.92% | | | mem_data_1 | 2| 693| 16.92% | | | n115 | 1| 693| 16.92% | | | n1215 | 1| 616| 15.04% | | | n741 | 1| 616| 15.04% | | | mem_data_2 | 2| 616| 15.04% | | | n749 | 1| 616| 15.04% | | | n116 | 1| 616| 15.04% | | | n742 | 1| 539| 13.16% | | | mem_data_3 | 2| 539| 13.16% | | | n117 | 1| 539| 13.16% | | | n1331 | 1| 468| 11.43% | | | n1330 | 1| 468| 11.43% | | | n118 | 1| 462| 11.28% | | | mem_data_4 | 2| 462| 11.28% | | | n743 | 1| 462| 11.28% | | | rom_impl/mux_45_Mux_1_1_f5b | 1| 459| 11.21% | | | rom_impl/mux_45_Mux_1_0_f5a | 1| 459| 11.21% | | | rom_impl/mux_45_Mux_2_1_f5b | 1| 459| 11.21% | | | rom_impl/mux_45_Mux_2_0_f5a | 1| 459| 11.21% | | | rom_impl/mux_45_Mux_0_1_f5b | 1| 459| 11.21% | | | rom_impl/mux_45_Mux_0_0_f5a | 1| 459| 11.21% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: CLK_c Source: CLK.PAD Loads: 16 Covered under: FREQUENCY PORT "CLK" 200.000000 MHz ; Data transfers from: Clock Domain: WE_mem Source: SLICE_53.F1 Covered under: FREQUENCY PORT "CLK" 200.000000 MHz ; Transfers: 8 Clock Domain: WE_mem Source: SLICE_53.F1 Loads: 4 No transfer within this clock domain is found Data transfers from: Clock Domain: CLK_c Source: CLK.PAD Covered under: FREQUENCY PORT "CLK" 200.000000 MHz ; Transfers: 14 Timing summary (Setup): --------------- Timing errors: 4096 Score: 47015140 Cumulative negative slack: 23745764 Constraints cover 4606 paths, 7 nets, and 497 connections (94.5% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond_1.4_Production (87) Sun Jun 24 11:33:49 2012 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_mcpu2.twr qfn32samples_mcpu2.ncd qfn32samples_mcpu2.prf Design file: qfn32samples_mcpu2.ncd Preference file: qfn32samples_mcpu2.prf Device,speed: LCMXO2-256HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY PORT "CLK" 200.000000 MHz (12 errors)
  • 4096 items scored, 12 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "CLK" 200.000000 MHz ; 4096 items scored, 12 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 2.858ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i1 (from CLK_c +) Destination: FF Data in sram_impl/mem1/RAM0 (to WE_mem +) FF sram_impl/mem1/RAM0 Delay: 0.341ns (38.4% logic, 61.6% route), 2 logic levels. Constraint Details: 0.341ns physical path delay SLICE_15 to sram_impl/mem1/SLICE_10 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.070ns skew requirement (totaling 3.199ns) by 2.858ns Physical Path Details: Data path SLICE_15 to sram_impl/mem1/SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C7C.CLK to R2C7C.Q0 SLICE_15 (from CLK_c) ROUTE 4 0.210 R2C7C.Q0 to R3C7C.A1 O_DATA_c ZERO_DEL --- 0.000 R3C7C.A1 to R3C7C.WDO0 sram_impl/mem1/SLICE_9 ROUTE 1 0.000 R3C7C.WDO0 to R3C7A.WD0 sram_impl/mem1/WD0_INT (to WE_mem) -------- 0.341 (38.4% logic, 61.6% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_15: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C7C.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_10: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C6A.CLK CLK_c REG_DEL --- 0.151 R3C6A.CLK to R3C6A.Q0 SLICE_13 ROUTE 27 0.523 R3C6A.Q0 to R4C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R4C6D.B0 to R4C6D.OFX0 SLICE_39 ROUTE 1 0.000 R4C6D.OFX0 to R4C6C.FXA n1336 FXTOOFX_DE --- 0.098 R4C6C.FXA to R4C6C.OFX1 SLICE_40 ROUTE 1 0.316 R4C6C.OFX1 to R5C6B.B0 n15_adj_5 CTOOFX_DEL --- 0.267 R5C6B.B0 to R5C6B.OFX0 SLICE_30 ROUTE 1 0.000 R5C6B.OFX0 to R5C6A.FXA n1327 FXTOOFX_DE --- 0.098 R5C6A.FXA to R5C6A.OFX1 i724/SLICE_38 ROUTE 3 0.581 R5C6A.OFX1 to R4C4B.B1 n763 CTOF_DEL --- 0.174 R4C4B.B1 to R4C4B.F1 SLICE_53 ROUTE 4 0.595 R4C4B.F1 to R3C7A.WCK WE_mem -------- 4.124 (36.2% logic, 63.8% route), 7 logic levels. Error: The following path exceeds requirements by 2.823ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i4 (from CLK_c +) Destination: FF Data in sram_impl/mem1/RAM1 (to WE_mem +) FF sram_impl/mem1/RAM1 Delay: 0.376ns (34.8% logic, 65.2% route), 2 logic levels. Constraint Details: 0.376ns physical path delay SLICE_21 to sram_impl/mem1/SLICE_11 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.070ns skew requirement (totaling 3.199ns) by 2.823ns Physical Path Details: Data path SLICE_21 to sram_impl/mem1/SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C7B.CLK to R2C7B.Q0 SLICE_21 (from CLK_c) ROUTE 4 0.245 R2C7B.Q0 to R3C7C.D1 n772 ZERO_DEL --- 0.000 R3C7C.D1 to R3C7C.WDO3 sram_impl/mem1/SLICE_9 ROUTE 1 0.000 R3C7C.WDO3 to R3C7B.WD1 sram_impl/mem1/WD3_INT (to WE_mem) -------- 0.376 (34.8% logic, 65.2% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_21: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C7B.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_11: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C6A.CLK CLK_c REG_DEL --- 0.151 R3C6A.CLK to R3C6A.Q0 SLICE_13 ROUTE 27 0.523 R3C6A.Q0 to R4C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R4C6D.B0 to R4C6D.OFX0 SLICE_39 ROUTE 1 0.000 R4C6D.OFX0 to R4C6C.FXA n1336 FXTOOFX_DE --- 0.098 R4C6C.FXA to R4C6C.OFX1 SLICE_40 ROUTE 1 0.316 R4C6C.OFX1 to R5C6B.B0 n15_adj_5 CTOOFX_DEL --- 0.267 R5C6B.B0 to R5C6B.OFX0 SLICE_30 ROUTE 1 0.000 R5C6B.OFX0 to R5C6A.FXA n1327 FXTOOFX_DE --- 0.098 R5C6A.FXA to R5C6A.OFX1 i724/SLICE_38 ROUTE 3 0.581 R5C6A.OFX1 to R4C4B.B1 n763 CTOF_DEL --- 0.174 R4C4B.B1 to R4C4B.F1 SLICE_53 ROUTE 4 0.595 R4C4B.F1 to R3C7B.WCK WE_mem -------- 4.124 (36.2% logic, 63.8% route), 7 logic levels. Error: The following path exceeds requirements by 2.820ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i3 (from CLK_c +) Destination: FF Data in sram_impl/mem1/RAM1 (to WE_mem +) FF sram_impl/mem1/RAM1 Delay: 0.379ns (34.6% logic, 65.4% route), 2 logic levels. Constraint Details: 0.379ns physical path delay SLICE_21 to sram_impl/mem1/SLICE_11 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.070ns skew requirement (totaling 3.199ns) by 2.820ns Physical Path Details: Data path SLICE_21 to sram_impl/mem1/SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C7B.CLK to R2C7B.Q1 SLICE_21 (from CLK_c) ROUTE 4 0.248 R2C7B.Q1 to R3C7C.C1 n773 ZERO_DEL --- 0.000 R3C7C.C1 to R3C7C.WDO2 sram_impl/mem1/SLICE_9 ROUTE 1 0.000 R3C7C.WDO2 to R3C7B.WD0 sram_impl/mem1/WD2_INT (to WE_mem) -------- 0.379 (34.6% logic, 65.4% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_21: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C7B.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_11: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C6A.CLK CLK_c REG_DEL --- 0.151 R3C6A.CLK to R3C6A.Q0 SLICE_13 ROUTE 27 0.523 R3C6A.Q0 to R4C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R4C6D.B0 to R4C6D.OFX0 SLICE_39 ROUTE 1 0.000 R4C6D.OFX0 to R4C6C.FXA n1336 FXTOOFX_DE --- 0.098 R4C6C.FXA to R4C6C.OFX1 SLICE_40 ROUTE 1 0.316 R4C6C.OFX1 to R5C6B.B0 n15_adj_5 CTOOFX_DEL --- 0.267 R5C6B.B0 to R5C6B.OFX0 SLICE_30 ROUTE 1 0.000 R5C6B.OFX0 to R5C6A.FXA n1327 FXTOOFX_DE --- 0.098 R5C6A.FXA to R5C6A.OFX1 i724/SLICE_38 ROUTE 3 0.581 R5C6A.OFX1 to R4C4B.B1 n763 CTOF_DEL --- 0.174 R4C4B.B1 to R4C4B.F1 SLICE_53 ROUTE 4 0.595 R4C4B.F1 to R3C7B.WCK WE_mem -------- 4.124 (36.2% logic, 63.8% route), 7 logic levels. Error: The following path exceeds requirements by 2.787ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i8 (from CLK_c +) Destination: FF Data in sram_impl/mem0/RAM1 (to WE_mem +) FF sram_impl/mem0/RAM1 Delay: 0.264ns (49.6% logic, 50.4% route), 2 logic levels. Constraint Details: 0.264ns physical path delay SLICE_19 to SLICE_14 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -2.922ns skew requirement (totaling 3.051ns) by 2.787ns Physical Path Details: Data path SLICE_19 to SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C6D.CLK to R3C6D.Q0 SLICE_19 (from CLK_c) ROUTE 4 0.133 R3C6D.Q0 to R3C6C.D1 n768 ZERO_DEL --- 0.000 R3C6C.D1 to R3C6C.WDO3 sram_impl/mem0/SLICE_12 ROUTE 1 0.000 R3C6C.WDO3 to R3C6B.WD1 sram_impl/mem0/WD3_INT (to WE_mem) -------- 0.264 (49.6% logic, 50.4% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_19: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C6D.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to SLICE_14: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C6A.CLK CLK_c REG_DEL --- 0.151 R3C6A.CLK to R3C6A.Q0 SLICE_13 ROUTE 27 0.523 R3C6A.Q0 to R4C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R4C6D.B0 to R4C6D.OFX0 SLICE_39 ROUTE 1 0.000 R4C6D.OFX0 to R4C6C.FXA n1336 FXTOOFX_DE --- 0.098 R4C6C.FXA to R4C6C.OFX1 SLICE_40 ROUTE 1 0.316 R4C6C.OFX1 to R5C6B.B0 n15_adj_5 CTOOFX_DEL --- 0.267 R5C6B.B0 to R5C6B.OFX0 SLICE_30 ROUTE 1 0.000 R5C6B.OFX0 to R5C6A.FXA n1327 FXTOOFX_DE --- 0.098 R5C6A.FXA to R5C6A.OFX1 i724/SLICE_38 ROUTE 3 0.581 R5C6A.OFX1 to R4C4B.B1 n763 CTOF_DEL --- 0.174 R4C4B.B1 to R4C4B.F1 SLICE_53 ROUTE 4 0.447 R4C4B.F1 to R3C6B.WCK WE_mem -------- 3.976 (37.6% logic, 62.4% route), 7 logic levels. Error: The following path exceeds requirements by 2.783ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i7 (from CLK_c +) Destination: FF Data in sram_impl/mem0/RAM1 (to WE_mem +) FF sram_impl/mem0/RAM1 Delay: 0.268ns (48.9% logic, 51.1% route), 2 logic levels. Constraint Details: 0.268ns physical path delay SLICE_19 to SLICE_14 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -2.922ns skew requirement (totaling 3.051ns) by 2.783ns Physical Path Details: Data path SLICE_19 to SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C6D.CLK to R3C6D.Q1 SLICE_19 (from CLK_c) ROUTE 4 0.137 R3C6D.Q1 to R3C6C.C1 n769 ZERO_DEL --- 0.000 R3C6C.C1 to R3C6C.WDO2 sram_impl/mem0/SLICE_12 ROUTE 1 0.000 R3C6C.WDO2 to R3C6B.WD0 sram_impl/mem0/WD2_INT (to WE_mem) -------- 0.268 (48.9% logic, 51.1% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_19: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C6D.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to SLICE_14: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C6A.CLK CLK_c REG_DEL --- 0.151 R3C6A.CLK to R3C6A.Q0 SLICE_13 ROUTE 27 0.523 R3C6A.Q0 to R4C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R4C6D.B0 to R4C6D.OFX0 SLICE_39 ROUTE 1 0.000 R4C6D.OFX0 to R4C6C.FXA n1336 FXTOOFX_DE --- 0.098 R4C6C.FXA to R4C6C.OFX1 SLICE_40 ROUTE 1 0.316 R4C6C.OFX1 to R5C6B.B0 n15_adj_5 CTOOFX_DEL --- 0.267 R5C6B.B0 to R5C6B.OFX0 SLICE_30 ROUTE 1 0.000 R5C6B.OFX0 to R5C6A.FXA n1327 FXTOOFX_DE --- 0.098 R5C6A.FXA to R5C6A.OFX1 i724/SLICE_38 ROUTE 3 0.581 R5C6A.OFX1 to R4C4B.B1 n763 CTOF_DEL --- 0.174 R4C4B.B1 to R4C4B.F1 SLICE_53 ROUTE 4 0.447 R4C4B.F1 to R3C6B.WCK WE_mem -------- 3.976 (37.6% logic, 62.4% route), 7 logic levels. Error: The following path exceeds requirements by 2.736ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i2 (from CLK_c +) Destination: FF Data in sram_impl/mem1/RAM0 (to WE_mem +) FF sram_impl/mem1/RAM0 Delay: 0.463ns (28.3% logic, 71.7% route), 2 logic levels. Constraint Details: 0.463ns physical path delay SLICE_22 to sram_impl/mem1/SLICE_10 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.070ns skew requirement (totaling 3.199ns) by 2.736ns Physical Path Details: Data path SLICE_22 to sram_impl/mem1/SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C7D.CLK to R2C7D.Q0 SLICE_22 (from CLK_c) ROUTE 4 0.332 R2C7D.Q0 to R3C7C.B1 n774 ZERO_DEL --- 0.000 R3C7C.B1 to R3C7C.WDO1 sram_impl/mem1/SLICE_9 ROUTE 1 0.000 R3C7C.WDO1 to R3C7A.WD1 sram_impl/mem1/WD1_INT (to WE_mem) -------- 0.463 (28.3% logic, 71.7% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_22: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C7D.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_10: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C6A.CLK CLK_c REG_DEL --- 0.151 R3C6A.CLK to R3C6A.Q0 SLICE_13 ROUTE 27 0.523 R3C6A.Q0 to R4C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R4C6D.B0 to R4C6D.OFX0 SLICE_39 ROUTE 1 0.000 R4C6D.OFX0 to R4C6C.FXA n1336 FXTOOFX_DE --- 0.098 R4C6C.FXA to R4C6C.OFX1 SLICE_40 ROUTE 1 0.316 R4C6C.OFX1 to R5C6B.B0 n15_adj_5 CTOOFX_DEL --- 0.267 R5C6B.B0 to R5C6B.OFX0 SLICE_30 ROUTE 1 0.000 R5C6B.OFX0 to R5C6A.FXA n1327 FXTOOFX_DE --- 0.098 R5C6A.FXA to R5C6A.OFX1 i724/SLICE_38 ROUTE 3 0.581 R5C6A.OFX1 to R4C4B.B1 n763 CTOF_DEL --- 0.174 R4C4B.B1 to R4C4B.F1 SLICE_53 ROUTE 4 0.595 R4C4B.F1 to R3C7A.WCK WE_mem -------- 4.124 (36.2% logic, 63.8% route), 7 logic levels. Error: The following path exceeds requirements by 2.709ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i5 (from CLK_c +) Destination: FF Data in sram_impl/mem0/RAM0 (to WE_mem +) FF sram_impl/mem0/RAM0 Delay: 0.342ns (38.3% logic, 61.7% route), 2 logic levels. Constraint Details: 0.342ns physical path delay SLICE_20 to SLICE_13 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -2.922ns skew requirement (totaling 3.051ns) by 2.709ns Physical Path Details: Data path SLICE_20 to SLICE_13: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C6B.CLK to R4C6B.Q1 SLICE_20 (from CLK_c) ROUTE 4 0.211 R4C6B.Q1 to R3C6C.A1 n771 ZERO_DEL --- 0.000 R3C6C.A1 to R3C6C.WDO0 sram_impl/mem0/SLICE_12 ROUTE 1 0.000 R3C6C.WDO0 to R3C6A.WD0 sram_impl/mem0/WD0_INT (to WE_mem) -------- 0.342 (38.3% logic, 61.7% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_20: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R4C6B.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C6A.CLK CLK_c REG_DEL --- 0.151 R3C6A.CLK to R3C6A.Q0 SLICE_13 ROUTE 27 0.523 R3C6A.Q0 to R4C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R4C6D.B0 to R4C6D.OFX0 SLICE_39 ROUTE 1 0.000 R4C6D.OFX0 to R4C6C.FXA n1336 FXTOOFX_DE --- 0.098 R4C6C.FXA to R4C6C.OFX1 SLICE_40 ROUTE 1 0.316 R4C6C.OFX1 to R5C6B.B0 n15_adj_5 CTOOFX_DEL --- 0.267 R5C6B.B0 to R5C6B.OFX0 SLICE_30 ROUTE 1 0.000 R5C6B.OFX0 to R5C6A.FXA n1327 FXTOOFX_DE --- 0.098 R5C6A.FXA to R5C6A.OFX1 i724/SLICE_38 ROUTE 3 0.581 R5C6A.OFX1 to R4C4B.B1 n763 CTOF_DEL --- 0.174 R4C4B.B1 to R4C4B.F1 SLICE_53 ROUTE 4 0.447 R4C4B.F1 to R3C6A.WCK WE_mem -------- 3.976 (37.6% logic, 62.4% route), 7 logic levels. Error: The following path exceeds requirements by 2.695ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i6 (from CLK_c +) Destination: FF Data in sram_impl/mem0/RAM0 (to WE_mem +) FF sram_impl/mem0/RAM0 Delay: 0.356ns (36.8% logic, 63.2% route), 2 logic levels. Constraint Details: 0.356ns physical path delay SLICE_20 to SLICE_13 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -2.922ns skew requirement (totaling 3.051ns) by 2.695ns Physical Path Details: Data path SLICE_20 to SLICE_13: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C6B.CLK to R4C6B.Q0 SLICE_20 (from CLK_c) ROUTE 4 0.225 R4C6B.Q0 to R3C6C.B1 n770 ZERO_DEL --- 0.000 R3C6C.B1 to R3C6C.WDO1 sram_impl/mem0/SLICE_12 ROUTE 1 0.000 R3C6C.WDO1 to R3C6A.WD1 sram_impl/mem0/WD1_INT (to WE_mem) -------- 0.356 (36.8% logic, 63.2% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_20: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R4C6B.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C6A.CLK CLK_c REG_DEL --- 0.151 R3C6A.CLK to R3C6A.Q0 SLICE_13 ROUTE 27 0.523 R3C6A.Q0 to R4C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R4C6D.B0 to R4C6D.OFX0 SLICE_39 ROUTE 1 0.000 R4C6D.OFX0 to R4C6C.FXA n1336 FXTOOFX_DE --- 0.098 R4C6C.FXA to R4C6C.OFX1 SLICE_40 ROUTE 1 0.316 R4C6C.OFX1 to R5C6B.B0 n15_adj_5 CTOOFX_DEL --- 0.267 R5C6B.B0 to R5C6B.OFX0 SLICE_30 ROUTE 1 0.000 R5C6B.OFX0 to R5C6A.FXA n1327 FXTOOFX_DE --- 0.098 R5C6A.FXA to R5C6A.OFX1 i724/SLICE_38 ROUTE 3 0.581 R5C6A.OFX1 to R4C4B.B1 n763 CTOF_DEL --- 0.174 R4C4B.B1 to R4C4B.F1 SLICE_53 ROUTE 4 0.447 R4C4B.F1 to R3C6A.WCK WE_mem -------- 3.976 (37.6% logic, 62.4% route), 7 logic levels. Error: The following path exceeds requirements by 0.171ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in sram_impl/mem1/RAM1 (to WE_mem +) FF sram_impl/mem1/RAM1 Delay: 0.528ns (42.4% logic, 57.6% route), 3 logic levels. Constraint Details: 0.528ns physical path delay SLICE_13 to sram_impl/mem1/SLICE_11 exceeds 0.129ns WAD_HLD and -2.500ns delay constraint less -3.070ns skew requirement (totaling 0.699ns) by 0.171ns Physical Path Details: Data path SLICE_13 to sram_impl/mem1/SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C6A.CLK to R3C6A.Q0 SLICE_13 (from CLK_c) ROUTE 27 0.160 R3C6A.Q0 to R3C8A.M1 r_addr_0 MTOOFX_DEL --- 0.093 R3C8A.M1 to R3C8A.OFX1 rom_impl/SLICE_48 ROUTE 11 0.144 R3C8A.OFX1 to R3C7C.C0 n766 ZERO_DEL --- 0.000 R3C7C.C0 to R3C7C.WADO2 sram_impl/mem1/SLICE_9 ROUTE 2 0.000 R3C7C.WADO2 to R3C7B.WAD2 sram_impl/mem1/AD2_INT (to WE_mem) -------- 0.528 (42.4% logic, 57.6% route), 3 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C6A.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_11: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C6A.CLK CLK_c REG_DEL --- 0.151 R3C6A.CLK to R3C6A.Q0 SLICE_13 ROUTE 27 0.523 R3C6A.Q0 to R4C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R4C6D.B0 to R4C6D.OFX0 SLICE_39 ROUTE 1 0.000 R4C6D.OFX0 to R4C6C.FXA n1336 FXTOOFX_DE --- 0.098 R4C6C.FXA to R4C6C.OFX1 SLICE_40 ROUTE 1 0.316 R4C6C.OFX1 to R5C6B.B0 n15_adj_5 CTOOFX_DEL --- 0.267 R5C6B.B0 to R5C6B.OFX0 SLICE_30 ROUTE 1 0.000 R5C6B.OFX0 to R5C6A.FXA n1327 FXTOOFX_DE --- 0.098 R5C6A.FXA to R5C6A.OFX1 i724/SLICE_38 ROUTE 3 0.581 R5C6A.OFX1 to R4C4B.B1 n763 CTOF_DEL --- 0.174 R4C4B.B1 to R4C4B.F1 SLICE_53 ROUTE 4 0.595 R4C4B.F1 to R3C7B.WCK WE_mem -------- 4.124 (36.2% logic, 63.8% route), 7 logic levels. Error: The following path exceeds requirements by 0.171ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in sram_impl/mem1/RAM0 (to WE_mem +) FF sram_impl/mem1/RAM0 Delay: 0.528ns (42.4% logic, 57.6% route), 3 logic levels. Constraint Details: 0.528ns physical path delay SLICE_13 to sram_impl/mem1/SLICE_10 exceeds 0.129ns WAD_HLD and -2.500ns delay constraint less -3.070ns skew requirement (totaling 0.699ns) by 0.171ns Physical Path Details: Data path SLICE_13 to sram_impl/mem1/SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C6A.CLK to R3C6A.Q0 SLICE_13 (from CLK_c) ROUTE 27 0.160 R3C6A.Q0 to R3C8A.M1 r_addr_0 MTOOFX_DEL --- 0.093 R3C8A.M1 to R3C8A.OFX1 rom_impl/SLICE_48 ROUTE 11 0.144 R3C8A.OFX1 to R3C7C.C0 n766 ZERO_DEL --- 0.000 R3C7C.C0 to R3C7C.WADO2 sram_impl/mem1/SLICE_9 ROUTE 2 0.000 R3C7C.WADO2 to R3C7A.WAD2 sram_impl/mem1/AD2_INT (to WE_mem) -------- 0.528 (42.4% logic, 57.6% route), 3 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_13: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C6A.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_10: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C6A.CLK CLK_c REG_DEL --- 0.151 R3C6A.CLK to R3C6A.Q0 SLICE_13 ROUTE 27 0.523 R3C6A.Q0 to R4C6D.B0 r_addr_0 CTOOFX_DEL --- 0.267 R4C6D.B0 to R4C6D.OFX0 SLICE_39 ROUTE 1 0.000 R4C6D.OFX0 to R4C6C.FXA n1336 FXTOOFX_DE --- 0.098 R4C6C.FXA to R4C6C.OFX1 SLICE_40 ROUTE 1 0.316 R4C6C.OFX1 to R5C6B.B0 n15_adj_5 CTOOFX_DEL --- 0.267 R5C6B.B0 to R5C6B.OFX0 SLICE_30 ROUTE 1 0.000 R5C6B.OFX0 to R5C6A.FXA n1327 FXTOOFX_DE --- 0.098 R5C6A.FXA to R5C6A.OFX1 i724/SLICE_38 ROUTE 3 0.581 R5C6A.OFX1 to R4C4B.B1 n763 CTOF_DEL --- 0.174 R4C4B.B1 to R4C4B.F1 SLICE_53 ROUTE 4 0.595 R4C4B.F1 to R3C7A.WCK WE_mem -------- 4.124 (36.2% logic, 63.8% route), 7 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "CLK" 200.000000 MHz ; | -| -| 2 * | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- n766 | 11| 4| 33.33% | | | r_addr_0 | 27| 4| 33.33% | | | sram_impl/mem0/AD2_INT | 2| 2| 16.67% | | | sram_impl/mem1/AD2_INT | 2| 2| 16.67% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: CLK_c Source: CLK.PAD Loads: 16 Covered under: FREQUENCY PORT "CLK" 200.000000 MHz ; Data transfers from: Clock Domain: WE_mem Source: SLICE_53.F1 Covered under: FREQUENCY PORT "CLK" 200.000000 MHz ; Transfers: 8 Clock Domain: WE_mem Source: SLICE_53.F1 Loads: 4 No transfer within this clock domain is found Data transfers from: Clock Domain: CLK_c Source: CLK.PAD Covered under: FREQUENCY PORT "CLK" 200.000000 MHz ; Transfers: 14 Timing summary (Hold): --------------- Timing errors: 12 Score: 22577 Cumulative negative slack: 22577 Constraints cover 4606 paths, 7 nets, and 497 connections (94.5% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 4096 (setup), 12 (hold) Score: 47015140 (setup), 22577 (hold) Cumulative negative slack: 23768341 (23745764+22577) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------