PAR: Place And Route Diamond_1.4_Production (87). Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Mon Jun 18 11:34:49 2012 Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_jtag_comm.p2t qfn32samples_jtag_comm_map.ncd qfn32samples_jtag_comm.dir qfn32samples_jtag_comm.prf Preference file: qfn32samples_jtag_comm.prf. Cost Table Summary Level/ Number Timing Run NCD Cost [ncd] Unrouted Score Time Status ---------- -------- -------- ----- ------------ 5_1 * 0 0 37 Complete * : Design saved. par done! Lattice Place and Route Report for Design "qfn32samples_jtag_comm_map.ncd" Mon Jun 18 11:34:49 2012 Best Par Run PAR: Place And Route Diamond_1.4_Production (87). Command Line: Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_jtag_comm.p2t qfn32samples_jtag_comm_map.ncd qfn32samples_jtag_comm.dir qfn32samples_jtag_comm.prf Preference file: qfn32samples_jtag_comm.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file qfn32samples_jtag_comm_map.ncd. Design name: tool_test NCD version: 3.2 Vendor: LATTICE Device: LCMXO2-256HC Package: QFN32 Performance: 4 Loading device for application par from file 'xo2c256.nph' in environment: Y:/Program_Files/lscc/diamond/1.4/ispfpga. Package Status: Advanced Version 1.34 Performance Hardware Data Status: Final) Version 22.4 License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 8/56 14% used 8/22 36% bonded SLICE 26/128 20% used GSR 1/1 100% used OSC 1/1 100% used JTAG 1/1 100% used EFB 1/1 100% used Number of Signals: 93 Number of Connections: 230 Pin Constraint Summary: 4 out of 8 pins locked (50% locked). The following 1 signal is selected to use the primary clock routing resources: CLK (driver: clk_selector, clk load #: 27) The following 1 signal is selected to use the DCM clock routing resources: CLK (driver: clk_selector, clk load #: 27) No signal is selected as secondary clock. Signal RESET is selected as Global Set/Reset. Starting Placer Phase 0. Finished Placer Phase 0. REAL time: 19 secs Starting Placer Phase 1. ................. Placer score = 9771. Finished Placer Phase 1. REAL time: 30 secs Starting Placer Phase 2. . Placer score = 9729 Finished Placer Phase 2. REAL time: 30 secs Clock Report Global Clock Resources: CLK_PIN : 0 out of 8 (0%) General PIO: 1 out of 56 (1%) DCM : 1 out of 2 (50%) DCC : 0 out of 8 (0%) Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY DCM "CLK", total # of clk loads = 27 "CLK" from comp "clk_selector" on DCM site "DCM6" - DCM input "CLK_INT" from OSC on comp "osc_internal" on site "OSC" - DCM input "EXTOSC_c" from comp "EXTOSC" on PIO site "12 (PB4B)" PRIMARY : 1 out of 8 (12%) SECONDARY: 0 out of 8 (0%) I/O Usage Summary (final): 8 out of 56 (14.3%) PIO sites used. 8 out of 22 (36.4%) bonded PIO sites used. Number of PIO comps: 8; differential: 0 Number of Vref pins used: 0 I/O Bank Usage Summary: +----------+--------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+--------------+------------+-----------+ | 0 | 6 / 9 ( 66%) | 2.5V | - | | 1 | 0 / 2 ( 0%) | - | - | | 2 | 2 / 9 ( 22%) | 2.5V | - | | 3 | 0 / 2 ( 0%) | - | - | +----------+--------------+------------+-----------+ Total placer CPU time: 13 secs Dumping design to file qfn32samples_jtag_comm.dir/5_1.ncd. 0 connections routed; 230 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 32 secs Starting iterative routing. For each routing iteration the number inside the parenthesis is the total time (in picoseconds) the design is failing the timing constraints. For each routing iteration the router will attempt to reduce this number until the number of routing iterations is completed or the value is 0 meaning the design has fully met the timing constraints. End of iteration 1 230 successful; 0 unrouted; (0) real time: 33 secs Dumping design to file qfn32samples_jtag_comm.dir/5_1.ncd. Total CPU time 14 secs Total REAL time: 33 secs Completely routed. End of route. 230 routed (100.00%); 0 unrouted. Checking DRC ... No errors found. Timing score: 0 Total REAL time to completion: 37 secs Dumping design to file qfn32samples_jtag_comm.dir/5_1.ncd. All signals are completely routed. par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.