PAR: Place And Route Diamond_1.4_Production (87).
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.
Sun Jun 24 10:48:27 2012

C:/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_mcpu3.p2t
qfn32samples_mcpu3_map.ncd qfn32samples_mcpu3.dir qfn32samples_mcpu3.prf

Preference file: qfn32samples_mcpu3.prf.

Cost Table Summary
Level/      Number      Timing      Run         NCD
Cost [ncd]  Unrouted    Score       Time        Status
----------  --------    --------    -----       ------------
5_1   *     0           123289688   05:42       Complete        


* : Design saved.

par done!

Lattice Place and Route Report for Design "qfn32samples_mcpu3_map.ncd"
Sun Jun 24 10:48:27 2012


Best Par Run
PAR: Place And Route Diamond_1.4_Production (87).
Command Line: C:/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_mcpu3.p2t
qfn32samples_mcpu3_map.ncd qfn32samples_mcpu3.dir qfn32samples_mcpu3.prf
Preference file: qfn32samples_mcpu3.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file qfn32samples_mcpu3_map.ncd.
Design name: mcpu
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-256HC
Package:     TQFP100
Performance: 4
Loading device for application par from file 'xo2c256.nph' in environment: C:/lscc/diamond/1.4/ispfpga.
Package Status:                     Final          Version 1.34
Performance Hardware Data Status:   Final)         Version 22.4
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)      17/56           30% used
                     17/56           30% bonded

   SLICE            101/128          78% used



Number of Signals: 217
Number of Connections: 905
WARNING - par: Placement timing preferences are hard to meet.  However, placement will continue.  Use static timing analysis to identify errors.  For more information, see online help subjects "Place & Route TRACE Report"  or the "TRACE" application.

Pin Constraint Summary:
   0 out of 17 pins locked (0% locked).

The following 1 signal is selected to use the primary clock routing resources:
    CLK_c (driver: CLK, clk load #: 16)


The following 1 signal is selected to use the secondary clock routing resources:
    RST_c (driver: RST, clk load #: 0, sr load #: 11, ce load #: 0)

No signal is selected as Global Set/Reset.
.
Starting Placer Phase 0.
........
Finished Placer Phase 0.  REAL time: 13 secs 

Starting Placer Phase 1.
..
Placer score = 55113529.
Finished Placer Phase 1.  REAL time: 35 secs 

Starting Placer Phase 2.
.
Placer score =  52875589
Finished Placer Phase 2.  REAL time: 41 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 2 out of 8 (25%)
  DCM        : 0 out of 2 (0%)
  DCC        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "CLK_c" from comp "CLK" on CLK_PIN site "38 (PB4C)", clk load = 16
  SECONDARY "RST_c" from comp "RST" on CLK_PIN site "20 (PL5C)", clk load = 0, ce load = 0, sr load = 11

  PRIMARY  : 1 out of 8 (12%)
  SECONDARY: 1 out of 8 (12%)




I/O Usage Summary (final):
   17 out of 56 (30.4%) PIO sites used.
   17 out of 56 (30.4%) bonded PIO sites used.
   Number of PIO comps: 17; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
+----------+---------------+------------+-----------+
| I/O Bank | Usage         | Bank Vccio | Bank Vref |
+----------+---------------+------------+-----------+
| 0        | 6 / 14 ( 42%) | 2.5V       | -         |
| 1        | 4 / 14 ( 28%) | 2.5V       | -         |
| 2        | 3 / 14 ( 21%) | 2.5V       | -         |
| 3        | 4 / 14 ( 28%) | 2.5V       | -         |
+----------+---------------+------------+-----------+

Total placer CPU time: 39 secs 

Dumping design to file qfn32samples_mcpu3.dir/5_1.ncd.

0 connections routed; 905 unrouted.
Starting router resource preassignment

Completed router resource preassignment. Real time: 47 secs 
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
905 successful; 0 unrouted; (133373426) real time: 1 mins 4 secs 
Dumping design to file qfn32samples_mcpu3.dir/5_1.ncd.
End of iteration 2
905 successful; 0 unrouted; (126809938) real time: 1 mins 49 secs 
Dumping design to file qfn32samples_mcpu3.dir/5_1.ncd.
End of iteration 3
905 successful; 0 unrouted; (123290832) real time: 2 mins 44 secs 
Dumping design to file qfn32samples_mcpu3.dir/5_1.ncd.
End of iteration 4
905 successful; 0 unrouted; (123290832) real time: 3 mins 34 secs 
End of iteration 5
905 successful; 0 unrouted; (123289688) real time: 4 mins 37 secs 
Dumping design to file qfn32samples_mcpu3.dir/5_1.ncd.
End of iteration 6
905 successful; 0 unrouted; (123289688) real time: 5 mins 40 secs 
Total CPU time 5 mins 36 secs 
Total REAL time: 5 mins 40 secs 
Completely routed.
End of route.  905 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.

Timing score: 123289688 

Total REAL time to completion: 5 mins 42 secs 

Dumping design to file qfn32samples_mcpu3.dir/5_1.ncd.


All signals are completely routed.


par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.