Place & Route TRACE Report
Loading design for application trce from file qfn32samples_dac.ncd.
Design name: dac3
NCD version: 3.2
Vendor: LATTICE
Device: LCMXO2-256HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c256.nph' in environment: Y:/Program_Files/lscc/diamond/1.4/ispfpga.
Package Status: Final Version 1.34
Performance Hardware Data Status: Final) Version 22.4
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond_1.4_Production (87)
Fri Jun 22 16:26:33 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_dac.twr qfn32samples_dac.ncd qfn32samples_dac.prf
Design file: qfn32samples_dac.ncd
Preference file: qfn32samples_dac.prf
Device,speed: LCMXO2-256HC,4
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY PORT "CLK" 248.000000 MHz (464 errors)
604 items scored, 464 timing errors detected.
Warning: 50.779MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY PORT "CLK" 248.000000 MHz ;
604 items scored, 464 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 15.661ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q r_data_i0_i0 (from CLK_c +)
Destination: FF Data in r_out0_32 (to CLK_c +)
Delay: 19.527ns (39.0% logic, 61.0% route), 15 logic levels.
Constraint Details:
19.527ns physical path delay SLICE_25 to SLICE_20 exceeds
4.032ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.866ns) by 15.661ns
Physical Path Details:
Data path SLICE_25 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C5B.CLK to R3C5B.Q0 SLICE_25 (from CLK_c)
ROUTE 1 1.004 R3C5B.Q0 to R3C5A.B0 r_data_0
CTOF_DEL --- 0.495 R3C5A.B0 to R3C5A.F0 SLICE_23
ROUTE 1 0.747 R3C5A.F0 to R3C5A.C1 n2
CTOF_DEL --- 0.495 R3C5A.C1 to R3C5A.F1 SLICE_23
ROUTE 1 0.747 R3C5A.F1 to R3C5C.C0 n4
CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 SLICE_24
ROUTE 1 0.436 R3C5C.F0 to R3C5C.C1 n6
CTOF_DEL --- 0.495 R3C5C.C1 to R3C5C.F1 SLICE_24
ROUTE 1 0.693 R3C5C.F1 to R3C5B.B0 n543
CTOF_DEL --- 0.495 R3C5B.B0 to R3C5B.F0 SLICE_25
ROUTE 1 0.436 R3C5B.F0 to R3C5B.C1 n10
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 SLICE_25
ROUTE 1 1.630 R3C5B.F1 to R3C5D.B0 n12
CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_26
ROUTE 1 0.626 R3C5D.F0 to R3C5D.D1 n14
CTOF_DEL --- 0.495 R3C5D.D1 to R3C5D.F1 SLICE_26
ROUTE 1 1.498 R3C5D.F1 to R3C4C.A0 n16
CTOF_DEL --- 0.495 R3C4C.A0 to R3C4C.F0 SLICE_27
ROUTE 1 0.436 R3C4C.F0 to R3C4C.C1 n18_adj_1
CTOF_DEL --- 0.495 R3C4C.C1 to R3C4C.F1 SLICE_27
ROUTE 1 1.004 R3C4C.F1 to R3C4D.B0 n20
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 SLICE_32
ROUTE 1 0.693 R3C4D.F0 to R3C4B.B1 n22
CTOF_DEL --- 0.495 R3C4B.B1 to R3C4B.F1 SLICE_22
ROUTE 1 1.004 R3C4B.F1 to R3C4B.B0 n24
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 SLICE_22
ROUTE 2 0.965 R3C4B.F0 to R5C4D.D0 n26
CTOOFX_DEL --- 0.721 R5C4D.D0 to R5C4D.OFX0 SLICE_20
ROUTE 1 0.000 R5C4D.OFX0 to R5C4D.DI0 n512 (to CLK_c)
--------
19.527 (39.0% logic, 61.0% route), 15 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_25:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R3C5B.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R5C4D.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 15.661ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q r_data_i0_i0 (from CLK_c +)
Destination: FF Data in r_out0_32 (to CLK_c +)
Delay: 19.527ns (39.0% logic, 61.0% route), 15 logic levels.
Constraint Details:
19.527ns physical path delay SLICE_25 to SLICE_20 exceeds
4.032ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.866ns) by 15.661ns
Physical Path Details:
Data path SLICE_25 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C5B.CLK to R3C5B.Q0 SLICE_25 (from CLK_c)
ROUTE 1 1.004 R3C5B.Q0 to R3C5A.B0 r_data_0
CTOF_DEL --- 0.495 R3C5A.B0 to R3C5A.F0 SLICE_23
ROUTE 1 0.747 R3C5A.F0 to R3C5A.C1 n2
CTOF_DEL --- 0.495 R3C5A.C1 to R3C5A.F1 SLICE_23
ROUTE 1 0.747 R3C5A.F1 to R3C5C.C0 n4
CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 SLICE_24
ROUTE 1 0.436 R3C5C.F0 to R3C5C.C1 n6
CTOF_DEL --- 0.495 R3C5C.C1 to R3C5C.F1 SLICE_24
ROUTE 1 0.693 R3C5C.F1 to R3C5B.B0 n543
CTOF_DEL --- 0.495 R3C5B.B0 to R3C5B.F0 SLICE_25
ROUTE 1 0.436 R3C5B.F0 to R3C5B.C1 n10
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 SLICE_25
ROUTE 1 1.630 R3C5B.F1 to R3C5D.B0 n12
CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_26
ROUTE 1 0.626 R3C5D.F0 to R3C5D.D1 n14
CTOF_DEL --- 0.495 R3C5D.D1 to R3C5D.F1 SLICE_26
ROUTE 1 1.498 R3C5D.F1 to R3C4C.A0 n16
CTOF_DEL --- 0.495 R3C4C.A0 to R3C4C.F0 SLICE_27
ROUTE 1 0.436 R3C4C.F0 to R3C4C.C1 n18_adj_1
CTOF_DEL --- 0.495 R3C4C.C1 to R3C4C.F1 SLICE_27
ROUTE 1 1.004 R3C4C.F1 to R3C4D.B0 n20
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 SLICE_32
ROUTE 1 0.693 R3C4D.F0 to R3C4B.B1 n22
CTOF_DEL --- 0.495 R3C4B.B1 to R3C4B.F1 SLICE_22
ROUTE 1 1.004 R3C4B.F1 to R3C4B.B0 n24
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 SLICE_22
ROUTE 2 0.965 R3C4B.F0 to R5C4D.D1 n26
CTOOFX_DEL --- 0.721 R5C4D.D1 to R5C4D.OFX0 SLICE_20
ROUTE 1 0.000 R5C4D.OFX0 to R5C4D.DI0 n512 (to CLK_c)
--------
19.527 (39.0% logic, 61.0% route), 15 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_25:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R3C5B.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R5C4D.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 15.422ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i0 (from CLK_c +)
Destination: FF Data in r_out0_32 (to CLK_c +)
Delay: 19.288ns (39.4% logic, 60.6% route), 15 logic levels.
Constraint Details:
19.288ns physical path delay SLICE_0 to SLICE_20 exceeds
4.032ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.866ns) by 15.422ns
Physical Path Details:
Data path SLICE_0 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C6A.CLK to R3C6A.Q1 SLICE_0 (from CLK_c)
ROUTE 3 0.765 R3C6A.Q1 to R3C5A.C0 count_0
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_23
ROUTE 1 0.747 R3C5A.F0 to R3C5A.C1 n2
CTOF_DEL --- 0.495 R3C5A.C1 to R3C5A.F1 SLICE_23
ROUTE 1 0.747 R3C5A.F1 to R3C5C.C0 n4
CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 SLICE_24
ROUTE 1 0.436 R3C5C.F0 to R3C5C.C1 n6
CTOF_DEL --- 0.495 R3C5C.C1 to R3C5C.F1 SLICE_24
ROUTE 1 0.693 R3C5C.F1 to R3C5B.B0 n543
CTOF_DEL --- 0.495 R3C5B.B0 to R3C5B.F0 SLICE_25
ROUTE 1 0.436 R3C5B.F0 to R3C5B.C1 n10
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 SLICE_25
ROUTE 1 1.630 R3C5B.F1 to R3C5D.B0 n12
CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_26
ROUTE 1 0.626 R3C5D.F0 to R3C5D.D1 n14
CTOF_DEL --- 0.495 R3C5D.D1 to R3C5D.F1 SLICE_26
ROUTE 1 1.498 R3C5D.F1 to R3C4C.A0 n16
CTOF_DEL --- 0.495 R3C4C.A0 to R3C4C.F0 SLICE_27
ROUTE 1 0.436 R3C4C.F0 to R3C4C.C1 n18_adj_1
CTOF_DEL --- 0.495 R3C4C.C1 to R3C4C.F1 SLICE_27
ROUTE 1 1.004 R3C4C.F1 to R3C4D.B0 n20
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 SLICE_32
ROUTE 1 0.693 R3C4D.F0 to R3C4B.B1 n22
CTOF_DEL --- 0.495 R3C4B.B1 to R3C4B.F1 SLICE_22
ROUTE 1 1.004 R3C4B.F1 to R3C4B.B0 n24
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 SLICE_22
ROUTE 2 0.965 R3C4B.F0 to R5C4D.D0 n26
CTOOFX_DEL --- 0.721 R5C4D.D0 to R5C4D.OFX0 SLICE_20
ROUTE 1 0.000 R5C4D.OFX0 to R5C4D.DI0 n512 (to CLK_c)
--------
19.288 (39.4% logic, 60.6% route), 15 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R3C6A.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R5C4D.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 15.422ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i0 (from CLK_c +)
Destination: FF Data in r_out0_32 (to CLK_c +)
Delay: 19.288ns (39.4% logic, 60.6% route), 15 logic levels.
Constraint Details:
19.288ns physical path delay SLICE_0 to SLICE_20 exceeds
4.032ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.866ns) by 15.422ns
Physical Path Details:
Data path SLICE_0 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C6A.CLK to R3C6A.Q1 SLICE_0 (from CLK_c)
ROUTE 3 0.765 R3C6A.Q1 to R3C5A.C0 count_0
CTOF_DEL --- 0.495 R3C5A.C0 to R3C5A.F0 SLICE_23
ROUTE 1 0.747 R3C5A.F0 to R3C5A.C1 n2
CTOF_DEL --- 0.495 R3C5A.C1 to R3C5A.F1 SLICE_23
ROUTE 1 0.747 R3C5A.F1 to R3C5C.C0 n4
CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 SLICE_24
ROUTE 1 0.436 R3C5C.F0 to R3C5C.C1 n6
CTOF_DEL --- 0.495 R3C5C.C1 to R3C5C.F1 SLICE_24
ROUTE 1 0.693 R3C5C.F1 to R3C5B.B0 n543
CTOF_DEL --- 0.495 R3C5B.B0 to R3C5B.F0 SLICE_25
ROUTE 1 0.436 R3C5B.F0 to R3C5B.C1 n10
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 SLICE_25
ROUTE 1 1.630 R3C5B.F1 to R3C5D.B0 n12
CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_26
ROUTE 1 0.626 R3C5D.F0 to R3C5D.D1 n14
CTOF_DEL --- 0.495 R3C5D.D1 to R3C5D.F1 SLICE_26
ROUTE 1 1.498 R3C5D.F1 to R3C4C.A0 n16
CTOF_DEL --- 0.495 R3C4C.A0 to R3C4C.F0 SLICE_27
ROUTE 1 0.436 R3C4C.F0 to R3C4C.C1 n18_adj_1
CTOF_DEL --- 0.495 R3C4C.C1 to R3C4C.F1 SLICE_27
ROUTE 1 1.004 R3C4C.F1 to R3C4D.B0 n20
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 SLICE_32
ROUTE 1 0.693 R3C4D.F0 to R3C4B.B1 n22
CTOF_DEL --- 0.495 R3C4B.B1 to R3C4B.F1 SLICE_22
ROUTE 1 1.004 R3C4B.F1 to R3C4B.B0 n24
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 SLICE_22
ROUTE 2 0.965 R3C4B.F0 to R5C4D.D1 n26
CTOOFX_DEL --- 0.721 R5C4D.D1 to R5C4D.OFX0 SLICE_20
ROUTE 1 0.000 R5C4D.OFX0 to R5C4D.DI0 n512 (to CLK_c)
--------
19.288 (39.4% logic, 60.6% route), 15 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R3C6A.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R5C4D.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 15.328ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i13 (from CLK_c +)
Destination: FF Data in r_out0_32 (to CLK_c +)
Delay: 19.194ns (39.6% logic, 60.4% route), 15 logic levels.
Constraint Details:
19.194ns physical path delay SLICE_7 to SLICE_20 exceeds
4.032ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.866ns) by 15.328ns
Physical Path Details:
Data path SLICE_7 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C7D.CLK to R3C7D.Q0 SLICE_7 (from CLK_c)
ROUTE 17 0.671 R3C7D.Q0 to R3C5A.D0 count_13
CTOF_DEL --- 0.495 R3C5A.D0 to R3C5A.F0 SLICE_23
ROUTE 1 0.747 R3C5A.F0 to R3C5A.C1 n2
CTOF_DEL --- 0.495 R3C5A.C1 to R3C5A.F1 SLICE_23
ROUTE 1 0.747 R3C5A.F1 to R3C5C.C0 n4
CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 SLICE_24
ROUTE 1 0.436 R3C5C.F0 to R3C5C.C1 n6
CTOF_DEL --- 0.495 R3C5C.C1 to R3C5C.F1 SLICE_24
ROUTE 1 0.693 R3C5C.F1 to R3C5B.B0 n543
CTOF_DEL --- 0.495 R3C5B.B0 to R3C5B.F0 SLICE_25
ROUTE 1 0.436 R3C5B.F0 to R3C5B.C1 n10
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 SLICE_25
ROUTE 1 1.630 R3C5B.F1 to R3C5D.B0 n12
CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_26
ROUTE 1 0.626 R3C5D.F0 to R3C5D.D1 n14
CTOF_DEL --- 0.495 R3C5D.D1 to R3C5D.F1 SLICE_26
ROUTE 1 1.498 R3C5D.F1 to R3C4C.A0 n16
CTOF_DEL --- 0.495 R3C4C.A0 to R3C4C.F0 SLICE_27
ROUTE 1 0.436 R3C4C.F0 to R3C4C.C1 n18_adj_1
CTOF_DEL --- 0.495 R3C4C.C1 to R3C4C.F1 SLICE_27
ROUTE 1 1.004 R3C4C.F1 to R3C4D.B0 n20
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 SLICE_32
ROUTE 1 0.693 R3C4D.F0 to R3C4B.B1 n22
CTOF_DEL --- 0.495 R3C4B.B1 to R3C4B.F1 SLICE_22
ROUTE 1 1.004 R3C4B.F1 to R3C4B.B0 n24
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 SLICE_22
ROUTE 2 0.965 R3C4B.F0 to R5C4D.D0 n26
CTOOFX_DEL --- 0.721 R5C4D.D0 to R5C4D.OFX0 SLICE_20
ROUTE 1 0.000 R5C4D.OFX0 to R5C4D.DI0 n512 (to CLK_c)
--------
19.194 (39.6% logic, 60.4% route), 15 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R3C7D.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R5C4D.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 15.328ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i13 (from CLK_c +)
Destination: FF Data in r_out0_32 (to CLK_c +)
Delay: 19.194ns (39.6% logic, 60.4% route), 15 logic levels.
Constraint Details:
19.194ns physical path delay SLICE_7 to SLICE_20 exceeds
4.032ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.866ns) by 15.328ns
Physical Path Details:
Data path SLICE_7 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C7D.CLK to R3C7D.Q0 SLICE_7 (from CLK_c)
ROUTE 17 0.671 R3C7D.Q0 to R3C5A.D0 count_13
CTOF_DEL --- 0.495 R3C5A.D0 to R3C5A.F0 SLICE_23
ROUTE 1 0.747 R3C5A.F0 to R3C5A.C1 n2
CTOF_DEL --- 0.495 R3C5A.C1 to R3C5A.F1 SLICE_23
ROUTE 1 0.747 R3C5A.F1 to R3C5C.C0 n4
CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 SLICE_24
ROUTE 1 0.436 R3C5C.F0 to R3C5C.C1 n6
CTOF_DEL --- 0.495 R3C5C.C1 to R3C5C.F1 SLICE_24
ROUTE 1 0.693 R3C5C.F1 to R3C5B.B0 n543
CTOF_DEL --- 0.495 R3C5B.B0 to R3C5B.F0 SLICE_25
ROUTE 1 0.436 R3C5B.F0 to R3C5B.C1 n10
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 SLICE_25
ROUTE 1 1.630 R3C5B.F1 to R3C5D.B0 n12
CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_26
ROUTE 1 0.626 R3C5D.F0 to R3C5D.D1 n14
CTOF_DEL --- 0.495 R3C5D.D1 to R3C5D.F1 SLICE_26
ROUTE 1 1.498 R3C5D.F1 to R3C4C.A0 n16
CTOF_DEL --- 0.495 R3C4C.A0 to R3C4C.F0 SLICE_27
ROUTE 1 0.436 R3C4C.F0 to R3C4C.C1 n18_adj_1
CTOF_DEL --- 0.495 R3C4C.C1 to R3C4C.F1 SLICE_27
ROUTE 1 1.004 R3C4C.F1 to R3C4D.B0 n20
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 SLICE_32
ROUTE 1 0.693 R3C4D.F0 to R3C4B.B1 n22
CTOF_DEL --- 0.495 R3C4B.B1 to R3C4B.F1 SLICE_22
ROUTE 1 1.004 R3C4B.F1 to R3C4B.B0 n24
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 SLICE_22
ROUTE 2 0.965 R3C4B.F0 to R5C4D.D1 n26
CTOOFX_DEL --- 0.721 R5C4D.D1 to R5C4D.OFX0 SLICE_20
ROUTE 1 0.000 R5C4D.OFX0 to R5C4D.DI0 n512 (to CLK_c)
--------
19.194 (39.6% logic, 60.4% route), 15 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R3C7D.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R5C4D.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 14.790ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i13 (from CLK_c +)
Destination: FF Data in r_out0_32 (to CLK_c +)
Delay: 18.656ns (38.1% logic, 61.9% route), 14 logic levels.
Constraint Details:
18.656ns physical path delay SLICE_7 to SLICE_20 exceeds
4.032ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.866ns) by 14.790ns
Physical Path Details:
Data path SLICE_7 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C7D.CLK to R3C7D.Q0 SLICE_7 (from CLK_c)
ROUTE 17 1.375 R3C7D.Q0 to R3C5A.A1 count_13
CTOF_DEL --- 0.495 R3C5A.A1 to R3C5A.F1 SLICE_23
ROUTE 1 0.747 R3C5A.F1 to R3C5C.C0 n4
CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 SLICE_24
ROUTE 1 0.436 R3C5C.F0 to R3C5C.C1 n6
CTOF_DEL --- 0.495 R3C5C.C1 to R3C5C.F1 SLICE_24
ROUTE 1 0.693 R3C5C.F1 to R3C5B.B0 n543
CTOF_DEL --- 0.495 R3C5B.B0 to R3C5B.F0 SLICE_25
ROUTE 1 0.436 R3C5B.F0 to R3C5B.C1 n10
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 SLICE_25
ROUTE 1 1.630 R3C5B.F1 to R3C5D.B0 n12
CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_26
ROUTE 1 0.626 R3C5D.F0 to R3C5D.D1 n14
CTOF_DEL --- 0.495 R3C5D.D1 to R3C5D.F1 SLICE_26
ROUTE 1 1.498 R3C5D.F1 to R3C4C.A0 n16
CTOF_DEL --- 0.495 R3C4C.A0 to R3C4C.F0 SLICE_27
ROUTE 1 0.436 R3C4C.F0 to R3C4C.C1 n18_adj_1
CTOF_DEL --- 0.495 R3C4C.C1 to R3C4C.F1 SLICE_27
ROUTE 1 1.004 R3C4C.F1 to R3C4D.B0 n20
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 SLICE_32
ROUTE 1 0.693 R3C4D.F0 to R3C4B.B1 n22
CTOF_DEL --- 0.495 R3C4B.B1 to R3C4B.F1 SLICE_22
ROUTE 1 1.004 R3C4B.F1 to R3C4B.B0 n24
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 SLICE_22
ROUTE 2 0.965 R3C4B.F0 to R5C4D.D0 n26
CTOOFX_DEL --- 0.721 R5C4D.D0 to R5C4D.OFX0 SLICE_20
ROUTE 1 0.000 R5C4D.OFX0 to R5C4D.DI0 n512 (to CLK_c)
--------
18.656 (38.1% logic, 61.9% route), 14 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R3C7D.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R5C4D.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 14.790ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i13 (from CLK_c +)
Destination: FF Data in r_out0_32 (to CLK_c +)
Delay: 18.656ns (38.1% logic, 61.9% route), 14 logic levels.
Constraint Details:
18.656ns physical path delay SLICE_7 to SLICE_20 exceeds
4.032ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.866ns) by 14.790ns
Physical Path Details:
Data path SLICE_7 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C7D.CLK to R3C7D.Q0 SLICE_7 (from CLK_c)
ROUTE 17 1.375 R3C7D.Q0 to R3C5A.A1 count_13
CTOF_DEL --- 0.495 R3C5A.A1 to R3C5A.F1 SLICE_23
ROUTE 1 0.747 R3C5A.F1 to R3C5C.C0 n4
CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 SLICE_24
ROUTE 1 0.436 R3C5C.F0 to R3C5C.C1 n6
CTOF_DEL --- 0.495 R3C5C.C1 to R3C5C.F1 SLICE_24
ROUTE 1 0.693 R3C5C.F1 to R3C5B.B0 n543
CTOF_DEL --- 0.495 R3C5B.B0 to R3C5B.F0 SLICE_25
ROUTE 1 0.436 R3C5B.F0 to R3C5B.C1 n10
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 SLICE_25
ROUTE 1 1.630 R3C5B.F1 to R3C5D.B0 n12
CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_26
ROUTE 1 0.626 R3C5D.F0 to R3C5D.D1 n14
CTOF_DEL --- 0.495 R3C5D.D1 to R3C5D.F1 SLICE_26
ROUTE 1 1.498 R3C5D.F1 to R3C4C.A0 n16
CTOF_DEL --- 0.495 R3C4C.A0 to R3C4C.F0 SLICE_27
ROUTE 1 0.436 R3C4C.F0 to R3C4C.C1 n18_adj_1
CTOF_DEL --- 0.495 R3C4C.C1 to R3C4C.F1 SLICE_27
ROUTE 1 1.004 R3C4C.F1 to R3C4D.B0 n20
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 SLICE_32
ROUTE 1 0.693 R3C4D.F0 to R3C4B.B1 n22
CTOF_DEL --- 0.495 R3C4B.B1 to R3C4B.F1 SLICE_22
ROUTE 1 1.004 R3C4B.F1 to R3C4B.B0 n24
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 SLICE_22
ROUTE 2 0.965 R3C4B.F0 to R5C4D.D1 n26
CTOOFX_DEL --- 0.721 R5C4D.D1 to R5C4D.OFX0 SLICE_20
ROUTE 1 0.000 R5C4D.OFX0 to R5C4D.DI0 n512 (to CLK_c)
--------
18.656 (38.1% logic, 61.9% route), 14 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R3C7D.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R5C4D.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 14.452ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i1 (from CLK_c +)
Destination: FF Data in r_out0_32 (to CLK_c +)
Delay: 18.318ns (38.8% logic, 61.2% route), 14 logic levels.
Constraint Details:
18.318ns physical path delay SLICE_5 to SLICE_20 exceeds
4.032ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.866ns) by 14.452ns
Physical Path Details:
Data path SLICE_5 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C6B.CLK to R3C6B.Q0 SLICE_5 (from CLK_c)
ROUTE 3 1.037 R3C6B.Q0 to R3C5A.B1 count_1
CTOF_DEL --- 0.495 R3C5A.B1 to R3C5A.F1 SLICE_23
ROUTE 1 0.747 R3C5A.F1 to R3C5C.C0 n4
CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 SLICE_24
ROUTE 1 0.436 R3C5C.F0 to R3C5C.C1 n6
CTOF_DEL --- 0.495 R3C5C.C1 to R3C5C.F1 SLICE_24
ROUTE 1 0.693 R3C5C.F1 to R3C5B.B0 n543
CTOF_DEL --- 0.495 R3C5B.B0 to R3C5B.F0 SLICE_25
ROUTE 1 0.436 R3C5B.F0 to R3C5B.C1 n10
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 SLICE_25
ROUTE 1 1.630 R3C5B.F1 to R3C5D.B0 n12
CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_26
ROUTE 1 0.626 R3C5D.F0 to R3C5D.D1 n14
CTOF_DEL --- 0.495 R3C5D.D1 to R3C5D.F1 SLICE_26
ROUTE 1 1.498 R3C5D.F1 to R3C4C.A0 n16
CTOF_DEL --- 0.495 R3C4C.A0 to R3C4C.F0 SLICE_27
ROUTE 1 0.436 R3C4C.F0 to R3C4C.C1 n18_adj_1
CTOF_DEL --- 0.495 R3C4C.C1 to R3C4C.F1 SLICE_27
ROUTE 1 1.004 R3C4C.F1 to R3C4D.B0 n20
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 SLICE_32
ROUTE 1 0.693 R3C4D.F0 to R3C4B.B1 n22
CTOF_DEL --- 0.495 R3C4B.B1 to R3C4B.F1 SLICE_22
ROUTE 1 1.004 R3C4B.F1 to R3C4B.B0 n24
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 SLICE_22
ROUTE 2 0.965 R3C4B.F0 to R5C4D.D0 n26
CTOOFX_DEL --- 0.721 R5C4D.D0 to R5C4D.OFX0 SLICE_20
ROUTE 1 0.000 R5C4D.OFX0 to R5C4D.DI0 n512 (to CLK_c)
--------
18.318 (38.8% logic, 61.2% route), 14 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R3C6B.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R5C4D.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 14.452ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i1 (from CLK_c +)
Destination: FF Data in r_out0_32 (to CLK_c +)
Delay: 18.318ns (38.8% logic, 61.2% route), 14 logic levels.
Constraint Details:
18.318ns physical path delay SLICE_5 to SLICE_20 exceeds
4.032ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 3.866ns) by 14.452ns
Physical Path Details:
Data path SLICE_5 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C6B.CLK to R3C6B.Q0 SLICE_5 (from CLK_c)
ROUTE 3 1.037 R3C6B.Q0 to R3C5A.B1 count_1
CTOF_DEL --- 0.495 R3C5A.B1 to R3C5A.F1 SLICE_23
ROUTE 1 0.747 R3C5A.F1 to R3C5C.C0 n4
CTOF_DEL --- 0.495 R3C5C.C0 to R3C5C.F0 SLICE_24
ROUTE 1 0.436 R3C5C.F0 to R3C5C.C1 n6
CTOF_DEL --- 0.495 R3C5C.C1 to R3C5C.F1 SLICE_24
ROUTE 1 0.693 R3C5C.F1 to R3C5B.B0 n543
CTOF_DEL --- 0.495 R3C5B.B0 to R3C5B.F0 SLICE_25
ROUTE 1 0.436 R3C5B.F0 to R3C5B.C1 n10
CTOF_DEL --- 0.495 R3C5B.C1 to R3C5B.F1 SLICE_25
ROUTE 1 1.630 R3C5B.F1 to R3C5D.B0 n12
CTOF_DEL --- 0.495 R3C5D.B0 to R3C5D.F0 SLICE_26
ROUTE 1 0.626 R3C5D.F0 to R3C5D.D1 n14
CTOF_DEL --- 0.495 R3C5D.D1 to R3C5D.F1 SLICE_26
ROUTE 1 1.498 R3C5D.F1 to R3C4C.A0 n16
CTOF_DEL --- 0.495 R3C4C.A0 to R3C4C.F0 SLICE_27
ROUTE 1 0.436 R3C4C.F0 to R3C4C.C1 n18_adj_1
CTOF_DEL --- 0.495 R3C4C.C1 to R3C4C.F1 SLICE_27
ROUTE 1 1.004 R3C4C.F1 to R3C4D.B0 n20
CTOF_DEL --- 0.495 R3C4D.B0 to R3C4D.F0 SLICE_32
ROUTE 1 0.693 R3C4D.F0 to R3C4B.B1 n22
CTOF_DEL --- 0.495 R3C4B.B1 to R3C4B.F1 SLICE_22
ROUTE 1 1.004 R3C4B.F1 to R3C4B.B0 n24
CTOF_DEL --- 0.495 R3C4B.B0 to R3C4B.F0 SLICE_22
ROUTE 2 0.965 R3C4B.F0 to R5C4D.D1 n26
CTOOFX_DEL --- 0.721 R5C4D.D1 to R5C4D.OFX0 SLICE_20
ROUTE 1 0.000 R5C4D.OFX0 to R5C4D.DI0 n512 (to CLK_c)
--------
18.318 (38.8% logic, 61.2% route), 14 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R3C6B.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 24 1.966 38.PADDI to R5C4D.CLK CLK_c
--------
1.966 (0.0% logic, 100.0% route), 0 logic levels.
Warning: 50.779MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "CLK" 248.000000 MHz ; | 248.000 MHz| 50.779 MHz| 15 *
| | |
----------------------------------------------------------------------------
1 preference(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
n39 | 20| 390| 84.05%
| | |
n26_adj_2 | 1| 216| 46.55%
| | |
n25 | 1| 162| 34.91%
| | |
n359 | 8| 118| 25.43%
| | |
n22_adj_4 | 1| 108| 23.28%
| | |
n24_adj_3 | 1| 108| 23.28%
| | |
n26 | 2| 74| 15.95%
| | |
n512 | 1| 74| 15.95%
| | |
n24 | 1| 72| 15.52%
| | |
n22 | 1| 66| 14.22%
| | |
n20 | 1| 60| 12.93%
| | |
n18_adj_1 | 1| 54| 11.64%
| | |
n18 | 1| 54| 11.64%
| | |
count_13 | 17| 51| 10.99%
| | |
n16 | 1| 48| 10.34%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: CLK_c Source: CLK.PAD Loads: 24
Covered under: FREQUENCY PORT "CLK" 248.000000 MHz ;
Timing summary (Setup):
---------------
Timing errors: 464 Score: 1509737
Cumulative negative slack: 1509737
Constraints cover 604 paths, 1 nets, and 182 connections (85.0% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond_1.4_Production (87)
Fri Jun 22 16:26:36 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_dac.twr qfn32samples_dac.ncd qfn32samples_dac.prf
Design file: qfn32samples_dac.ncd
Preference file: qfn32samples_dac.prf
Device,speed: LCMXO2-256HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY PORT "CLK" 248.000000 MHz (0 errors) 604 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "CLK" 248.000000 MHz ;
604 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.372ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i0 (from CLK_c +)
Destination: FF Data in count_49__i0 (to CLK_c +)
Delay: 0.359ns (64.1% logic, 35.9% route), 2 logic levels.
Constraint Details:
0.359ns physical path delay SLICE_0 to SLICE_0 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.372ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C6A.CLK to R3C6A.Q1 SLICE_0 (from CLK_c)
ROUTE 3 0.129 R3C6A.Q1 to R3C6A.A1 count_0
CTOF_DEL --- 0.099 R3C6A.A1 to R3C6A.F1 SLICE_0
ROUTE 1 0.000 R3C6A.F1 to R3C6A.DI1 n76 (to CLK_c)
--------
0.359 (64.1% logic, 35.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C6A.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C6A.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.372ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i12 (from CLK_c +)
Destination: FF Data in count_49__i12 (to CLK_c +)
Delay: 0.359ns (64.1% logic, 35.9% route), 2 logic levels.
Constraint Details:
0.359ns physical path delay SLICE_1 to SLICE_1 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.372ns
Physical Path Details:
Data path SLICE_1 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C7C.CLK to R3C7C.Q1 SLICE_1 (from CLK_c)
ROUTE 3 0.129 R3C7C.Q1 to R3C7C.A1 count_12
CTOF_DEL --- 0.099 R3C7C.A1 to R3C7C.F1 SLICE_1
ROUTE 1 0.000 R3C7C.F1 to R3C7C.DI1 n64 (to CLK_c)
--------
0.359 (64.1% logic, 35.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C7C.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C7C.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.372ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i7 (from CLK_c +)
Destination: FF Data in count_49__i7 (to CLK_c +)
Delay: 0.359ns (64.1% logic, 35.9% route), 2 logic levels.
Constraint Details:
0.359ns physical path delay SLICE_2 to SLICE_2 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.372ns
Physical Path Details:
Data path SLICE_2 to SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C7A.CLK to R3C7A.Q0 SLICE_2 (from CLK_c)
ROUTE 3 0.129 R3C7A.Q0 to R3C7A.A0 count_7
CTOF_DEL --- 0.099 R3C7A.A0 to R3C7A.F0 SLICE_2
ROUTE 1 0.000 R3C7A.F0 to R3C7A.DI0 n69 (to CLK_c)
--------
0.359 (64.1% logic, 35.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C7A.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C7A.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.372ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i9 (from CLK_c +)
Destination: FF Data in count_49__i9 (to CLK_c +)
Delay: 0.359ns (64.1% logic, 35.9% route), 2 logic levels.
Constraint Details:
0.359ns physical path delay SLICE_3 to SLICE_3 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.372ns
Physical Path Details:
Data path SLICE_3 to SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C7B.CLK to R3C7B.Q0 SLICE_3 (from CLK_c)
ROUTE 3 0.129 R3C7B.Q0 to R3C7B.A0 count_9
CTOF_DEL --- 0.099 R3C7B.A0 to R3C7B.F0 SLICE_3
ROUTE 1 0.000 R3C7B.F0 to R3C7B.DI0 n67 (to CLK_c)
--------
0.359 (64.1% logic, 35.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C7B.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C7B.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.372ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i2 (from CLK_c +)
Destination: FF Data in count_49__i2 (to CLK_c +)
Delay: 0.359ns (64.1% logic, 35.9% route), 2 logic levels.
Constraint Details:
0.359ns physical path delay SLICE_5 to SLICE_5 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.372ns
Physical Path Details:
Data path SLICE_5 to SLICE_5:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C6B.CLK to R3C6B.Q1 SLICE_5 (from CLK_c)
ROUTE 3 0.129 R3C6B.Q1 to R3C6B.A1 count_2
CTOF_DEL --- 0.099 R3C6B.A1 to R3C6B.F1 SLICE_5
ROUTE 1 0.000 R3C6B.F1 to R3C6B.DI1 n74 (to CLK_c)
--------
0.359 (64.1% logic, 35.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C6B.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C6B.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.372ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i1 (from CLK_c +)
Destination: FF Data in count_49__i1 (to CLK_c +)
Delay: 0.359ns (64.1% logic, 35.9% route), 2 logic levels.
Constraint Details:
0.359ns physical path delay SLICE_5 to SLICE_5 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.372ns
Physical Path Details:
Data path SLICE_5 to SLICE_5:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C6B.CLK to R3C6B.Q0 SLICE_5 (from CLK_c)
ROUTE 3 0.129 R3C6B.Q0 to R3C6B.A0 count_1
CTOF_DEL --- 0.099 R3C6B.A0 to R3C6B.F0 SLICE_5
ROUTE 1 0.000 R3C6B.F0 to R3C6B.DI0 n75 (to CLK_c)
--------
0.359 (64.1% logic, 35.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C6B.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C6B.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.372ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i4 (from CLK_c +)
Destination: FF Data in count_49__i4 (to CLK_c +)
Delay: 0.359ns (64.1% logic, 35.9% route), 2 logic levels.
Constraint Details:
0.359ns physical path delay SLICE_6 to SLICE_6 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.372ns
Physical Path Details:
Data path SLICE_6 to SLICE_6:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C6C.CLK to R3C6C.Q1 SLICE_6 (from CLK_c)
ROUTE 3 0.129 R3C6C.Q1 to R3C6C.A1 count_4
CTOF_DEL --- 0.099 R3C6C.A1 to R3C6C.F1 SLICE_6
ROUTE 1 0.000 R3C6C.F1 to R3C6C.DI1 n72 (to CLK_c)
--------
0.359 (64.1% logic, 35.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C6C.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C6C.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.372ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i3 (from CLK_c +)
Destination: FF Data in count_49__i3 (to CLK_c +)
Delay: 0.359ns (64.1% logic, 35.9% route), 2 logic levels.
Constraint Details:
0.359ns physical path delay SLICE_6 to SLICE_6 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.372ns
Physical Path Details:
Data path SLICE_6 to SLICE_6:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C6C.CLK to R3C6C.Q0 SLICE_6 (from CLK_c)
ROUTE 3 0.129 R3C6C.Q0 to R3C6C.A0 count_3
CTOF_DEL --- 0.099 R3C6C.A0 to R3C6C.F0 SLICE_6
ROUTE 1 0.000 R3C6C.F0 to R3C6C.DI0 n73 (to CLK_c)
--------
0.359 (64.1% logic, 35.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C6C.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C6C.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.373ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i11 (from CLK_c +)
Destination: FF Data in count_49__i11 (to CLK_c +)
Delay: 0.360ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.360ns physical path delay SLICE_1 to SLICE_1 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.373ns
Physical Path Details:
Data path SLICE_1 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C7C.CLK to R3C7C.Q0 SLICE_1 (from CLK_c)
ROUTE 3 0.130 R3C7C.Q0 to R3C7C.A0 count_11
CTOF_DEL --- 0.099 R3C7C.A0 to R3C7C.F0 SLICE_1
ROUTE 1 0.000 R3C7C.F0 to R3C7C.DI0 n65 (to CLK_c)
--------
0.360 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C7C.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C7C.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.373ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q count_49__i8 (from CLK_c +)
Destination: FF Data in count_49__i8 (to CLK_c +)
Delay: 0.360ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.360ns physical path delay SLICE_2 to SLICE_2 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.373ns
Physical Path Details:
Data path SLICE_2 to SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R3C7A.CLK to R3C7A.Q1 SLICE_2 (from CLK_c)
ROUTE 3 0.130 R3C7A.Q1 to R3C7A.A1 count_8
CTOF_DEL --- 0.099 R3C7A.A1 to R3C7A.F1 SLICE_2
ROUTE 1 0.000 R3C7A.F1 to R3C7A.DI1 n68 (to CLK_c)
--------
0.360 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path CLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C7A.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path CLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 24 0.615 38.PADDI to R3C7A.CLK CLK_c
--------
0.615 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "CLK" 248.000000 MHz ; | -| -| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: CLK_c Source: CLK.PAD Loads: 24
Covered under: FREQUENCY PORT "CLK" 248.000000 MHz ;
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 604 paths, 1 nets, and 182 connections (85.0% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 464 (setup), 0 (hold)
Score: 1509737 (setup), 0 (hold)
Cumulative negative slack: 1509737 (1509737+0)
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