Lattice Mapping Report File for Design Module 'mcpu' Design Information Command line: map -a MachXO2 -p LCMXO2-256HC -t TQFP100 -s 4 -oc Commercial qfn32samples_mcpu3.ngd -o qfn32samples_mcpu3_map.ncd -pr qfn32samples_mcpu3.prf -mp qfn32samples_mcpu3.mrp C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-w07/qfn32samples.lpf -c 0 Target Vendor: LATTICE Target Device: LCMXO2-256HCTQFP100 Target Performance: 4 Mapper: xo2c00, version: Diamond_1.4_Production (87) Mapped on: 06/24/12 10:48:25 Design Summary Number of registers: 26 PFU registers: 26 PIO registers: 0 Number of SLICEs: 101 out of 128 (79%) SLICEs(logic/ROM): 32 out of 32 (100%) SLICEs(logic/ROM/RAM): 69 out of 96 (72%) As RAM: 6 out of 96 (6%) As Logic/ROM: 63 out of 96 (66%) Number of logic LUT4s: 181 Number of distributed RAM: 6 (12 LUT4s) Number of ripple logic: 4 (8 LUT4s) Number of shift registers: 0 Total number of LUT4s: 201 Number of PIO sites used: 17 out of 56 (30%) Number of block RAMs: 0 out of 0 Number of GSRs: 0 out of 1 (0%) EFB used : No JTAG used : No Readback used : No Oscillator used : No Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 1 Net CLK_c: 16 loads, 13 rising, 3 falling (Driver: PIO CLK ) Number of Clock Enables: 5 Net rom_rd: 3 loads, 3 LSLICEs Net n1022: 1 loads, 1 LSLICEs Net n3519: 1 loads, 1 LSLICEs Net alu_impl_I/alu_impl/n1163: 4 loads, 4 LSLICEs Net alu_impl_I/alu_impl/alu_hi/n3600: 1 loads, 1 LSLICEs Number of LSRs: 2 Net RST_c: 11 loads, 11 LSLICEs Net n1231: 2 loads, 2 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net r_addr_2: 67 loads Net r_addr_3: 67 loads Net r_addr_1: 66 loads Net r_addr_4: 60 loads Net r_addr_5: 30 loads Net r_addr_0: 28 loads Net inst_2: 21 loads Net inst_0: 20 loads Net inst_1: 20 loads Net int_c_adj_26: 19 loads Number of warnings: 5 Number of errors: 0 Design Errors/Warnings WARNING: input pad net 'SCL' has no legal load WARNING: input pad net 'SDA' has no legal load WARNING: logical net 'add_28_1/CI' has no driver WARNING: IO buffer missing for top level port SCL...logic will be discarded. WARNING: IO buffer missing for top level port SDA...logic will be discarded. IO (PIO) Attributes +---------------------+-----------+-----------+------------+ | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | +---------------------+-----------+-----------+------------+ | WE | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | RST | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | CLK | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_DATA_0 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_DATA_1 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_DATA_2 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_DATA_3 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_DATA_4 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_DATA_5 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_DATA_6 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_DATA_7 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_ADDR_0 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_ADDR_1 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_ADDR_2 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_ADDR_3 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_ADDR_4 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | O_ADDR_5 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ Removed logic Block GSR_INST undriven or does not drive anything - clipped. Signal rom_impl/n4 was merged into signal CLK_c Signal GND_net undriven or does not drive anything - clipped. Signal VCC_net undriven or does not drive anything - clipped. Signal add_28_1/S0 undriven or does not drive anything - clipped. Signal add_28_1/CI undriven or does not drive anything - clipped. Signal add_28_7/CO undriven or does not drive anything - clipped. Block rom_impl/i4 was optimized away. Block i1 was optimized away. Block i2 was optimized away. Memory Usage /: EBRs: 0 RAM SLICEs: 2 Logic SLICEs: 44 PFU Registers: 19 /sram_impl/mem0: EBRs: 0 RAM SLICEs: 1 Logic SLICEs: 0 PFU Registers: 0 /sram_impl/mem1: EBRs: 0 RAM SLICEs: 3 Logic SLICEs: 0 PFU Registers: 0 Run Time and Memory Usage ------------------------- Total CPU Time: 1 secs Total REAL Time: 0 secs Peak Memory Usage: 23 MB Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.