PAD Specification File *************************** PART TYPE: LCMXO2-256HC Performance Grade: 4 PACKAGE: TQFP100 Package Status: Final Version 1.34 Sun Jun 24 11:31:49 2012 Pinout by Port Name: +-----------+----------+--------------+------+-----------+-----------+--------------------------------------+ | Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | +-----------+----------+--------------+------+-----------+-----------+--------------------------------------+ | CLK | 38/2 | LVCMOS25_IN | PB4C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | | O_ADDR_0 | 81/0 | LVCMOS25_OUT | PT9B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | | O_ADDR_1 | 70/1 | LVCMOS25_OUT | PR3B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | | O_ADDR_2 | 71/1 | LVCMOS25_OUT | PR3A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | | O_ADDR_3 | 7/3 | LVCMOS25_OUT | PL3A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | | O_ADDR_4 | 8/3 | LVCMOS25_OUT | PL3B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | | O_ADDR_5 | 48/2 | LVCMOS25_OUT | PB9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | | O_DATA_0 | 66/1 | LVCMOS25_OUT | PR3D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | | O_DATA_1 | 17/3 | LVCMOS25_OUT | PL5B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | | O_DATA_2 | 99/0 | LVCMOS25_OUT | PT6A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | | O_DATA_3 | 74/1 | LVCMOS25_OUT | PR2B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | | O_DATA_4 | 4/3 | LVCMOS25_OUT | PL2D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | | O_DATA_5 | 62/1 | LVCMOS25_OUT | PR5B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | | O_DATA_6 | 77/0 | LVCMOS25_OUT | PT9C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | | O_DATA_7 | 82/0 | LVCMOS25_OUT | PT9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | | RST | 53/1 | LVCMOS25_IN | PR6B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | | WE | 21/3 | LVCMOS25_OUT | PL5D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +-----------+----------+--------------+------+-----------+-----------+--------------------------------------+ Vccio by Bank: +------+-------+ | Bank | Vccio | +------+-------+ | 0 | 2.5V | | 1 | 2.5V | | 2 | 2.5V | | 3 | 2.5V | +------+-------+ Vref by Bank: +------+-----+-----------------+---------+ | Vref | Pin | Bank # / Vref # | Load(s) | +------+-----+-----------------+---------+ +------+-----+-----------------+---------+ Pinout by Pin Number: +----------+-----------------------+------------+--------------+------+-------------------------------------+-----------+-----------+ | Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | +----------+-----------------------+------------+--------------+------+-------------------------------------+-----------+-----------+ | 1/3 | unused, PULL:DOWN | | | PL2A | | | | | 2/3 | unused, PULL:DOWN | | | PL2B | | | | | 3/3 | unused, PULL:DOWN | | | PL2C | PCLKT3_2 | | | | 4/3 | O_DATA_4 | | LVCMOS25_OUT | PL2D | PCLKC3_2 | | | | 7/3 | O_ADDR_3 | | LVCMOS25_OUT | PL3A | | | | | 8/3 | O_ADDR_4 | | LVCMOS25_OUT | PL3B | | | | | 12/3 | unused, PULL:DOWN | | | PL3C | PCLKT3_1 | | | | 13/3 | unused, PULL:DOWN | | | PL3D | PCLKC3_1 | | | | 16/3 | unused, PULL:DOWN | | | PL5A | | | | | 17/3 | O_DATA_1 | | LVCMOS25_OUT | PL5B | | | | | 20/3 | unused, PULL:DOWN | | | PL5C | PCLKT3_0 | | | | 21/3 | WE | | LVCMOS25_OUT | PL5D | PCLKC3_0 | | | | 24/3 | unused, PULL:DOWN | | | PL6A | | | | | 25/3 | unused, PULL:DOWN | | | PL6B | | | | | 27/2 | unused, PULL:DOWN | | | PB2A | CSSPIN/MD4/TDOB | | | | 28/2 | unused, PULL:DOWN | | | PB2B | | | | | 31/2 | unused, PULL:DOWN | | | PB2C | MCLK/CCLK | | | | 32/2 | unused, PULL:DOWN | | | PB2D | SO/SPISO/IO1/MD1/TDIL | | | | 34/2 | unused, PULL:DOWN | | | PB4A | PCLKT2_0/INTEST_OVER | | | | 35/2 | unused, PULL:DOWN | | | PB4B | PCLKC2_0 | | | | 38/2 | CLK | | LVCMOS25_IN | PB4C | PCLKT2_1/INTEST_OVER | | | | 39/2 | unused, PULL:DOWN | | | PB4D | PCLKC2_1 | | | | 40/2 | unused, PULL:DOWN | | | PB7A | | | | | 41/2 | unused, PULL:DOWN | | | PB7B | | | | | 42/2 | unused, PULL:DOWN | | | PB7C | | | | | 43/2 | unused, PULL:DOWN | | | PB7D | | | | | 48/2 | O_ADDR_5 | | LVCMOS25_OUT | PB9A | SN/MD5/SCAN_SHFT_ENB/TDIB | | | | 49/2 | unused, PULL:DOWN | | | PB9B | SI/SISPI/IO0/MD0/TDOR | | | | 51/1 | unused, PULL:DOWN | | | PR6D | | | | | 52/1 | unused, PULL:DOWN | | | PR6C | | | | | 53/1 | RST | | LVCMOS25_IN | PR6B | | | | | 54/1 | unused, PULL:DOWN | | | PR6A | | | | | 57/1 | unused, PULL:DOWN | | | PR5D | | | | | 58/1 | unused, PULL:DOWN | | | PR5C | | | | | 62/1 | O_DATA_5 | | LVCMOS25_OUT | PR5B | PCLKC1_0 | | | | 63/1 | unused, PULL:DOWN | | | PR5A | PCLKT1_0 | | | | 66/1 | O_DATA_0 | | LVCMOS25_OUT | PR3D | | | | | 67/1 | unused, PULL:DOWN | | | PR3C | | | | | 70/1 | O_ADDR_1 | | LVCMOS25_OUT | PR3B | | | | | 71/1 | O_ADDR_2 | | LVCMOS25_OUT | PR3A | | | | | 74/1 | O_DATA_3 | | LVCMOS25_OUT | PR2B | | | | | 75/1 | unused, PULL:DOWN | | | PR2A | | | | | 76/0 | unused, PULL:DOWN | | | PT9D | DONE | | | | 77/0 | O_DATA_6 | | LVCMOS25_OUT | PT9C | INITN | | | | 81/0 | O_ADDR_0 | | LVCMOS25_OUT | PT9B | PROGRAMN | | | | 82/0 | O_DATA_7 | | LVCMOS25_OUT | PT9A | JTAGENB/MD6/TDIR | | | | 85/0 | unused, PULL:DOWN | | | PT8D | SDA/IO3/MD3/ATB_FORCE/PCLKC0_0/TDOT | | | | 86/0 | unused, PULL:DOWN | | | PT8C | SCL/IO2/MD2/ATB_SENSE/PCLKT0_0 | | | | 87/0 | unused, PULL:DOWN | | | PT8B | PCLKC0_1 | | | | 88/0 | unused, PULL:DOWN | | | PT8A | PCLKT0_1 | | | | 90/0 | Reserved: sysCONFIG | | | PT7B | TMS | | | | 91/0 | Reserved: sysCONFIG | | | PT7A | TCK/TEST_CLK | | | | 94/0 | Reserved: sysCONFIG | | | PT6D | TDI/MD7 | | | | 95/0 | Reserved: sysCONFIG | | | PT6C | TDO | | | | 98/0 | unused, PULL:DOWN | | | PT6B | | | | | 99/0 | O_DATA_2 | | LVCMOS25_OUT | PT6A | | | | +----------+-----------------------+------------+--------------+------+-------------------------------------+-----------+-----------+ sysCONFIG Pins: +----------+--------------------+--------------------+----------+-------------+-------------------+ | Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | +----------+--------------------+--------------------+----------+-------------+-------------------+ | PT7B | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | | PT7A | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | | PT6D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | | PT6C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | +----------+--------------------+--------------------+----------+-------------+-------------------+ Locate Preferences for each Pin: LOCATE COMP "CLK" SITE "38"; LOCATE COMP "O_ADDR_0" SITE "81"; LOCATE COMP "O_ADDR_1" SITE "70"; LOCATE COMP "O_ADDR_2" SITE "71"; LOCATE COMP "O_ADDR_3" SITE "7"; LOCATE COMP "O_ADDR_4" SITE "8"; LOCATE COMP "O_ADDR_5" SITE "48"; LOCATE COMP "O_DATA_0" SITE "66"; LOCATE COMP "O_DATA_1" SITE "17"; LOCATE COMP "O_DATA_2" SITE "99"; LOCATE COMP "O_DATA_3" SITE "74"; LOCATE COMP "O_DATA_4" SITE "4"; LOCATE COMP "O_DATA_5" SITE "62"; LOCATE COMP "O_DATA_6" SITE "77"; LOCATE COMP "O_DATA_7" SITE "82"; LOCATE COMP "RST" SITE "53"; LOCATE COMP "WE" SITE "21"; PAR: Place And Route Diamond_1.4_Production (87). Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Sun Jun 24 11:31:49 2012