Place & Route TRACE Report

Loading design for application trce from file qfn32samples_mcpu3.ncd.
Design name: mcpu
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-256HC
Package:     TQFP100
Performance: 4
Loading device for application trce from file 'xo2c256.nph' in environment: C:/lscc/diamond/1.4/ispfpga.
Package Status:                     Final          Version 1.34
Performance Hardware Data Status:   Final)         Version 22.4
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond_1.4_Production (87)
Sun Jun 24 10:54:11 2012

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_mcpu3.twr qfn32samples_mcpu3.ncd qfn32samples_mcpu3.prf 
Design file:     qfn32samples_mcpu3.ncd
Preference file: qfn32samples_mcpu3.prf
Device,speed:    LCMXO2-256HC,4
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY PORT "CLK" 200.000000 MHz (4096 errors)
  • 4096 items scored, 4096 timing errors detected. Warning: 22.945MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "CLK" 200.000000 MHz ; 4096 items scored, 4096 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 19.291ns (weighted slack = -38.582ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in Z_69 (to CLK_c +) Delay: 21.625ns (31.7% logic, 68.3% route), 14 logic levels. Constraint Details: 21.625ns physical path delay SLICE_25 to SLICE_11 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 19.291ns Physical Path Details: Data path SLICE_25 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C3D.CLK to R2C3D.Q0 SLICE_25 (from CLK_c) ROUTE 60 1.476 R2C3D.Q0 to R2C4A.A0 r_addr_4 CTOOFX_DEL --- 0.721 R2C4A.A0 to R2C4A.OFX0 rom_impl/SLICE_61 ROUTE 1 0.000 R2C4A.OFX0 to R2C4A.FXB rom_impl/mux_87_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R2C4A.FXB to R2C4A.OFX1 rom_impl/SLICE_61 ROUTE 12 1.998 R2C4A.OFX1 to R3C4A.B0 n995 CTOF_DEL --- 0.495 R3C4A.B0 to R3C4A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.345 R3C4A.F0 to R4C5C.B0 mem_data_0 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 0.976 R4C5C.F0 to R4C5C.A1 n52_adj_30 CTOF_DEL --- 0.495 R4C5C.A1 to R4C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 1.390 R4C5C.F1 to R3C5C.A1 alu_impl/alu_impl/alu_lo/n1815 CTOF_DEL --- 0.495 R3C5C.A1 to R3C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_91 ROUTE 2 1.093 R3C5C.F1 to R3C7B.C1 n1889 CTOF_DEL --- 0.495 R3C7B.C1 to R3C7B.F1 SLICE_74 ROUTE 3 1.591 R3C7B.F1 to R4C7D.D1 n1879 CTOF_DEL --- 0.495 R4C7D.D1 to R4C7D.F1 alu_impl/alu_impl/SLICE_94 ROUTE 2 1.010 R4C7D.F1 to R4C6C.B1 alu_impl/alu_impl/alu_hi/n1913 CTOF_DEL --- 0.495 R4C6C.B1 to R4C6C.F1 SLICE_84 ROUTE 2 0.665 R4C6C.F1 to R4C6D.A0 n3314 CTOF_DEL --- 0.495 R4C6D.A0 to R4C6D.F0 alu_impl/alu_impl/alu_hi/SLICE_102 ROUTE 2 1.821 R4C6D.F0 to R2C6D.D1 n1919 CTOF_DEL --- 0.495 R2C6D.D1 to R2C6D.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 0.654 R2C6D.F1 to R3C6C.D1 F_7 CTOF_DEL --- 0.495 R3C6C.D1 to R3C6C.F1 alu_impl/SLICE_101 ROUTE 1 0.747 R3C6C.F1 to R3C6A.C0 alu_impl/n3346 CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_11 ROUTE 1 0.000 R3C6A.F0 to R3C6A.DI0 Z_out (to CLK_c) -------- 21.625 (31.7% logic, 68.3% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_25: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R2C3D.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 19.291ns (weighted slack = -38.582ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in Z_69 (to CLK_c +) Delay: 21.625ns (31.7% logic, 68.3% route), 14 logic levels. Constraint Details: 21.625ns physical path delay SLICE_25 to SLICE_11 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 19.291ns Physical Path Details: Data path SLICE_25 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C3D.CLK to R2C3D.Q0 SLICE_25 (from CLK_c) ROUTE 60 1.476 R2C3D.Q0 to R2C4B.A0 r_addr_4 CTOOFX_DEL --- 0.721 R2C4B.A0 to R2C4B.OFX0 rom_impl/SLICE_60 ROUTE 1 0.000 R2C4B.OFX0 to R2C4A.FXA rom_impl/mux_87_Mux_1_0_f5a FXTOOFX_DE --- 0.241 R2C4A.FXA to R2C4A.OFX1 rom_impl/SLICE_61 ROUTE 12 1.998 R2C4A.OFX1 to R3C4A.B0 n995 CTOF_DEL --- 0.495 R3C4A.B0 to R3C4A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.345 R3C4A.F0 to R4C5C.B0 mem_data_0 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 0.976 R4C5C.F0 to R4C5C.A1 n52_adj_30 CTOF_DEL --- 0.495 R4C5C.A1 to R4C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 1.390 R4C5C.F1 to R3C5C.A1 alu_impl/alu_impl/alu_lo/n1815 CTOF_DEL --- 0.495 R3C5C.A1 to R3C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_91 ROUTE 2 1.093 R3C5C.F1 to R3C7B.C1 n1889 CTOF_DEL --- 0.495 R3C7B.C1 to R3C7B.F1 SLICE_74 ROUTE 3 1.591 R3C7B.F1 to R4C7D.D1 n1879 CTOF_DEL --- 0.495 R4C7D.D1 to R4C7D.F1 alu_impl/alu_impl/SLICE_94 ROUTE 2 1.010 R4C7D.F1 to R4C6C.B1 alu_impl/alu_impl/alu_hi/n1913 CTOF_DEL --- 0.495 R4C6C.B1 to R4C6C.F1 SLICE_84 ROUTE 2 0.665 R4C6C.F1 to R4C6D.A0 n3314 CTOF_DEL --- 0.495 R4C6D.A0 to R4C6D.F0 alu_impl/alu_impl/alu_hi/SLICE_102 ROUTE 2 1.821 R4C6D.F0 to R2C6D.D1 n1919 CTOF_DEL --- 0.495 R2C6D.D1 to R2C6D.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 0.654 R2C6D.F1 to R3C6C.D1 F_7 CTOF_DEL --- 0.495 R3C6C.D1 to R3C6C.F1 alu_impl/SLICE_101 ROUTE 1 0.747 R3C6C.F1 to R3C6A.C0 alu_impl/n3346 CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_11 ROUTE 1 0.000 R3C6A.F0 to R3C6A.DI0 Z_out (to CLK_c) -------- 21.625 (31.7% logic, 68.3% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_25: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R2C3D.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 19.291ns (weighted slack = -38.582ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in Z_69 (to CLK_c +) Delay: 21.625ns (31.7% logic, 68.3% route), 14 logic levels. Constraint Details: 21.625ns physical path delay SLICE_25 to SLICE_11 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 19.291ns Physical Path Details: Data path SLICE_25 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C3D.CLK to R2C3D.Q0 SLICE_25 (from CLK_c) ROUTE 60 1.476 R2C3D.Q0 to R2C4B.A1 r_addr_4 CTOOFX_DEL --- 0.721 R2C4B.A1 to R2C4B.OFX0 rom_impl/SLICE_60 ROUTE 1 0.000 R2C4B.OFX0 to R2C4A.FXA rom_impl/mux_87_Mux_1_0_f5a FXTOOFX_DE --- 0.241 R2C4A.FXA to R2C4A.OFX1 rom_impl/SLICE_61 ROUTE 12 1.998 R2C4A.OFX1 to R3C4A.B0 n995 CTOF_DEL --- 0.495 R3C4A.B0 to R3C4A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.345 R3C4A.F0 to R4C5C.B0 mem_data_0 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 0.976 R4C5C.F0 to R4C5C.A1 n52_adj_30 CTOF_DEL --- 0.495 R4C5C.A1 to R4C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 1.390 R4C5C.F1 to R3C5C.A1 alu_impl/alu_impl/alu_lo/n1815 CTOF_DEL --- 0.495 R3C5C.A1 to R3C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_91 ROUTE 2 1.093 R3C5C.F1 to R3C7B.C1 n1889 CTOF_DEL --- 0.495 R3C7B.C1 to R3C7B.F1 SLICE_74 ROUTE 3 1.591 R3C7B.F1 to R4C7D.D1 n1879 CTOF_DEL --- 0.495 R4C7D.D1 to R4C7D.F1 alu_impl/alu_impl/SLICE_94 ROUTE 2 1.010 R4C7D.F1 to R4C6C.B1 alu_impl/alu_impl/alu_hi/n1913 CTOF_DEL --- 0.495 R4C6C.B1 to R4C6C.F1 SLICE_84 ROUTE 2 0.665 R4C6C.F1 to R4C6D.A0 n3314 CTOF_DEL --- 0.495 R4C6D.A0 to R4C6D.F0 alu_impl/alu_impl/alu_hi/SLICE_102 ROUTE 2 1.821 R4C6D.F0 to R2C6D.D1 n1919 CTOF_DEL --- 0.495 R2C6D.D1 to R2C6D.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 0.654 R2C6D.F1 to R3C6C.D1 F_7 CTOF_DEL --- 0.495 R3C6C.D1 to R3C6C.F1 alu_impl/SLICE_101 ROUTE 1 0.747 R3C6C.F1 to R3C6A.C0 alu_impl/n3346 CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_11 ROUTE 1 0.000 R3C6A.F0 to R3C6A.DI0 Z_out (to CLK_c) -------- 21.625 (31.7% logic, 68.3% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_25: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R2C3D.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 19.291ns (weighted slack = -38.582ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q rom_impl/r_addr__i5 (from CLK_c -) Destination: FF Data in Z_69 (to CLK_c +) Delay: 21.625ns (31.7% logic, 68.3% route), 14 logic levels. Constraint Details: 21.625ns physical path delay SLICE_25 to SLICE_11 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 19.291ns Physical Path Details: Data path SLICE_25 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C3D.CLK to R2C3D.Q0 SLICE_25 (from CLK_c) ROUTE 60 1.476 R2C3D.Q0 to R2C4A.A1 r_addr_4 CTOOFX_DEL --- 0.721 R2C4A.A1 to R2C4A.OFX0 rom_impl/SLICE_61 ROUTE 1 0.000 R2C4A.OFX0 to R2C4A.FXB rom_impl/mux_87_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R2C4A.FXB to R2C4A.OFX1 rom_impl/SLICE_61 ROUTE 12 1.998 R2C4A.OFX1 to R3C4A.B0 n995 CTOF_DEL --- 0.495 R3C4A.B0 to R3C4A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.345 R3C4A.F0 to R4C5C.B0 mem_data_0 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 0.976 R4C5C.F0 to R4C5C.A1 n52_adj_30 CTOF_DEL --- 0.495 R4C5C.A1 to R4C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 1.390 R4C5C.F1 to R3C5C.A1 alu_impl/alu_impl/alu_lo/n1815 CTOF_DEL --- 0.495 R3C5C.A1 to R3C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_91 ROUTE 2 1.093 R3C5C.F1 to R3C7B.C1 n1889 CTOF_DEL --- 0.495 R3C7B.C1 to R3C7B.F1 SLICE_74 ROUTE 3 1.591 R3C7B.F1 to R4C7D.D1 n1879 CTOF_DEL --- 0.495 R4C7D.D1 to R4C7D.F1 alu_impl/alu_impl/SLICE_94 ROUTE 2 1.010 R4C7D.F1 to R4C6C.B1 alu_impl/alu_impl/alu_hi/n1913 CTOF_DEL --- 0.495 R4C6C.B1 to R4C6C.F1 SLICE_84 ROUTE 2 0.665 R4C6C.F1 to R4C6D.A0 n3314 CTOF_DEL --- 0.495 R4C6D.A0 to R4C6D.F0 alu_impl/alu_impl/alu_hi/SLICE_102 ROUTE 2 1.821 R4C6D.F0 to R2C6D.D1 n1919 CTOF_DEL --- 0.495 R2C6D.D1 to R2C6D.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 0.654 R2C6D.F1 to R3C6C.D1 F_7 CTOF_DEL --- 0.495 R3C6C.D1 to R3C6C.F1 alu_impl/SLICE_101 ROUTE 1 0.747 R3C6C.F1 to R3C6A.C0 alu_impl/n3346 CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_11 ROUTE 1 0.000 R3C6A.F0 to R3C6A.DI0 Z_out (to CLK_c) -------- 21.625 (31.7% logic, 68.3% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_25: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R2C3D.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 19.082ns (weighted slack = -38.164ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i3 (from CLK_c -) Destination: FF Data in Z_69 (to CLK_c +) Delay: 21.416ns (32.0% logic, 68.0% route), 14 logic levels. Constraint Details: 21.416ns physical path delay SLICE_6 to SLICE_11 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 19.082ns Physical Path Details: Data path SLICE_6 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C3B.CLK to R2C3B.Q0 SLICE_6 (from CLK_c) ROUTE 67 1.267 R2C3B.Q0 to R2C4A.C0 r_addr_2 CTOOFX_DEL --- 0.721 R2C4A.C0 to R2C4A.OFX0 rom_impl/SLICE_61 ROUTE 1 0.000 R2C4A.OFX0 to R2C4A.FXB rom_impl/mux_87_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R2C4A.FXB to R2C4A.OFX1 rom_impl/SLICE_61 ROUTE 12 1.998 R2C4A.OFX1 to R3C4A.B0 n995 CTOF_DEL --- 0.495 R3C4A.B0 to R3C4A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.345 R3C4A.F0 to R4C5C.B0 mem_data_0 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 0.976 R4C5C.F0 to R4C5C.A1 n52_adj_30 CTOF_DEL --- 0.495 R4C5C.A1 to R4C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 1.390 R4C5C.F1 to R3C5C.A1 alu_impl/alu_impl/alu_lo/n1815 CTOF_DEL --- 0.495 R3C5C.A1 to R3C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_91 ROUTE 2 1.093 R3C5C.F1 to R3C7B.C1 n1889 CTOF_DEL --- 0.495 R3C7B.C1 to R3C7B.F1 SLICE_74 ROUTE 3 1.591 R3C7B.F1 to R4C7D.D1 n1879 CTOF_DEL --- 0.495 R4C7D.D1 to R4C7D.F1 alu_impl/alu_impl/SLICE_94 ROUTE 2 1.010 R4C7D.F1 to R4C6C.B1 alu_impl/alu_impl/alu_hi/n1913 CTOF_DEL --- 0.495 R4C6C.B1 to R4C6C.F1 SLICE_84 ROUTE 2 0.665 R4C6C.F1 to R4C6D.A0 n3314 CTOF_DEL --- 0.495 R4C6D.A0 to R4C6D.F0 alu_impl/alu_impl/alu_hi/SLICE_102 ROUTE 2 1.821 R4C6D.F0 to R2C6D.D1 n1919 CTOF_DEL --- 0.495 R2C6D.D1 to R2C6D.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 0.654 R2C6D.F1 to R3C6C.D1 F_7 CTOF_DEL --- 0.495 R3C6C.D1 to R3C6C.F1 alu_impl/SLICE_101 ROUTE 1 0.747 R3C6C.F1 to R3C6A.C0 alu_impl/n3346 CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_11 ROUTE 1 0.000 R3C6A.F0 to R3C6A.DI0 Z_out (to CLK_c) -------- 21.416 (32.0% logic, 68.0% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R2C3B.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 18.964ns (weighted slack = -37.928ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in Z_69 (to CLK_c +) Delay: 21.298ns (32.2% logic, 67.8% route), 14 logic levels. Constraint Details: 21.298ns physical path delay SLICE_5 to SLICE_11 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 18.964ns Physical Path Details: Data path SLICE_5 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C3A.CLK to R2C3A.Q1 SLICE_5 (from CLK_c) ROUTE 66 1.149 R2C3A.Q1 to R2C4A.D1 r_addr_1 CTOOFX_DEL --- 0.721 R2C4A.D1 to R2C4A.OFX0 rom_impl/SLICE_61 ROUTE 1 0.000 R2C4A.OFX0 to R2C4A.FXB rom_impl/mux_87_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R2C4A.FXB to R2C4A.OFX1 rom_impl/SLICE_61 ROUTE 12 1.998 R2C4A.OFX1 to R3C4A.B0 n995 CTOF_DEL --- 0.495 R3C4A.B0 to R3C4A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.345 R3C4A.F0 to R4C5C.B0 mem_data_0 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 0.976 R4C5C.F0 to R4C5C.A1 n52_adj_30 CTOF_DEL --- 0.495 R4C5C.A1 to R4C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 1.390 R4C5C.F1 to R3C5C.A1 alu_impl/alu_impl/alu_lo/n1815 CTOF_DEL --- 0.495 R3C5C.A1 to R3C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_91 ROUTE 2 1.093 R3C5C.F1 to R3C7B.C1 n1889 CTOF_DEL --- 0.495 R3C7B.C1 to R3C7B.F1 SLICE_74 ROUTE 3 1.591 R3C7B.F1 to R4C7D.D1 n1879 CTOF_DEL --- 0.495 R4C7D.D1 to R4C7D.F1 alu_impl/alu_impl/SLICE_94 ROUTE 2 1.010 R4C7D.F1 to R4C6C.B1 alu_impl/alu_impl/alu_hi/n1913 CTOF_DEL --- 0.495 R4C6C.B1 to R4C6C.F1 SLICE_84 ROUTE 2 0.665 R4C6C.F1 to R4C6D.A0 n3314 CTOF_DEL --- 0.495 R4C6D.A0 to R4C6D.F0 alu_impl/alu_impl/alu_hi/SLICE_102 ROUTE 2 1.821 R4C6D.F0 to R2C6D.D1 n1919 CTOF_DEL --- 0.495 R2C6D.D1 to R2C6D.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 0.654 R2C6D.F1 to R3C6C.D1 F_7 CTOF_DEL --- 0.495 R3C6C.D1 to R3C6C.F1 alu_impl/SLICE_101 ROUTE 1 0.747 R3C6C.F1 to R3C6A.C0 alu_impl/n3346 CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_11 ROUTE 1 0.000 R3C6A.F0 to R3C6A.DI0 Z_out (to CLK_c) -------- 21.298 (32.2% logic, 67.8% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R2C3A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 18.964ns (weighted slack = -37.928ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i2 (from CLK_c -) Destination: FF Data in Z_69 (to CLK_c +) Delay: 21.298ns (32.2% logic, 67.8% route), 14 logic levels. Constraint Details: 21.298ns physical path delay SLICE_5 to SLICE_11 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 18.964ns Physical Path Details: Data path SLICE_5 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C3A.CLK to R2C3A.Q1 SLICE_5 (from CLK_c) ROUTE 66 1.149 R2C3A.Q1 to R2C4A.D0 r_addr_1 CTOOFX_DEL --- 0.721 R2C4A.D0 to R2C4A.OFX0 rom_impl/SLICE_61 ROUTE 1 0.000 R2C4A.OFX0 to R2C4A.FXB rom_impl/mux_87_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R2C4A.FXB to R2C4A.OFX1 rom_impl/SLICE_61 ROUTE 12 1.998 R2C4A.OFX1 to R3C4A.B0 n995 CTOF_DEL --- 0.495 R3C4A.B0 to R3C4A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.345 R3C4A.F0 to R4C5C.B0 mem_data_0 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 0.976 R4C5C.F0 to R4C5C.A1 n52_adj_30 CTOF_DEL --- 0.495 R4C5C.A1 to R4C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 1.390 R4C5C.F1 to R3C5C.A1 alu_impl/alu_impl/alu_lo/n1815 CTOF_DEL --- 0.495 R3C5C.A1 to R3C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_91 ROUTE 2 1.093 R3C5C.F1 to R3C7B.C1 n1889 CTOF_DEL --- 0.495 R3C7B.C1 to R3C7B.F1 SLICE_74 ROUTE 3 1.591 R3C7B.F1 to R4C7D.D1 n1879 CTOF_DEL --- 0.495 R4C7D.D1 to R4C7D.F1 alu_impl/alu_impl/SLICE_94 ROUTE 2 1.010 R4C7D.F1 to R4C6C.B1 alu_impl/alu_impl/alu_hi/n1913 CTOF_DEL --- 0.495 R4C6C.B1 to R4C6C.F1 SLICE_84 ROUTE 2 0.665 R4C6C.F1 to R4C6D.A0 n3314 CTOF_DEL --- 0.495 R4C6D.A0 to R4C6D.F0 alu_impl/alu_impl/alu_hi/SLICE_102 ROUTE 2 1.821 R4C6D.F0 to R2C6D.D1 n1919 CTOF_DEL --- 0.495 R2C6D.D1 to R2C6D.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 0.654 R2C6D.F1 to R3C6C.D1 F_7 CTOF_DEL --- 0.495 R3C6C.D1 to R3C6C.F1 alu_impl/SLICE_101 ROUTE 1 0.747 R3C6C.F1 to R3C6A.C0 alu_impl/n3346 CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_11 ROUTE 1 0.000 R3C6A.F0 to R3C6A.DI0 Z_out (to CLK_c) -------- 21.298 (32.2% logic, 67.8% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R2C3A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 18.942ns (weighted slack = -37.884ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i3 (from CLK_c -) Destination: FF Data in Z_69 (to CLK_c +) Delay: 21.276ns (32.2% logic, 67.8% route), 14 logic levels. Constraint Details: 21.276ns physical path delay SLICE_6 to SLICE_11 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 18.942ns Physical Path Details: Data path SLICE_6 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C3B.CLK to R2C3B.Q0 SLICE_6 (from CLK_c) ROUTE 67 1.127 R2C3B.Q0 to R2C4B.B0 r_addr_2 CTOOFX_DEL --- 0.721 R2C4B.B0 to R2C4B.OFX0 rom_impl/SLICE_60 ROUTE 1 0.000 R2C4B.OFX0 to R2C4A.FXA rom_impl/mux_87_Mux_1_0_f5a FXTOOFX_DE --- 0.241 R2C4A.FXA to R2C4A.OFX1 rom_impl/SLICE_61 ROUTE 12 1.998 R2C4A.OFX1 to R3C4A.B0 n995 CTOF_DEL --- 0.495 R3C4A.B0 to R3C4A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.345 R3C4A.F0 to R4C5C.B0 mem_data_0 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 0.976 R4C5C.F0 to R4C5C.A1 n52_adj_30 CTOF_DEL --- 0.495 R4C5C.A1 to R4C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 1.390 R4C5C.F1 to R3C5C.A1 alu_impl/alu_impl/alu_lo/n1815 CTOF_DEL --- 0.495 R3C5C.A1 to R3C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_91 ROUTE 2 1.093 R3C5C.F1 to R3C7B.C1 n1889 CTOF_DEL --- 0.495 R3C7B.C1 to R3C7B.F1 SLICE_74 ROUTE 3 1.591 R3C7B.F1 to R4C7D.D1 n1879 CTOF_DEL --- 0.495 R4C7D.D1 to R4C7D.F1 alu_impl/alu_impl/SLICE_94 ROUTE 2 1.010 R4C7D.F1 to R4C6C.B1 alu_impl/alu_impl/alu_hi/n1913 CTOF_DEL --- 0.495 R4C6C.B1 to R4C6C.F1 SLICE_84 ROUTE 2 0.665 R4C6C.F1 to R4C6D.A0 n3314 CTOF_DEL --- 0.495 R4C6D.A0 to R4C6D.F0 alu_impl/alu_impl/alu_hi/SLICE_102 ROUTE 2 1.821 R4C6D.F0 to R2C6D.D1 n1919 CTOF_DEL --- 0.495 R2C6D.D1 to R2C6D.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 0.654 R2C6D.F1 to R3C6C.D1 F_7 CTOF_DEL --- 0.495 R3C6C.D1 to R3C6C.F1 alu_impl/SLICE_101 ROUTE 1 0.747 R3C6C.F1 to R3C6A.C0 alu_impl/n3346 CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_11 ROUTE 1 0.000 R3C6A.F0 to R3C6A.DI0 Z_out (to CLK_c) -------- 21.276 (32.2% logic, 67.8% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R2C3B.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 18.942ns (weighted slack = -37.884ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i3 (from CLK_c -) Destination: FF Data in Z_69 (to CLK_c +) Delay: 21.276ns (32.2% logic, 67.8% route), 14 logic levels. Constraint Details: 21.276ns physical path delay SLICE_6 to SLICE_11 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 18.942ns Physical Path Details: Data path SLICE_6 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C3B.CLK to R2C3B.Q0 SLICE_6 (from CLK_c) ROUTE 67 1.127 R2C3B.Q0 to R2C4A.B1 r_addr_2 CTOOFX_DEL --- 0.721 R2C4A.B1 to R2C4A.OFX0 rom_impl/SLICE_61 ROUTE 1 0.000 R2C4A.OFX0 to R2C4A.FXB rom_impl/mux_87_Mux_1_1_f5b FXTOOFX_DE --- 0.241 R2C4A.FXB to R2C4A.OFX1 rom_impl/SLICE_61 ROUTE 12 1.998 R2C4A.OFX1 to R3C4A.B0 n995 CTOF_DEL --- 0.495 R3C4A.B0 to R3C4A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.345 R3C4A.F0 to R4C5C.B0 mem_data_0 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 0.976 R4C5C.F0 to R4C5C.A1 n52_adj_30 CTOF_DEL --- 0.495 R4C5C.A1 to R4C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 1.390 R4C5C.F1 to R3C5C.A1 alu_impl/alu_impl/alu_lo/n1815 CTOF_DEL --- 0.495 R3C5C.A1 to R3C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_91 ROUTE 2 1.093 R3C5C.F1 to R3C7B.C1 n1889 CTOF_DEL --- 0.495 R3C7B.C1 to R3C7B.F1 SLICE_74 ROUTE 3 1.591 R3C7B.F1 to R4C7D.D1 n1879 CTOF_DEL --- 0.495 R4C7D.D1 to R4C7D.F1 alu_impl/alu_impl/SLICE_94 ROUTE 2 1.010 R4C7D.F1 to R4C6C.B1 alu_impl/alu_impl/alu_hi/n1913 CTOF_DEL --- 0.495 R4C6C.B1 to R4C6C.F1 SLICE_84 ROUTE 2 0.665 R4C6C.F1 to R4C6D.A0 n3314 CTOF_DEL --- 0.495 R4C6D.A0 to R4C6D.F0 alu_impl/alu_impl/alu_hi/SLICE_102 ROUTE 2 1.821 R4C6D.F0 to R2C6D.D1 n1919 CTOF_DEL --- 0.495 R2C6D.D1 to R2C6D.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 0.654 R2C6D.F1 to R3C6C.D1 F_7 CTOF_DEL --- 0.495 R3C6C.D1 to R3C6C.F1 alu_impl/SLICE_101 ROUTE 1 0.747 R3C6C.F1 to R3C6A.C0 alu_impl/n3346 CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_11 ROUTE 1 0.000 R3C6A.F0 to R3C6A.DI0 Z_out (to CLK_c) -------- 21.276 (32.2% logic, 67.8% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R2C3B.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 18.942ns (weighted slack = -37.884ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i3 (from CLK_c -) Destination: FF Data in Z_69 (to CLK_c +) Delay: 21.276ns (32.2% logic, 67.8% route), 14 logic levels. Constraint Details: 21.276ns physical path delay SLICE_6 to SLICE_11 exceeds 2.500ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 2.334ns) by 18.942ns Physical Path Details: Data path SLICE_6 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R2C3B.CLK to R2C3B.Q0 SLICE_6 (from CLK_c) ROUTE 67 1.127 R2C3B.Q0 to R2C4B.B1 r_addr_2 CTOOFX_DEL --- 0.721 R2C4B.B1 to R2C4B.OFX0 rom_impl/SLICE_60 ROUTE 1 0.000 R2C4B.OFX0 to R2C4A.FXA rom_impl/mux_87_Mux_1_0_f5a FXTOOFX_DE --- 0.241 R2C4A.FXA to R2C4A.OFX1 rom_impl/SLICE_61 ROUTE 12 1.998 R2C4A.OFX1 to R3C4A.B0 n995 CTOF_DEL --- 0.495 R3C4A.B0 to R3C4A.F0 sram_impl/mem1/SLICE_8 ROUTE 2 1.345 R3C4A.F0 to R4C5C.B0 mem_data_0 CTOF_DEL --- 0.495 R4C5C.B0 to R4C5C.F0 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 0.976 R4C5C.F0 to R4C5C.A1 n52_adj_30 CTOF_DEL --- 0.495 R4C5C.A1 to R4C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_90 ROUTE 2 1.390 R4C5C.F1 to R3C5C.A1 alu_impl/alu_impl/alu_lo/n1815 CTOF_DEL --- 0.495 R3C5C.A1 to R3C5C.F1 alu_impl/alu_impl/alu_lo/SLICE_91 ROUTE 2 1.093 R3C5C.F1 to R3C7B.C1 n1889 CTOF_DEL --- 0.495 R3C7B.C1 to R3C7B.F1 SLICE_74 ROUTE 3 1.591 R3C7B.F1 to R4C7D.D1 n1879 CTOF_DEL --- 0.495 R4C7D.D1 to R4C7D.F1 alu_impl/alu_impl/SLICE_94 ROUTE 2 1.010 R4C7D.F1 to R4C6C.B1 alu_impl/alu_impl/alu_hi/n1913 CTOF_DEL --- 0.495 R4C6C.B1 to R4C6C.F1 SLICE_84 ROUTE 2 0.665 R4C6C.F1 to R4C6D.A0 n3314 CTOF_DEL --- 0.495 R4C6D.A0 to R4C6D.F0 alu_impl/alu_impl/alu_hi/SLICE_102 ROUTE 2 1.821 R4C6D.F0 to R2C6D.D1 n1919 CTOF_DEL --- 0.495 R2C6D.D1 to R2C6D.F1 alu_impl_I/alu_impl/alu_hi/SLICE_14 ROUTE 2 0.654 R2C6D.F1 to R3C6C.D1 F_7 CTOF_DEL --- 0.495 R3C6C.D1 to R3C6C.F1 alu_impl/SLICE_101 ROUTE 1 0.747 R3C6C.F1 to R3C6A.C0 alu_impl/n3346 CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_11 ROUTE 1 0.000 R3C6A.F0 to R3C6A.DI0 Z_out (to CLK_c) -------- 21.276 (32.2% logic, 67.8% route), 14 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R2C3B.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path CLK to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 16 1.966 38.PADDI to R3C6A.CLK CLK_c -------- 1.966 (0.0% logic, 100.0% route), 0 logic levels. Warning: 22.945MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "CLK" 200.000000 MHz ; | 200.000 MHz| 22.945 MHz| 14 * | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- n1879 | 3| 4024| 98.24% | | | n1889 | 2| 3613| 88.21% | | | alu_impl/alu_impl/alu_hi/n1913 | 2| 3460| 84.47% | | | n3314 | 2| 2800| 68.36% | | | n1919 | 2| 2590| 63.23% | | | Z_out | 1| 2253| 55.00% | | | F_7 | 2| 1733| 42.31% | | | alu_impl/n3346 | 1| 1676| 40.92% | | | alu_impl/alu_impl/alu_lo/n1815 | 2| 1472| 35.94% | | | n52_adj_30 | 2| 1390| 33.94% | | | n1077 | 2| 910| 22.22% | | | r_addr_2 | 67| 890| 21.73% | | | mem_data_0 | 2| 873| 21.31% | | | r_addr_4 | 60| 864| 21.09% | | | C_out | 1| 857| 20.92% | | | n777 | 1| 857| 20.92% | | | r_addr_3 | 67| 822| 20.07% | | | r_addr_1 | 66| 821| 20.04% | | | code_data_7 | 17| 804| 19.63% | | | int_c_adj_26 | 19| 764| 18.65% | | | code_data_8 | 18| 737| 17.99% | | | n62_adj_31 | 2| 724| 17.68% | | | FS_2 | 8| 695| 16.97% | | | mem_data_1 | 2| 685| 16.72% | | | F_5 | 2| 660| 16.11% | | | n1927 | 1| 660| 16.11% | | | F_4 | 2| 632| 15.43% | | | n1907 | 1| 632| 15.43% | | | n7_adj_29 | 8| 618| 15.09% | | | alu_impl_I/alu_impl/alu_hi/n1170 | 1| 615| 15.01% | | | n995 | 12| 519| 12.67% | | | n1076 | 3| 507| 12.38% | | | O_ADDR_c | 12| 475| 11.60% | | | alu_impl/n3334 | 1| 453| 11.06% | | | n993 | 12| 411| 10.03% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: CLK_c Source: CLK.PAD Loads: 16 Covered under: FREQUENCY PORT "CLK" 200.000000 MHz ; Data transfers from: Clock Domain: WE_mem Source: SLICE_70.F0 Covered under: FREQUENCY PORT "CLK" 200.000000 MHz ; Transfers: 8 Clock Domain: WE_mem Source: SLICE_70.F0 Loads: 4 No transfer within this clock domain is found Data transfers from: Clock Domain: CLK_c Source: CLK.PAD Covered under: FREQUENCY PORT "CLK" 200.000000 MHz ; Transfers: 14 Timing summary (Setup): --------------- Timing errors: 4096 Score: 123289688 Cumulative negative slack: 61644844 Constraints cover 31926 paths, 6 nets, and 873 connections (96.5% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond_1.4_Production (87) Sun Jun 24 10:54:12 2012 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o qfn32samples_mcpu3.twr qfn32samples_mcpu3.ncd qfn32samples_mcpu3.prf Design file: qfn32samples_mcpu3.ncd Preference file: qfn32samples_mcpu3.prf Device,speed: LCMXO2-256HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY PORT "CLK" 200.000000 MHz (94 errors)
  • 4096 items scored, 94 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "CLK" 200.000000 MHz ; 4096 items scored, 94 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 2.899ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i0 (from CLK_c +) Destination: FF Data in sram_impl/mem1/RAM0 (to WE_mem +) FF sram_impl/mem1/RAM0 Delay: 0.445ns (29.4% logic, 70.6% route), 2 logic levels. Constraint Details: 0.445ns physical path delay SLICE_10 to sram_impl/mem1/SLICE_8 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.215ns skew requirement (totaling 3.344ns) by 2.899ns Physical Path Details: Data path SLICE_10 to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C8C.CLK to R3C8C.Q0 SLICE_10 (from CLK_c) ROUTE 7 0.314 R3C8C.Q0 to R3C4C.A1 O_DATA_c ZERO_DEL --- 0.000 R3C4C.A1 to R3C4C.WDO0 sram_impl/mem1/SLICE_7 ROUTE 1 0.000 R3C4C.WDO0 to R3C4A.WD0 sram_impl/mem1/WD0_INT (to WE_mem) -------- 0.445 (29.4% logic, 70.6% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_10: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C8C.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C3A.CLK CLK_c REG_DEL --- 0.151 R2C3A.CLK to R2C3A.Q0 SLICE_5 ROUTE 28 0.495 R2C3A.Q0 to R2C2C.A0 r_addr_0 CTOF_DEL --- 0.174 R2C2C.A0 to R2C2C.F0 SLICE_95 ROUTE 1 0.595 R2C2C.F0 to R4C4A.D0 rom_impl/n46 CTOOFX_DEL --- 0.267 R4C4A.D0 to R4C4A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R4C4A.OFX0 to R4C4A.FXB rom_impl/n3355 FXTOOFX_DE --- 0.098 R4C4A.FXB to R4C4A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.604 R4C4A.OFX1 to R2C7C.A0 n992 CTOF_DEL --- 0.174 R2C7C.A0 to R2C7C.F0 SLICE_70 ROUTE 4 0.657 R2C7C.F0 to R3C4A.WCK WE_mem -------- 4.269 (30.5% logic, 69.5% route), 6 logic levels. Error: The following path exceeds requirements by 2.882ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i3 (from CLK_c +) Destination: FF Data in sram_impl/mem1/RAM1 (to WE_mem +) FF sram_impl/mem1/RAM1 Delay: 0.462ns (28.4% logic, 71.6% route), 2 logic levels. Constraint Details: 0.462ns physical path delay alu_impl_I/alu_impl/SLICE_16 to sram_impl/mem1/SLICE_9 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.215ns skew requirement (totaling 3.344ns) by 2.882ns Physical Path Details: Data path alu_impl_I/alu_impl/SLICE_16 to sram_impl/mem1/SLICE_9: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C7A.CLK to R3C7A.Q1 alu_impl_I/alu_impl/SLICE_16 (from CLK_c) ROUTE 8 0.331 R3C7A.Q1 to R3C4C.D1 n1000 ZERO_DEL --- 0.000 R3C4C.D1 to R3C4C.WDO3 sram_impl/mem1/SLICE_7 ROUTE 1 0.000 R3C4C.WDO3 to R3C4B.WD1 sram_impl/mem1/WD3_INT (to WE_mem) -------- 0.462 (28.4% logic, 71.6% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/SLICE_16: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C7A.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_9: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C3A.CLK CLK_c REG_DEL --- 0.151 R2C3A.CLK to R2C3A.Q0 SLICE_5 ROUTE 28 0.495 R2C3A.Q0 to R2C2C.A0 r_addr_0 CTOF_DEL --- 0.174 R2C2C.A0 to R2C2C.F0 SLICE_95 ROUTE 1 0.595 R2C2C.F0 to R4C4A.D0 rom_impl/n46 CTOOFX_DEL --- 0.267 R4C4A.D0 to R4C4A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R4C4A.OFX0 to R4C4A.FXB rom_impl/n3355 FXTOOFX_DE --- 0.098 R4C4A.FXB to R4C4A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.604 R4C4A.OFX1 to R2C7C.A0 n992 CTOF_DEL --- 0.174 R2C7C.A0 to R2C7C.F0 SLICE_70 ROUTE 4 0.657 R2C7C.F0 to R3C4B.WCK WE_mem -------- 4.269 (30.5% logic, 69.5% route), 6 logic levels. Error: The following path exceeds requirements by 2.877ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i2 (from CLK_c +) Destination: FF Data in sram_impl/mem1/RAM1 (to WE_mem +) FF sram_impl/mem1/RAM1 Delay: 0.467ns (28.1% logic, 71.9% route), 2 logic levels. Constraint Details: 0.467ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_17 to sram_impl/mem1/SLICE_9 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.215ns skew requirement (totaling 3.344ns) by 2.877ns Physical Path Details: Data path alu_impl_I/alu_impl/alu_lo/SLICE_17 to sram_impl/mem1/SLICE_9: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C7C.CLK to R3C7C.Q0 alu_impl_I/alu_impl/alu_lo/SLICE_17 (from CLK_c) ROUTE 8 0.336 R3C7C.Q0 to R3C4C.C1 n1001 ZERO_DEL --- 0.000 R3C4C.C1 to R3C4C.WDO2 sram_impl/mem1/SLICE_7 ROUTE 1 0.000 R3C4C.WDO2 to R3C4B.WD0 sram_impl/mem1/WD2_INT (to WE_mem) -------- 0.467 (28.1% logic, 71.9% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/alu_lo/SLICE_17: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C7C.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_9: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C3A.CLK CLK_c REG_DEL --- 0.151 R2C3A.CLK to R2C3A.Q0 SLICE_5 ROUTE 28 0.495 R2C3A.Q0 to R2C2C.A0 r_addr_0 CTOF_DEL --- 0.174 R2C2C.A0 to R2C2C.F0 SLICE_95 ROUTE 1 0.595 R2C2C.F0 to R4C4A.D0 rom_impl/n46 CTOOFX_DEL --- 0.267 R4C4A.D0 to R4C4A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R4C4A.OFX0 to R4C4A.FXB rom_impl/n3355 FXTOOFX_DE --- 0.098 R4C4A.FXB to R4C4A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.604 R4C4A.OFX1 to R2C7C.A0 n992 CTOF_DEL --- 0.174 R2C7C.A0 to R2C7C.F0 SLICE_70 ROUTE 4 0.657 R2C7C.F0 to R3C4B.WCK WE_mem -------- 4.269 (30.5% logic, 69.5% route), 6 logic levels. Error: The following path exceeds requirements by 2.793ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i7 (from CLK_c +) Destination: FF Data in sram_impl/mem0/RAM1 (to WE_mem +) FF sram_impl/mem0/RAM1 Delay: 0.403ns (32.5% logic, 67.5% route), 2 logic levels. Constraint Details: 0.403ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_14 to SLICE_6 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.067ns skew requirement (totaling 3.196ns) by 2.793ns Physical Path Details: Data path alu_impl_I/alu_impl/alu_hi/SLICE_14 to SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C6D.CLK to R2C6D.Q0 alu_impl_I/alu_impl/alu_hi/SLICE_14 (from CLK_c) ROUTE 8 0.272 R2C6D.Q0 to R2C3C.D1 n996 ZERO_DEL --- 0.000 R2C3C.D1 to R2C3C.WDO3 sram_impl/mem0/SLICE_4 ROUTE 1 0.000 R2C3C.WDO3 to R2C3B.WD1 sram_impl/mem0/WD3_INT (to WE_mem) -------- 0.403 (32.5% logic, 67.5% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_14: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C6D.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C3A.CLK CLK_c REG_DEL --- 0.151 R2C3A.CLK to R2C3A.Q0 SLICE_5 ROUTE 28 0.495 R2C3A.Q0 to R2C2C.A0 r_addr_0 CTOF_DEL --- 0.174 R2C2C.A0 to R2C2C.F0 SLICE_95 ROUTE 1 0.595 R2C2C.F0 to R4C4A.D0 rom_impl/n46 CTOOFX_DEL --- 0.267 R4C4A.D0 to R4C4A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R4C4A.OFX0 to R4C4A.FXB rom_impl/n3355 FXTOOFX_DE --- 0.098 R4C4A.FXB to R4C4A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.604 R4C4A.OFX1 to R2C7C.A0 n992 CTOF_DEL --- 0.174 R2C7C.A0 to R2C7C.F0 SLICE_70 ROUTE 4 0.509 R2C7C.F0 to R2C3B.WCK WE_mem -------- 4.121 (31.6% logic, 68.4% route), 6 logic levels. Error: The following path exceeds requirements by 2.773ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_lo/akku_i1 (from CLK_c +) Destination: FF Data in sram_impl/mem1/RAM0 (to WE_mem +) FF sram_impl/mem1/RAM0 Delay: 0.571ns (22.9% logic, 77.1% route), 2 logic levels. Constraint Details: 0.571ns physical path delay alu_impl_I/alu_impl/alu_lo/SLICE_17 to sram_impl/mem1/SLICE_8 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.215ns skew requirement (totaling 3.344ns) by 2.773ns Physical Path Details: Data path alu_impl_I/alu_impl/alu_lo/SLICE_17 to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C7C.CLK to R3C7C.Q1 alu_impl_I/alu_impl/alu_lo/SLICE_17 (from CLK_c) ROUTE 8 0.440 R3C7C.Q1 to R3C4C.B1 n1002 ZERO_DEL --- 0.000 R3C4C.B1 to R3C4C.WDO1 sram_impl/mem1/SLICE_7 ROUTE 1 0.000 R3C4C.WDO1 to R3C4A.WD1 sram_impl/mem1/WD1_INT (to WE_mem) -------- 0.571 (22.9% logic, 77.1% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/alu_lo/SLICE_17: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C7C.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C3A.CLK CLK_c REG_DEL --- 0.151 R2C3A.CLK to R2C3A.Q0 SLICE_5 ROUTE 28 0.495 R2C3A.Q0 to R2C2C.A0 r_addr_0 CTOF_DEL --- 0.174 R2C2C.A0 to R2C2C.F0 SLICE_95 ROUTE 1 0.595 R2C2C.F0 to R4C4A.D0 rom_impl/n46 CTOOFX_DEL --- 0.267 R4C4A.D0 to R4C4A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R4C4A.OFX0 to R4C4A.FXB rom_impl/n3355 FXTOOFX_DE --- 0.098 R4C4A.FXB to R4C4A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.604 R4C4A.OFX1 to R2C7C.A0 n992 CTOF_DEL --- 0.174 R2C7C.A0 to R2C7C.F0 SLICE_70 ROUTE 4 0.657 R2C7C.F0 to R3C4A.WCK WE_mem -------- 4.269 (30.5% logic, 69.5% route), 6 logic levels. Error: The following path exceeds requirements by 2.677ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i6 (from CLK_c +) Destination: FF Data in sram_impl/mem0/RAM1 (to WE_mem +) FF sram_impl/mem0/RAM1 Delay: 0.519ns (25.2% logic, 74.8% route), 2 logic levels. Constraint Details: 0.519ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_15 to SLICE_6 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.067ns skew requirement (totaling 3.196ns) by 2.677ns Physical Path Details: Data path alu_impl_I/alu_impl/alu_hi/SLICE_15 to SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C6B.CLK to R4C6B.Q0 alu_impl_I/alu_impl/alu_hi/SLICE_15 (from CLK_c) ROUTE 8 0.388 R4C6B.Q0 to R2C3C.C1 n997 ZERO_DEL --- 0.000 R2C3C.C1 to R2C3C.WDO2 sram_impl/mem0/SLICE_4 ROUTE 1 0.000 R2C3C.WDO2 to R2C3B.WD0 sram_impl/mem0/WD2_INT (to WE_mem) -------- 0.519 (25.2% logic, 74.8% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_15: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R4C6B.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to SLICE_6: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C3A.CLK CLK_c REG_DEL --- 0.151 R2C3A.CLK to R2C3A.Q0 SLICE_5 ROUTE 28 0.495 R2C3A.Q0 to R2C2C.A0 r_addr_0 CTOF_DEL --- 0.174 R2C2C.A0 to R2C2C.F0 SLICE_95 ROUTE 1 0.595 R2C2C.F0 to R4C4A.D0 rom_impl/n46 CTOOFX_DEL --- 0.267 R4C4A.D0 to R4C4A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R4C4A.OFX0 to R4C4A.FXB rom_impl/n3355 FXTOOFX_DE --- 0.098 R4C4A.FXB to R4C4A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.604 R4C4A.OFX1 to R2C7C.A0 n992 CTOF_DEL --- 0.174 R2C7C.A0 to R2C7C.F0 SLICE_70 ROUTE 4 0.509 R2C7C.F0 to R2C3B.WCK WE_mem -------- 4.121 (31.6% logic, 68.4% route), 6 logic levels. Error: The following path exceeds requirements by 2.537ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i4 (from CLK_c +) Destination: FF Data in sram_impl/mem0/RAM0 (to WE_mem +) FF sram_impl/mem0/RAM0 Delay: 0.659ns (19.9% logic, 80.1% route), 2 logic levels. Constraint Details: 0.659ns physical path delay alu_impl_I/alu_impl/SLICE_16 to SLICE_5 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.067ns skew requirement (totaling 3.196ns) by 2.537ns Physical Path Details: Data path alu_impl_I/alu_impl/SLICE_16 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C7A.CLK to R3C7A.Q0 alu_impl_I/alu_impl/SLICE_16 (from CLK_c) ROUTE 8 0.528 R3C7A.Q0 to R2C3C.A1 n999 ZERO_DEL --- 0.000 R2C3C.A1 to R2C3C.WDO0 sram_impl/mem0/SLICE_4 ROUTE 1 0.000 R2C3C.WDO0 to R2C3A.WD0 sram_impl/mem0/WD0_INT (to WE_mem) -------- 0.659 (19.9% logic, 80.1% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/SLICE_16: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R3C7A.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C3A.CLK CLK_c REG_DEL --- 0.151 R2C3A.CLK to R2C3A.Q0 SLICE_5 ROUTE 28 0.495 R2C3A.Q0 to R2C2C.A0 r_addr_0 CTOF_DEL --- 0.174 R2C2C.A0 to R2C2C.F0 SLICE_95 ROUTE 1 0.595 R2C2C.F0 to R4C4A.D0 rom_impl/n46 CTOOFX_DEL --- 0.267 R4C4A.D0 to R4C4A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R4C4A.OFX0 to R4C4A.FXB rom_impl/n3355 FXTOOFX_DE --- 0.098 R4C4A.FXB to R4C4A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.604 R4C4A.OFX1 to R2C7C.A0 n992 CTOF_DEL --- 0.174 R2C7C.A0 to R2C7C.F0 SLICE_70 ROUTE 4 0.509 R2C7C.F0 to R2C3A.WCK WE_mem -------- 4.121 (31.6% logic, 68.4% route), 6 logic levels. Error: The following path exceeds requirements by 2.519ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q alu_impl_I/alu_impl/alu_hi/akku_i5 (from CLK_c +) Destination: FF Data in sram_impl/mem0/RAM0 (to WE_mem +) FF sram_impl/mem0/RAM0 Delay: 0.677ns (19.4% logic, 80.6% route), 2 logic levels. Constraint Details: 0.677ns physical path delay alu_impl_I/alu_impl/alu_hi/SLICE_15 to SLICE_5 exceeds 0.129ns WD_HLD and 0.000ns delay constraint less -3.067ns skew requirement (totaling 3.196ns) by 2.519ns Physical Path Details: Data path alu_impl_I/alu_impl/alu_hi/SLICE_15 to SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R4C6B.CLK to R4C6B.Q1 alu_impl_I/alu_impl/alu_hi/SLICE_15 (from CLK_c) ROUTE 8 0.546 R4C6B.Q1 to R2C3C.B1 n998 ZERO_DEL --- 0.000 R2C3C.B1 to R2C3C.WDO1 sram_impl/mem0/SLICE_4 ROUTE 1 0.000 R2C3C.WDO1 to R2C3A.WD1 sram_impl/mem0/WD1_INT (to WE_mem) -------- 0.677 (19.4% logic, 80.6% route), 2 logic levels. Clock Skew Details: Source Clock Path CLK to alu_impl_I/alu_impl/alu_hi/SLICE_15: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R4C6B.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C3A.CLK CLK_c REG_DEL --- 0.151 R2C3A.CLK to R2C3A.Q0 SLICE_5 ROUTE 28 0.495 R2C3A.Q0 to R2C2C.A0 r_addr_0 CTOF_DEL --- 0.174 R2C2C.A0 to R2C2C.F0 SLICE_95 ROUTE 1 0.595 R2C2C.F0 to R4C4A.D0 rom_impl/n46 CTOOFX_DEL --- 0.267 R4C4A.D0 to R4C4A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R4C4A.OFX0 to R4C4A.FXB rom_impl/n3355 FXTOOFX_DE --- 0.098 R4C4A.FXB to R4C4A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.604 R4C4A.OFX1 to R2C7C.A0 n992 CTOF_DEL --- 0.174 R2C7C.A0 to R2C7C.F0 SLICE_70 ROUTE 4 0.509 R2C7C.F0 to R2C3A.WCK WE_mem -------- 4.121 (31.6% logic, 68.4% route), 6 logic levels. Error: The following path exceeds requirements by 0.222ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in sram_impl/mem1/RAM1 (to WE_mem +) FF sram_impl/mem1/RAM1 Delay: 0.622ns (36.0% logic, 64.0% route), 3 logic levels. Constraint Details: 0.622ns physical path delay SLICE_5 to sram_impl/mem1/SLICE_9 exceeds 0.129ns WAD_HLD and -2.500ns delay constraint less -3.215ns skew requirement (totaling 0.844ns) by 0.222ns Physical Path Details: Data path SLICE_5 to sram_impl/mem1/SLICE_9: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C3A.CLK to R2C3A.Q0 SLICE_5 (from CLK_c) ROUTE 28 0.164 R2C3A.Q0 to R2C2A.M1 r_addr_0 MTOOFX_DEL --- 0.093 R2C2A.M1 to R2C2A.OFX1 rom_impl/SLICE_43 ROUTE 12 0.234 R2C2A.OFX1 to R3C4C.D0 n993 ZERO_DEL --- 0.000 R3C4C.D0 to R3C4C.WADO3 sram_impl/mem1/SLICE_7 ROUTE 2 0.000 R3C4C.WADO3 to R3C4B.WAD3 sram_impl/mem1/AD3_INT (to WE_mem) -------- 0.622 (36.0% logic, 64.0% route), 3 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C3A.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_9: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C3A.CLK CLK_c REG_DEL --- 0.151 R2C3A.CLK to R2C3A.Q0 SLICE_5 ROUTE 28 0.495 R2C3A.Q0 to R2C2C.A0 r_addr_0 CTOF_DEL --- 0.174 R2C2C.A0 to R2C2C.F0 SLICE_95 ROUTE 1 0.595 R2C2C.F0 to R4C4A.D0 rom_impl/n46 CTOOFX_DEL --- 0.267 R4C4A.D0 to R4C4A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R4C4A.OFX0 to R4C4A.FXB rom_impl/n3355 FXTOOFX_DE --- 0.098 R4C4A.FXB to R4C4A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.604 R4C4A.OFX1 to R2C7C.A0 n992 CTOF_DEL --- 0.174 R2C7C.A0 to R2C7C.F0 SLICE_70 ROUTE 4 0.657 R2C7C.F0 to R3C4B.WCK WE_mem -------- 4.269 (30.5% logic, 69.5% route), 6 logic levels. Error: The following path exceeds requirements by 0.222ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr__i1 (from CLK_c -) Destination: FF Data in sram_impl/mem1/RAM0 (to WE_mem +) FF sram_impl/mem1/RAM0 Delay: 0.622ns (36.0% logic, 64.0% route), 3 logic levels. Constraint Details: 0.622ns physical path delay SLICE_5 to sram_impl/mem1/SLICE_8 exceeds 0.129ns WAD_HLD and -2.500ns delay constraint less -3.215ns skew requirement (totaling 0.844ns) by 0.222ns Physical Path Details: Data path SLICE_5 to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C3A.CLK to R2C3A.Q0 SLICE_5 (from CLK_c) ROUTE 28 0.164 R2C3A.Q0 to R2C2A.M1 r_addr_0 MTOOFX_DEL --- 0.093 R2C2A.M1 to R2C2A.OFX1 rom_impl/SLICE_43 ROUTE 12 0.234 R2C2A.OFX1 to R3C4C.D0 n993 ZERO_DEL --- 0.000 R3C4C.D0 to R3C4C.WADO3 sram_impl/mem1/SLICE_7 ROUTE 2 0.000 R3C4C.WADO3 to R3C4A.WAD3 sram_impl/mem1/AD3_INT (to WE_mem) -------- 0.622 (36.0% logic, 64.0% route), 3 logic levels. Clock Skew Details: Source Clock Path CLK to SLICE_5: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C3A.CLK CLK_c -------- 1.054 (41.7% logic, 58.3% route), 1 logic levels. Destination Clock Path CLK to sram_impl/mem1/SLICE_8: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.439 38.PAD to 38.PADDI CLK ROUTE 16 0.615 38.PADDI to R2C3A.CLK CLK_c REG_DEL --- 0.151 R2C3A.CLK to R2C3A.Q0 SLICE_5 ROUTE 28 0.495 R2C3A.Q0 to R2C2C.A0 r_addr_0 CTOF_DEL --- 0.174 R2C2C.A0 to R2C2C.F0 SLICE_95 ROUTE 1 0.595 R2C2C.F0 to R4C4A.D0 rom_impl/n46 CTOOFX_DEL --- 0.267 R4C4A.D0 to R4C4A.OFX0 rom_impl/SLICE_26 ROUTE 1 0.000 R4C4A.OFX0 to R4C4A.FXB rom_impl/n3355 FXTOOFX_DE --- 0.098 R4C4A.FXB to R4C4A.OFX1 rom_impl/SLICE_26 ROUTE 4 0.604 R4C4A.OFX1 to R2C7C.A0 n992 CTOF_DEL --- 0.174 R2C7C.A0 to R2C7C.F0 SLICE_70 ROUTE 4 0.657 R2C7C.F0 to R3C4A.WCK WE_mem -------- 4.269 (30.5% logic, 69.5% route), 6 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "CLK" 200.000000 MHz ; | -| -| 2 * | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- n994 | 12| 48| 51.06% | | | sram_impl/mem1/AD2_INT | 2| 36| 38.30% | | | sram_impl/mem1/AD3_INT | 2| 26| 27.66% | | | n993 | 12| 26| 27.66% | | | rom_impl/mux_87_Mux_2_1_f5b | 1| 22| 23.40% | | | rom_impl/mux_87_Mux_2_0_f5a | 1| 22| 23.40% | | | rom_impl/mux_87_Mux_3_0_f5a | 1| 18| 19.15% | | | r_addr_2 | 67| 18| 19.15% | | | r_addr_1 | 66| 18| 19.15% | | | r_addr_4 | 60| 14| 14.89% | | | r_addr_3 | 67| 14| 14.89% | | | r_addr_0 | 28| 14| 14.89% | | | sram_impl/mem0/AD2_INT | 2| 12| 12.77% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: CLK_c Source: CLK.PAD Loads: 16 Covered under: FREQUENCY PORT "CLK" 200.000000 MHz ; Data transfers from: Clock Domain: WE_mem Source: SLICE_70.F0 Covered under: FREQUENCY PORT "CLK" 200.000000 MHz ; Transfers: 8 Clock Domain: WE_mem Source: SLICE_70.F0 Loads: 4 No transfer within this clock domain is found Data transfers from: Clock Domain: CLK_c Source: CLK.PAD Covered under: FREQUENCY PORT "CLK" 200.000000 MHz ; Transfers: 14 Timing summary (Hold): --------------- Timing errors: 94 Score: 30013 Cumulative negative slack: 30013 Constraints cover 31926 paths, 6 nets, and 873 connections (96.5% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 4096 (setup), 94 (hold) Score: 123289688 (setup), 30013 (hold) Cumulative negative slack: 61674857 (61644844+30013) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------