Synthesis and Ngdbuild Report -- all messages logged in file synthesis.log Synthesis Options INFO: Synthesis Options: (LSE-1022) INFO: -a option is = MachXO2 INFO: -s option is = 4 INFO: -t option is = TQFP100 INFO: -d option is = LCMXO2-256HC INFO: Using package TQFP100 INFO: Using performance grade 4 INFO: INFO: ########################################################## INFO: ### Lattice Family : MachXO2 INFO: ### Device : LCMXO2-256HC INFO: ### Package : TQFP100 INFO: ### Speed : 4 INFO: ########################################################## INFO: INFO: Optimization Goal = Area INFO: -top option is not used WARNING: Ignoring Frequency option in Area Mode, Setting to default frequency of 1.0 MHz INFO: Target Frequency = 1.000000 MHz INFO: Max Fanout = 1000 INFO: Timing Path count = 3 INFO: bram Utilization = 100.000000 % INFO: dsp usage = TRUE (default) INFO: dsp utilization = 100 (default) INFO: fsm_encoding_style = auto INFO: Mux style = Auto INFO: Use Carry Chain = TRUE INFO: carry_chain_length = 0 INFO: Use IO Insertion = TRUE INFO: Use IO Reg = TRUE INFO: Resource Sharing = TRUE INFO: Propagate Constants = TRUE INFO: Remove Duplicate Registers = TRUE INFO: force_gsr = auto INFO: ROM style = auto INFO: RAM style = auto INFO: -comp option is FALSE INFO: -syn option is FALSE INFO: -p C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-w07 (searchpath added) INFO: -p C:/lscc/diamond/1.4/ispfpga/xo2c00/data (searchpath added) INFO: -p C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-w07/mcpu2 (searchpath added) INFO: -p C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-w07 (searchpath added) INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-w07/src/mcpu2.v INFO: Ngd file = qfn32samples_mcpu2.ngd INFO: -sdc option: sdc file input not used INFO: -lpf option: output file option is OFF INFO: hardtimer checking is enabled (default); -dt option not used INFO: -r option is OFF [ Remove LOC Properties is OFF ] -- Technology check ok...MachXO, MachXO2... INFO: The default vhdl library search path is now "c:/lscc/diamond/1.4/cae_library/vhdl_packages/vdbs" (VHDL-1504) INFO: * compile design * Compile Design INFO: Compile Design Begin c:/documents and settings/suz/my documents/lattice/xo2qfn-w07/src/mcpu2.v(64): INFO: compiling module mcpu (VERI-1018) c:/documents and settings/suz/my documents/lattice/xo2qfn-w07/src/mcpu2.v(233): INFO: compiling module sram (VERI-1018) c:/documents and settings/suz/my documents/lattice/xo2qfn-w07/src/mcpu2.v(280): INFO: compiling module rom (VERI-1018) c:/documents and settings/suz/my documents/lattice/xo2qfn-w07/src/mcpu2.v(290): WARNING: ram mem_original_ramnet has no write-port on it (VDB-1038) WARNING: Unsupported retiming instance (LSE-1120) WARNING: Unsupported retiming instance (LSE-1120) INFO: ######## Found 1 RAM Nets in design (LSE-1115) INFO: ######## Mapping RAM Net \sram_impl/mem to 2 Distributed blocks in SINGLE_PORT Mode ERROR: Bidir port should have Tristate Driver : efb_impl (LSE-1156)