PAR: Place And Route Diamond_1.4_Production (87). Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Fri Jun 15 15:25:47 2012 Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_clock1.p2t qfn32samples_clock1_map.ncd qfn32samples_clock1.dir qfn32samples_clock1.prf Preference file: qfn32samples_clock1.prf. Cost Table Summary Level/ Number Timing Run NCD Cost [ncd] Unrouted Score Time Status ---------- -------- -------- ----- ------------ 5_1 * 0 0 37 Complete * : Design saved. par done! Lattice Place and Route Report for Design "qfn32samples_clock1_map.ncd" Fri Jun 15 15:25:47 2012 Best Par Run PAR: Place And Route Diamond_1.4_Production (87). Command Line: Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_clock1.p2t qfn32samples_clock1_map.ncd qfn32samples_clock1.dir qfn32samples_clock1.prf Preference file: qfn32samples_clock1.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file qfn32samples_clock1_map.ncd. Design name: clock NCD version: 3.2 Vendor: LATTICE Device: LCMXO2-256HC Package: QFN32 Performance: 4 Loading device for application par from file 'xo2c256.nph' in environment: Y:/Program_Files/lscc/diamond/1.4/ispfpga. Package Status: Advanced Version 1.34 Performance Hardware Data Status: Final) Version 22.4 License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 17/56 30% used 17/22 77% bonded SLICE 122/128 95% used GSR 1/1 100% used Number of Signals: 328 Number of Connections: 1032 Pin Constraint Summary: 17 out of 17 pins locked (100% locked). The following 2 signals are selected to use the primary clock routing resources: sub_sec_0 (driver: sec_impl/SLICE_8, clk load #: 43) CLK_c (driver: CLK, clk load #: 14) WARNING - par: Signal "CLK_c" is selected to use Primary clock resources; however its driver comp "CLK" is located at "12", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it may suffer from excessive delay or skew. No signal is selected as secondary clock. Signal btn_sel_impl/btn_sel_ack is selected as Global Set/Reset. Starting Placer Phase 0. ....... Finished Placer Phase 0. REAL time: 16 secs Starting Placer Phase 1. ................... Placer score = 30837. Finished Placer Phase 1. REAL time: 28 secs Starting Placer Phase 2. . Placer score = 30542 Finished Placer Phase 2. REAL time: 28 secs Clock Report Global Clock Resources: CLK_PIN : 0 out of 8 (0%) General PIO: 1 out of 56 (1%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY "sub_sec_0" from Q1 on comp "sec_impl/SLICE_8" on site "R2C5A", clk load = 43 PRIMARY "CLK_c" from comp "CLK" on PIO site "12 (PB4B)", clk load = 14 PRIMARY : 2 out of 8 (25%) SECONDARY: 0 out of 8 (0%) I/O Usage Summary (final): 17 out of 56 (30.4%) PIO sites used. 17 out of 22 (77.3%) bonded PIO sites used. Number of PIO comps: 17; differential: 0 Number of Vref pins used: 0 I/O Bank Usage Summary: +----------+--------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+--------------+------------+-----------+ | 0 | 4 / 9 ( 44%) | 3.3V | - | | 1 | 2 / 2 (100%) | 3.3V | - | | 2 | 9 / 9 (100%) | 3.3V | - | | 3 | 2 / 2 (100%) | 3.3V | - | +----------+--------------+------------+-----------+ Total placer CPU time: 13 secs Dumping design to file qfn32samples_clock1.dir/5_1.ncd. 0 connections routed; 1032 unrouted. Starting router resource preassignment WARNING - par: The driver of primary clock net CLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource or will be routed as a secondary clock and may suffer from excessive delay or skew. Completed router resource preassignment. Real time: 30 secs Starting iterative routing. For each routing iteration the number inside the parenthesis is the total time (in picoseconds) the design is failing the timing constraints. For each routing iteration the router will attempt to reduce this number until the number of routing iterations is completed or the value is 0 meaning the design has fully met the timing constraints. End of iteration 1 1032 successful; 0 unrouted; (0) real time: 31 secs Dumping design to file qfn32samples_clock1.dir/5_1.ncd. Total CPU time 14 secs Total REAL time: 31 secs Completely routed. End of route. 1032 routed (100.00%); 0 unrouted. Checking DRC ... No errors found. Timing score: 0 Total REAL time to completion: 37 secs Dumping design to file qfn32samples_clock1.dir/5_1.ncd. All signals are completely routed. par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.