Lattice Mapping Report File for Design Module 'dacx'


Design Information

Command line:   map -a MachXO2 -p LCMXO2-256HC -t QFN32 -s 4 -oc Commercial
     qfn32samples_dac.ngd -o qfn32samples_dac_map.ncd -pr qfn32samples_dac.prf
     -mp qfn32samples_dac.mrp C:/Documents and Settings/suz/My
     Documents/lattice/xo2qfn-w06/qfn32samples.lpf -c 0
Target Vendor:  LATTICE
Target Device:  LCMXO2-256HCQFN32
Target Performance:   4
Mapper:  xo2c00,  version:  Diamond_1.4_Production (87)
Mapped on:  06/21/12  23:34:06


Design Summary
   Number of registers:    23
      PFU registers:    22
      PIO registers:    1
   Number of SLICEs:            16 out of   128 (13%)
      SLICEs(logic/ROM):        16 out of    32 (50%)
      SLICEs(logic/ROM/RAM):     0 out of    96 (0%)
          As RAM:            0 out of    96 (0%)
          As Logic/ROM:      0 out of    96 (0%)
   Number of logic LUT4s:      28
   Number of distributed RAM:   0 (0 LUT4s)
   Number of ripple logic:      0 (0 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:      28
   Number of PIO sites used: 8 out of 22 (36%)
   Number of block RAMs:  0 out of 0
   Number of GSRs:  0 out of 1 (0%)
   EFB used :       No
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   POR :            On
   Bandgap :        On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  2
     Net CLK_c: 9 loads, 6 rising, 3 falling (Driver: PIO CLK )
     Net hi_clk_2: 7 loads, 7 rising, 0 falling (Driver: hi_clk_17__i2 )
   Number of Clock Enables:  1
     Net dac_hi/n83: 2 loads, 2 LSLICEs
   Number of LSRs:  2
     Net dac_lo/n7: 3 loads, 2 LSLICEs
     Net dac_hi/n83: 1 loads, 1 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:

     Net dac_hi/n83: 8 loads
     Net dac_lo/n7: 6 loads
     Net dac_lo/count_0: 4 loads
     Net dac_hi/fraction_0: 3 loads
     Net dac_lo/count_1: 3 loads
     Net dac_lo/fraction_0: 3 loads
     Net hi_out_0: 3 loads
     Net I_DATA_c_2: 3 loads
     Net I_DATA_c_3: 3 loads
     Net I_DATA_c_4: 3 loads




   Number of warnings:  6
   Number of errors:    0




Design Errors/Warnings

WARNING: input pad net 'I_DATA_7' has no legal load
WARNING: input pad net 'I_DATA_6' has no legal load
WARNING: input pad net 'I_DATA_5' has no legal load
WARNING: IO buffer missing for top level port I_DATA[7:0](7)...logic will be
     discarded.
WARNING: IO buffer missing for top level port I_DATA[7:0](6)...logic will be
     discarded.
WARNING: IO buffer missing for top level port I_DATA[7:0](5)...logic will be
     discarded.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| STB                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| CLK                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| n440                | OUTPUT    | LVCMOS25  | OUT        |
+---------------------+-----------+-----------+------------+
| I_DATA_4            | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| I_DATA_3            | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| I_DATA_2            | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| I_DATA_1            | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| I_DATA_0            | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+






Removed logic

Block m0_lut undriven or does not drive anything - clipped.
Block i2 undriven or does not drive anything - clipped.
Block GSR_INST undriven or does not drive anything - clipped.
Signal n441 was merged into signal CLK_c
Signal n436 undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.
Block i4 was optimized away.



Memory Usage




Run Time and Memory Usage
-------------------------

   Total CPU Time: 0 secs
   Total REAL Time: 0 secs
   Peak Memory Usage: 22 MB







































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