Synthesis and Ngdbuild Report #Build: Synplify Pro F-2011.09L, Build 022R, Oct 19 2011 #install: C:\lscc\diamond\1.4\synpbase #OS: Windows XP 5.1 #Hostname: BANDIT $ Start of Compile #Sat Jun 09 17:40:52 2012 Synopsys Verilog Compiler, version comp560rcp1, Build 045R, built Oct 18 2011 @N|Running in 32-bit mode Copyright (C) 1994-2011 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. @I::"C:\lscc\diamond\1.4\synpbase\lib\lucent\machxo2.v" @I::"C:\lscc\diamond\1.4\synpbase\lib\vlog\scemi_objects.v" @I::"C:\lscc\diamond\1.4\synpbase\lib\vlog\hypermods.v" @I::"C:\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo2.v" @I::"C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\sram128\source\sram128.v" Verilog syntax check successful! File C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\sram128\source\sram128.v changed - recompiling Selecting top level module sram128 @N: CG364 :"C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\sram128\source\sram128.v":33:7:33:10|Synthesizing module sram SIZE=32'b00000000000000000000000010000000 Generated name = sram_128s @N: CL134 :"C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\sram128\source\sram128.v":43:4:43:9|Found RAM mem, depth=128, width=8 @N: CG364 :"C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\sram128\source\sram128.v":18:7:18:13|Synthesizing module sram128 @W: CL247 :"C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\sram128\source\sram128.v":38:28:38:32|Input port bit 7 of ADDRB[7:0] is unused @END Premap Report (contents appended below) @N:"C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\sram128\synlog\qfn32samples_sram128_premap.srr" Synopsys Lattice Technology Pre-mapping, Version maplat, Build 239R, Built Oct 19 2011 10:56:21 Copyright (C) 1994-2011, Synopsys Inc. All Rights Reserved Product Version F-2011.09L Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N: MF249 |Running in 32-bit mode. @N: MF257 |Gated clock conversion enabled @N: MF546 |Generated clock conversion enabled Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) syn_allowed_resources : blockrams=0 set on top level netlist sram128 Finished Pre Mapping Phase. (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 76MB) Pre Mapping successful! At Mapper Exit (Time elapsed 0h:00m:01s; Memory used current: 42MB peak: 76MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sat Jun 09 17:40:56 2012 ###########################################################] Map & Optimize Report (contents appended below) @N:"C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\sram128\synlog\qfn32samples_sram128_fpga_mapper.srr" Synopsys Lattice Technology Mapper, Version maplat, Build 239R, Built Oct 19 2011 10:56:21 Copyright (C) 1994-2011, Synopsys Inc. All Rights Reserved Product Version F-2011.09L Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N: MF249 |Running in 32-bit mode. @N: MF257 |Gated clock conversion enabled @N: MF546 |Generated clock conversion enabled Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N: MF203 |Set autoconstraint_io Starting Optimization and Mapping (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 76MB) Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 76MB) Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 76MB) #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[ ====================================================================================== Instance:Pin Generated Clock Optimization Status ====================================================================================== ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################] Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 76MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 76MB) Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 76MB) Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 76MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 76MB) Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 76MB) Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 76MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ ------------------------------------------------------------ Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 76MB) @N: FX164 |The option to pack flops in the IOB has not been specified @N: FO126 :"c:\documents and settings\suz\my documents\lattice\xo2qfn\sram128\source\sram128.v":43:4:43:9|Generating RAM II_0.mem[7:0] Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 74MB peak: 76MB) Writing Analyst data base C:\Documents and Settings\suz\My Documents\lattice\xo2qfn\sram128\qfn32samples_sram128.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:03s; Memory used current: 74MB peak: 76MB) Writing EDIF Netlist and constraint files F-2011.09L Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 79MB) Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:05s; Memory used current: 78MB peak: 79MB) @N: MF276 |Gated clock conversion enabled, but no gated clocks found in design Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:05s; Memory used current: 78MB peak: 79MB) Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:05s; Memory used current: 78MB peak: 79MB) @N: MF333 |Generated clock conversion enabled, but no generated clocks found in design Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:05s; Memory used current: 78MB peak: 79MB) @W: MT420 |Found inferred clock sram128|WE with period 1000.00ns. Please declare a user-defined clock on object "p:WE" ##### START OF TIMING REPORT #####[ # Timing Report written on Sat Jun 09 17:41:02 2012 # Top view: sram128 Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 3 Constraint File(s): @N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing. Performance Summary ******************* Worst slack in design: 992.449 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------- sram128|WE 1.0 MHz 184.4 MHz 1000.000 5.424 994.576 inferred Inferred_clkgroup_0 System 1.0 MHz 132.4 MHz 1000.000 7.551 992.449 system system_clkgroup ======================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------- System System | 1000.000 992.449 | No paths - | No paths - | No paths - System sram128|WE | 1000.000 996.636 | No paths - | No paths - | No paths - sram128|WE System | 1000.000 994.576 | No paths - | No paths - | No paths - ================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* Input Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock -------------------------------------------------------------------------- A[0] System (rising) NA 0.000 997.724 A[1] System (rising) NA 0.000 997.724 A[2] System (rising) NA 0.000 997.724 A[3] System (rising) NA 0.000 997.724 A[4] System (rising) NA 0.000 993.272 A[5] System (rising) NA 0.000 993.272 A[6] System (rising) NA 0.000 993.272 A[7] NA NA NA NA NA D[0] System (rising) NA 0.000 998.588 D[1] System (rising) NA 0.000 998.588 D[2] System (rising) NA 0.000 998.588 D[3] System (rising) NA 0.000 998.588 D[4] System (rising) NA 0.000 998.588 D[5] System (rising) NA 0.000 998.588 D[6] System (rising) NA 0.000 998.588 D[7] System (rising) NA 0.000 998.588 OE System (rising) NA 0.000 992.745 WE System (rising) NA 0.000 992.449 ========================================================================== Output Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock -------------------------------------------------------------------------- D[0] System (rising) NA 7.551 1000.000 D[1] System (rising) NA 7.551 1000.000 D[2] System (rising) NA 7.551 1000.000 D[3] System (rising) NA 7.551 1000.000 D[4] System (rising) NA 7.551 1000.000 D[5] System (rising) NA 7.551 1000.000 D[6] System (rising) NA 7.551 1000.000 D[7] System (rising) NA 7.551 1000.000 ========================================================================== ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report Part: lcmxo2_256hc-4 Register bits: 0 of 256 (0%) PIC Latch: 0 I/O cells: 17 Details: BB: 8 GSR: 1 IB: 9 MUX81: 8 ORCALUT4: 9 PUR: 1 SPR16X4C: 16 VHI: 1 VLO: 1 false: 2 true: 2 Mapper successful! At Mapper Exit (Time elapsed 0h:00m:05s; Memory used current: 24MB peak: 79MB) Process took 0h:00m:06s realtime, 0h:00m:05s cputime # Sat Jun 09 17:41:02 2012 ###########################################################]