Lattice Mapping Report File for Design Module 'alu381'


Design Information

Command line:   map -a MachXO2 -p LCMXO2-256HC -t QFN32 -s 4 -oc Commercial
     qfn32samples_alu381.ngd -o qfn32samples_alu381_map.ncd -pr
     qfn32samples_alu381.prf -mp qfn32samples_alu381.mrp C:/Documents and
     Settings/suz/My Documents/lattice/qfn32samples-02/qfn32samples.lpf -c 0
Target Vendor:  LATTICE
Target Device:  LCMXO2-256HCQFN32
Target Performance:   4
Mapper:  xo2c00,  version:  Diamond_1.4_Production (87)
Mapped on:  06/12/12  22:50:47


Design Summary
   Number of registers:    0
      PFU registers:    0
      PIO registers:    0
   Number of SLICEs:            17 out of   128 (13%)
      SLICEs(logic/ROM):        17 out of    32 (53%)
      SLICEs(logic/ROM/RAM):     0 out of    96 (0%)
          As RAM:            0 out of    96 (0%)
          As Logic/ROM:      0 out of    96 (0%)
   Number of logic LUT4s:      34
   Number of distributed RAM:   0 (0 LUT4s)
   Number of ripple logic:      0 (0 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:      34
   Number of PIO sites used: 20 out of 22 (91%)
   Number of block RAMs:  0 out of 0
   Number of GSRs:  0 out of 1 (0%)
   EFB used :       No
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   POR :            On
   Bandgap :        On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  0
   Number of Clock Enables:  0
   Number of LSRs:  0
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net S_c_1: 10 loads
     Net FS_2: 8 loads
     Net n2: 8 loads
     Net S_c_0: 7 loads
     Net S_c_2: 7 loads

     Net alu_impl/n62: 6 loads
     Net alu_impl/D_0: 5 loads
     Net alu_impl/n72: 5 loads
     Net alu_impl/n168: 4 loads
     Net alu_impl/n737: 4 loads




   Number of warnings:  0
   Number of errors:    0




Design Errors/Warnings

   No errors or warnings present.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| S_0                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| S_1                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| S_2                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| B_0                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| B_1                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| B_2                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| B_3                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| A_0                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| A_1                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| A_2                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| A_3                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| C_IN                | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| OVR                 | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| C_OUT               | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| G                   | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| P                   | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+

| F_0                 | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| F_1                 | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| F_2                 | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| F_3                 | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+



Removed logic

Block i1166 undriven or does not drive anything - clipped.
Block GSR_INST undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.



Memory Usage




Run Time and Memory Usage
-------------------------

   Total CPU Time: 0 secs
   Total REAL Time: 0 secs
   Peak Memory Usage: 22 MB
































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