Synthesis and Ngdbuild Report synthesis: version Diamond_1.4_Production (87) Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Thu Jun 21 21:18:50 2012 Command Line: synthesis -f qfn32samples_test_lattice.synproj -- all messages logged in file synthesis.log Synthesis Options INFO: Synthesis Options: (LSE-1022) INFO: -a option is = MachXO2 INFO: -s option is = 4 INFO: -t option is = QFN32 INFO: -d option is = LCMXO2-256HC INFO: Using package QFN32 INFO: Using performance grade 4 INFO: INFO: ########################################################## INFO: ### Lattice Family : MachXO2 INFO: ### Device : LCMXO2-256HC INFO: ### Package : QFN32 INFO: ### Speed : 4 INFO: ########################################################## INFO: INFO: Optimization Goal = Area INFO: -top option is not used WARNING: Ignoring Frequency option in Area Mode, Setting to default frequency of 1.0 MHz INFO: Target Frequency = 1.000000 MHz INFO: Max Fanout = 1000 INFO: Timing Path count = 3 INFO: bram Utilization = 100.000000 % INFO: dsp usage = TRUE (default) INFO: dsp utilization = 100 (default) INFO: fsm_encoding_style = auto INFO: Mux style = Auto INFO: Use Carry Chain = TRUE INFO: carry_chain_length = 0 INFO: Use IO Insertion = TRUE INFO: Use IO Reg = TRUE INFO: Resource Sharing = TRUE INFO: Propagate Constants = TRUE INFO: Remove Duplicate Registers = TRUE INFO: force_gsr = auto INFO: ROM style = auto INFO: RAM style = auto INFO: -comp option is FALSE INFO: -syn option is FALSE INFO: -p C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-w06 (searchpath added) INFO: -p C:/lscc/diamond/1.4/ispfpga/xo2c00/data (searchpath added) INFO: -p C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-w06/test (searchpath added) INFO: -p C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-w06 (searchpath added) INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-w06/src/dac_sd.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-w06/src/dac_sdx.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-w06/src/dac_sd3.v INFO: Ngd file = qfn32samples_test.ngd INFO: -sdc option: sdc file input not used INFO: -lpf option: output file option is OFF INFO: hardtimer checking is enabled (default); -dt option not used INFO: -r option is OFF [ Remove LOC Properties is OFF ] -- Technology check ok...MachXO, MachXO2... INFO: The default vhdl library search path is now "c:/lscc/diamond/1.4/cae_library/vhdl_packages/vdbs" (VHDL-1504) INFO: * compile design * Compile Design INFO: Compile Design Begin c:/documents and settings/suz/my documents/lattice/xo2qfn-w06/src/dac_sdx.v(19): INFO: compiling module dacx (VERI-1018) c:/documents and settings/suz/my documents/lattice/xo2qfn-w06/src/dac_sd.v(16): INFO: compiling module dac(WIDTH=3,WITH_LATCH=0) (VERI-1018) c:/documents and settings/suz/my documents/lattice/xo2qfn-w06/src/dac_sd3.v(18): INFO: compiling module dac3(WIDTH=5) (VERI-1018) INFO: GSR Instance connected to net: n1 (LSE-1148) INFO: GSR will not be inferred since no asynchronous signal was found in netlist (LSE-1147) INFO: Duplicate Register/Latch removal : \dac_hi/r_data_i0_i4 is one to one match with \dac_hi/r_data_i0_i3 WARNING: No lpf file will be written because -lpf option is not used or set to 0 INFO: Applying 1.000000 MHz constraint to all clocks (LSE-5000) INFO: Results of ngd drc checks are available in dacx_drc.log INFO: All blocks are expanded and NGD expansion is successful INFO: Writing ngd file qfn32samples_test.ngd ################### Begin Area Report (dacx)###################### Number of register bits => 23 of 1090 (2 % ) FD1P3AX => 4 FD1S3AX => 12 FD1S3IX => 5 FD1S3JX => 1 GSR => 1 IB => 7 INV => 4 LUT4 => 25 OB => 1 OFS1P3IX => 1 PFUMX => 1 ################### End Area Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 2 Net : hi_clk_2, loads : 12 Net : CLK_c, loads : 11 Clock Enable Nets Number of Clock Enables: 2 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : n17, loads : 11 Net : n7, loads : 7 Net : count_0, loads : 4 Net : I_DATA2_2, loads : 4 Net : n441, loads : 3 Net : n3, loads : 3 Net : fraction_0, loads : 3 Net : count_1, loads : 3 Net : fraction_0, loads : 3 Net : r_data_2, loads : 3 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 1000.000000 -name | | | clk1 [get_nets CLK_c] | 1.000 MHz| 145.666 MHz| 4 | | | create_clock -period 1000.000000 -name | | | clk0 [get_nets hi_clk[2]] | 1.000 MHz| 182.548 MHz| 3 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 39.543 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 3.656 secs --------------------------------------------------------------