Map TRACE Report

Loading design for application trce from file qfn32samples_mcpu_efb_map.ncd.
Design name: mcpu_efb
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-256HC
Package:     QFN32
Performance: 4
Loading device for application trce from file 'xo2c256.nph' in environment: C:/lscc/diamond/1.4/ispfpga.
Package Status:                     Advanced       Version 1.34
Performance Hardware Data Status:   Final)         Version 22.4
Setup and Hold Report

--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond_1.4_Production (87)
Wed Jun 20 20:39:22 2012

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o qfn32samples_mcpu_efb.tw1 qfn32samples_mcpu_efb_map.ncd qfn32samples_mcpu_efb.prf 
Design file:     qfn32samples_mcpu_efb_map.ncd
Preference file: qfn32samples_mcpu_efb.prf
Device,speed:    LCMXO2-256HC,4
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

Preference Summary

  • FREQUENCY NET "master_clk" 134.084000 MHz (103 errors)
  • 347 items scored, 103 timing errors detected. Warning: 82.891MHz is the maximum frequency for this preference.
  • FREQUENCY NET "CLK_3X_c" 102.302000 MHz (652 errors)
  • 1010 items scored, 652 timing errors detected. Warning: 47.405MHz is the maximum frequency for this preference.
  • FREQUENCY NET "WE_mem" 205.128000 MHz (288 errors)
  • 296 items scored, 288 timing errors detected. Warning: 50.297MHz is the maximum frequency for this preference. Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "master_clk" 134.084000 MHz ; 347 items scored, 103 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 2.303ns (weighted slack = -4.606ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr_i0 (from master_clk -) Destination: FF Data in pc_i4 (to master_clk +) Delay: 5.866ns (36.9% logic, 63.1% route), 4 logic levels. Constraint Details: 5.866ns physical path delay SLICE_13 to SLICE_30 exceeds 3.729ns delay constraint less 0.166ns DIN_SET requirement (totaling 3.563ns) by 2.303ns Physical Path Details: Data path SLICE_13 to SLICE_30: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_13.CLK to SLICE_13.Q0 SLICE_13 (from master_clk) ROUTE 20 e 1.234 SLICE_13.Q0 to SLICE_35.A1 r_addr_0 CTOF_DEL --- 0.495 SLICE_35.A1 to SLICE_35.F1 SLICE_35 ROUTE 1 e 1.234 SLICE_35.F1 to *8/SLICE_39.C0 n19 CTOOFX_DEL --- 0.721 *8/SLICE_39.C0 to *SLICE_39.OFX0 i28/SLICE_39 ROUTE 13 e 1.234 *SLICE_39.OFX0 to SLICE_30.C0 n747 CTOF_DEL --- 0.495 SLICE_30.C0 to SLICE_30.F0 SLICE_30 ROUTE 1 e 0.001 SLICE_30.F0 to SLICE_30.DI0 n112 (to master_clk) -------- 5.866 (36.9% logic, 63.1% route), 4 logic levels. Warning: 82.891MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "CLK_3X_c" 102.302000 MHz ; 1010 items scored, 652 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 2.683ns (weighted slack = -11.322ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q inst_i0 (from master_clk +) Destination: EFB Port efb_impl/EFBInst_0(ASIC) (to CLK_3X_c +) Delay: 3.415ns (27.7% logic, 72.3% route), 2 logic levels. Constraint Details: 3.415ns physical path delay SLICE_20 to efb_impl/EFBInst_0 exceeds (delay constraint based on source clock period of 7.458ns and destination clock period of 9.774ns) 2.316ns delay constraint less 1.584ns WBWEI_SET requirement (totaling 0.732ns) by 2.683ns Physical Path Details: Data path SLICE_20 to efb_impl/EFBInst_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_20.CLK to SLICE_20.Q1 SLICE_20 (from master_clk) ROUTE 7 e 1.234 SLICE_20.Q1 to SLICE_52.C1 inst_0 CTOF_DEL --- 0.495 SLICE_52.C1 to SLICE_52.F1 SLICE_52 ROUTE 3 e 1.234 SLICE_52.F1 to *BInst_0.WBWEI WE_c (to CLK_3X_c) -------- 3.415 (27.7% logic, 72.3% route), 2 logic levels. Warning: 47.405MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "WE_mem" 205.128000 MHz ; 296 items scored, 288 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 3.529ns (weighted slack = -15.012ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q rom_impl/r_addr_i0 (from master_clk -) Destination: FF Data in sram_impl/mem0/RAM0 (to WE_mem +) FF sram_impl/mem0/RAM0 Delay: 5.117ns (27.6% logic, 72.4% route), 4 logic levels. Constraint Details: 5.117ns physical path delay SLICE_13 to SLICE_13 exceeds (delay constraint based on source clock period of 7.458ns and destination clock period of 4.875ns) 1.146ns delay constraint less -0.442ns WAD_SET requirement (totaling 1.588ns) by 3.529ns Physical Path Details: Data path SLICE_13 to SLICE_13: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 SLICE_13.CLK to SLICE_13.Q0 SLICE_13 (from master_clk) ROUTE 20 e 1.234 SLICE_13.Q0 to *0/SLICE_42.D1 r_addr_0 CTOOFX_DEL --- 0.721 *0/SLICE_42.D1 to *SLICE_42.OFX0 i710/SLICE_42 ROUTE 1 e 0.001 *SLICE_42.OFX0 to */SLICE_41.FXA n1290 FXTOOFX_DE --- 0.241 */SLICE_41.FXA to *SLICE_41.OFX1 i711/SLICE_41 ROUTE 13 e 1.234 *SLICE_41.OFX1 to *0/SLICE_12.D0 n748 ZERO_DEL --- 0.000 *0/SLICE_12.D0 to *LICE_12.WADO3 sram_impl/mem0/SLICE_12 ROUTE 2 e 1.234 *LICE_12.WADO3 to SLICE_13.WAD3 sram_impl/mem0/AD3_INT (to WE_mem) -------- 5.117 (27.6% logic, 72.4% route), 4 logic levels. Warning: 50.297MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "master_clk" 134.084000 | | | MHz ; | 134.084 MHz| 82.891 MHz| 4 * | | | FREQUENCY NET "CLK_3X_c" 102.302000 MHz | | | ; | 102.302 MHz| 47.405 MHz| 2 * | | | FREQUENCY NET "WE_mem" 205.128000 MHz ; | 205.128 MHz| 50.297 MHz| 4 * | | | ---------------------------------------------------------------------------- 3 preferences(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- r_addr_3 | 35| 249| 23.87% | | | r_addr_1 | 35| 249| 23.87% | | | n750 | 13| 241| 23.11% | | | r_addr_2 | 33| 230| 22.05% | | | n748 | 13| 225| 21.57% | | | O_ADDR_c | 12| 223| 21.38% | | | n749 | 13| 208| 19.94% | | | r_addr_0 | 20| 143| 13.71% | | | r_addr_4 | 27| 122| 11.70% | | | n1294 | 1| 118| 11.31% | | | n1297 | 1| 118| 11.31% | | | n1296 | 1| 118| 11.31% | | | n1291 | 1| 117| 11.22% | | | rom_impl/mux_60_Mux_0_1_f5b | 1| 109| 10.45% | | | rom_impl/mux_60_Mux_0_0_f5a | 1| 109| 10.45% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 5 clocks: Clock Domain: master_clk Source: SLICE_23.Q0 Loads: 17 Covered under: FREQUENCY NET "master_clk" 134.084000 MHz ; Data transfers from: Clock Domain: CLK_3X_c Source: CLK_3X.PAD Covered under: FREQUENCY NET "master_clk" 134.084000 MHz ; Transfers: 8 Clock Domain: CLK_3X_c Source: CLK_3X.PAD Loads: 8 Covered under: FREQUENCY NET "CLK_3X_c" 102.302000 MHz ; Data transfers from: Clock Domain: master_clk Source: SLICE_23.Q0 Covered under: FREQUENCY NET "CLK_3X_c" 102.302000 MHz ; Transfers: 17 Clock Domain: WE_mem Source: SLICE_52.F0 Covered under: FREQUENCY NET "CLK_3X_c" 102.302000 MHz ; Transfers: 8 Clock Domain: i2c1_sclo Source: efb_impl/EFBInst_0.I2C1SCLO Loads: 1 No transfer within this clock domain is found Clock Domain: i2c1_scli Source: SCL.PAD Loads: 1 No transfer within this clock domain is found Clock Domain: WE_mem Source: SLICE_52.F0 Loads: 4 No transfer within this clock domain is found Data transfers from: Clock Domain: master_clk Source: SLICE_23.Q0 Covered under: FREQUENCY NET "WE_mem" 205.128000 MHz ; Transfers: 14 Timing summary (Setup): --------------- Timing errors: 1043 Score: 5003259 Cumulative negative slack: 4923765 Constraints cover 2631 paths, 4 nets, and 503 connections (93.7% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond_1.4_Production (87) Wed Jun 20 20:39:24 2012 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o qfn32samples_mcpu_efb.tw1 qfn32samples_mcpu_efb_map.ncd qfn32samples_mcpu_efb.prf Design file: qfn32samples_mcpu_efb_map.ncd Preference file: qfn32samples_mcpu_efb.prf Device,speed: LCMXO2-256HC,M Report level: verbose report, limited to 1 item per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "master_clk" 134.084000 MHz (0 errors)
  • 347 items scored, 0 timing errors detected.
  • FREQUENCY NET "CLK_3X_c" 102.302000 MHz (0 errors)
  • 1010 items scored, 0 timing errors detected.
  • FREQUENCY NET "WE_mem" 205.128000 MHz (0 errors)
  • 296 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "master_clk" 134.084000 MHz ; 347 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.443ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i1 (from master_clk +) Destination: FF Data in akku_i1 (to master_clk +) Delay: 0.430ns (53.5% logic, 46.5% route), 2 logic levels. Constraint Details: 0.430ns physical path delay SLICE_19 to SLICE_19 meets -0.013ns DIN_HLD and 0.000ns delay constraint requirement (totaling -0.013ns) by 0.443ns Physical Path Details: Data path SLICE_19 to SLICE_19: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 SLICE_19.CLK to SLICE_19.Q0 SLICE_19 (from master_clk) ROUTE 5 e 0.199 SLICE_19.Q0 to SLICE_19.A0 O_DATA_c CTOF_DEL --- 0.099 SLICE_19.A0 to SLICE_19.F0 SLICE_19 ROUTE 1 e 0.001 SLICE_19.F0 to SLICE_19.DI0 n168 (to master_clk) -------- 0.430 (53.5% logic, 46.5% route), 2 logic levels. ================================================================================ Preference: FREQUENCY NET "CLK_3X_c" 102.302000 MHz ; 1010 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.443ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q wb_stat_i0 (from CLK_3X_c +) Destination: FF Data in wb_stat_i0 (to CLK_3X_c +) Delay: 0.430ns (53.5% logic, 46.5% route), 2 logic levels. Constraint Details: 0.430ns physical path delay SLICE_34 to SLICE_34 meets -0.013ns DIN_HLD and 0.000ns delay constraint requirement (totaling -0.013ns) by 0.443ns Physical Path Details: Data path SLICE_34 to SLICE_34: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from CLK_3X_c) ROUTE 2 e 0.199 SLICE_34.Q0 to SLICE_34.B0 wb_stat_0 CTOF_DEL --- 0.099 SLICE_34.B0 to SLICE_34.F0 SLICE_34 ROUTE 3 e 0.001 SLICE_34.F0 to SLICE_34.DI0 n37 (to CLK_3X_c) -------- 0.430 (53.5% logic, 46.5% route), 2 logic levels. ================================================================================ Preference: FREQUENCY NET "WE_mem" 205.128000 MHz ; 296 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 1.032ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q akku_i1 (from master_clk +) Destination: FF Data in sram_impl/mem1/RAM0 (to WE_mem +) FF sram_impl/mem1/RAM0 Delay: 1.161ns (11.3% logic, 88.7% route), 2 logic levels. Constraint Details: 1.161ns physical path delay SLICE_19 to sram_impl/mem1/SLICE_10 meets (delay constraint based on source clock period of 7.458ns and destination clock period of 4.875ns) 0.129ns WD_HLD and 0.000ns delay constraint requirement (totaling 0.129ns) by 1.032ns Physical Path Details: Data path SLICE_19 to sram_impl/mem1/SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 SLICE_19.CLK to SLICE_19.Q0 SLICE_19 (from master_clk) ROUTE 5 e 0.515 SLICE_19.Q0 to *m1/SLICE_9.A1 O_DATA_c ZERO_DEL --- 0.000 *m1/SLICE_9.A1 to */SLICE_9.WDO0 sram_impl/mem1/SLICE_9 ROUTE 1 e 0.515 */SLICE_9.WDO0 to */SLICE_10.WD0 sram_impl/mem1/WD0_INT (to WE_mem) -------- 1.161 (11.3% logic, 88.7% route), 2 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "master_clk" 134.084000 | | | MHz ; | -| -| 2 | | | FREQUENCY NET "CLK_3X_c" 102.302000 MHz | | | ; | -| -| 2 | | | FREQUENCY NET "WE_mem" 205.128000 MHz ; | -| -| 2 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 5 clocks: Clock Domain: master_clk Source: SLICE_23.Q0 Loads: 17 Covered under: FREQUENCY NET "master_clk" 134.084000 MHz ; Data transfers from: Clock Domain: CLK_3X_c Source: CLK_3X.PAD Covered under: FREQUENCY NET "master_clk" 134.084000 MHz ; Transfers: 8 Clock Domain: CLK_3X_c Source: CLK_3X.PAD Loads: 8 Covered under: FREQUENCY NET "CLK_3X_c" 102.302000 MHz ; Data transfers from: Clock Domain: master_clk Source: SLICE_23.Q0 Covered under: FREQUENCY NET "CLK_3X_c" 102.302000 MHz ; Transfers: 17 Clock Domain: WE_mem Source: SLICE_52.F0 Covered under: FREQUENCY NET "CLK_3X_c" 102.302000 MHz ; Transfers: 8 Clock Domain: i2c1_sclo Source: efb_impl/EFBInst_0.I2C1SCLO Loads: 1 No transfer within this clock domain is found Clock Domain: i2c1_scli Source: SCL.PAD Loads: 1 No transfer within this clock domain is found Clock Domain: WE_mem Source: SLICE_52.F0 Loads: 4 No transfer within this clock domain is found Data transfers from: Clock Domain: master_clk Source: SLICE_23.Q0 Covered under: FREQUENCY NET "WE_mem" 205.128000 MHz ; Transfers: 14 Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 2631 paths, 4 nets, and 503 connections (93.7% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 1043 (setup), 0 (hold) Score: 5003259 (setup), 0 (hold) Cumulative negative slack: 4923765 (4923765+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------