Synthesis and Ngdbuild Report synthesis: version Diamond_1.4_Production (87) Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Fri Jun 15 15:23:38 2012 Command Line: synthesis -f qfn32samples_clock1_lattice.synproj -- all messages logged in file synthesis.log Synthesis Options INFO: Synthesis Options: (LSE-1022) INFO: -a option is = MachXO2 INFO: -s option is = 4 INFO: -t option is = QFN32 INFO: -d option is = LCMXO2-256HC INFO: Using package QFN32 INFO: Using performance grade 4 INFO: INFO: ########################################################## INFO: ### Lattice Family : MachXO2 INFO: ### Device : LCMXO2-256HC INFO: ### Package : QFN32 INFO: ### Speed : 4 INFO: ########################################################## INFO: INFO: Optimization Goal = Area INFO: -top option is not used WARNING: Ignoring Frequency option in Area Mode, Setting to default frequency of 1.0 MHz INFO: Target Frequency = 1.000000 MHz INFO: Max Fanout = 1000 INFO: Timing Path count = 3 INFO: bram Utilization = 100.000000 % INFO: dsp usage = TRUE (default) INFO: dsp utilization = 100 (default) INFO: fsm_encoding_style = auto INFO: Mux style = Auto INFO: Use Carry Chain = TRUE INFO: carry_chain_length = 0 INFO: Use IO Insertion = TRUE INFO: Use IO Reg = TRUE INFO: Resource Sharing = TRUE INFO: Propagate Constants = TRUE INFO: Remove Duplicate Registers = TRUE INFO: force_gsr = auto INFO: ROM style = auto INFO: RAM style = auto INFO: -comp option is FALSE INFO: -syn option is FALSE INFO: -p Z:/XC2C/qfn32samples-03 (searchpath added) INFO: -p Y:/Program_Files/lscc/diamond/1.4/ispfpga/xo2c00/data (searchpath added) INFO: -p Z:/XC2C/qfn32samples-03/clock1 (searchpath added) INFO: -p Z:/XC2C/qfn32samples-03 (searchpath added) INFO: Verilog design file = Z:/XC2C/qfn32samples-03/src/seg7dec.v INFO: Verilog design file = Z:/XC2C/qfn32samples-03/src/time_counter.v INFO: Verilog design file = Z:/XC2C/qfn32samples-03/src/button.v INFO: Verilog design file = Z:/XC2C/qfn32samples-03/src/clock1.v INFO: Ngd file = qfn32samples_clock1.ngd INFO: -sdc option: sdc file input not used INFO: -lpf option: output file option is OFF INFO: hardtimer checking is enabled (default); -dt option not used INFO: -r option is OFF [ Remove LOC Properties is OFF ] -- Technology check ok...MachXO, MachXO2... INFO: The default vhdl library search path is now "y:/program_files/lscc/diamond/1.4/cae_library/vhdl_packages/vdbs" (VHDL-1504) INFO: * compile design * Compile Design INFO: Compile Design Begin z:/xc2c/qfn32samples-03/src/clock1.v(54): INFO: compiling module clock (VERI-1018) z:/xc2c/qfn32samples-03/src/seg7dec.v(28): INFO: compiling module seg7dec (VERI-1018) z:/xc2c/qfn32samples-03/src/button.v(18): INFO: compiling module button (VERI-1018) z:/xc2c/qfn32samples-03/src/time_counter.v(21): INFO: compiling module time_counter(MAX=60) (VERI-1018) z:/xc2c/qfn32samples-03/src/time_counter.v(21): INFO: compiling module time_counter(MAX=24) (VERI-1018) INFO: ######## Missing driver on net : n363, patching with GND... (LSE-1017) z:/xc2c/qfn32samples-03/src/time_counter.v(137): WARNING: Register \sec_impl/lower_a_i0 is stuck at Zero (VDB-5013) INFO: GSR Instance connected to net: \btn_sel_impl/n19 (LSE-1148) WARNING: mRegister \btn_sel_impl/r_btn_stat_reset is stuck at Zero WARNING: mRegister \btn_up_impl/r_btn_stat_reset is stuck at Zero WARNING: mRegister \btn_sel_impl/prev_stat_reset is stuck at Zero WARNING: mRegister \btn_dn_impl/r_btn_stat_reset is stuck at Zero WARNING: mRegister \btn_up_impl/prev_stat_reset is stuck at Zero WARNING: mRegister \btn_dn_impl/prev_stat_reset is stuck at Zero WARNING: No lpf file will be written because -lpf option is not used or set to 0 INFO: Applying 1.000000 MHz constraint to all clocks (LSE-5000) INFO: Results of ngd drc checks are available in clock_drc.log INFO: All blocks are expanded and NGD expansion is successful INFO: Writing ngd file qfn32samples_clock1.ngd ################### Begin Area Report (clock)###################### Number of register bits => 85 of 1090 (7 % ) CCU2D => 14 FD1P3AX => 18 FD1P3IX => 23 FD1P3JX => 2 FD1S1A => 1 FD1S1B => 6 FD1S1D => 5 FD1S3AX => 13 FD1S3IX => 17 GSR => 1 IB => 4 INV => 8 L6MUX21 => 4 LUT4 => 194 MUX41 => 4 OB => 12 OBZ => 1 PFUMX => 16 ################### End Area Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 11 Net : n25, loads : 42 Net : sub_sec_0, loads : 9 Net : n4, loads : 7 Net : GND_net, loads : 6 Net : BTN_DN_c, loads : 4 Net : BTN_UP_c, loads : 4 Net : BTN_SEL_c, loads : 4 Net : n1402, loads : 2 Net : n1527, loads : 2 Net : n1404, loads : 2 Net : CLK_c, loads : 1 Clock Enable Nets Number of Clock Enables: 6 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : alarm_mode, loads : 40 Net : sub_sec_1, loads : 22 Net : n28, loads : 17 Net : n5, loads : 15 Net : n1, loads : 14 Net : lower_a_0, loads : 11 Net : sec_up_i, loads : 11 Net : n137, loads : 11 Net : set_mode_1, loads : 10 Net : set_mode_0, loads : 10 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 1000.000000 -name | | | clk8 [get_nets \btn_sel_impl/n1402] | -| -| 0 | | | create_clock -period 1000.000000 -name | | | clk7 [get_nets BTN_SEL_c] | -| -| 0 | | | create_clock -period 1000.000000 -name | | | clk6 [get_nets BTN_DN_c] | -| -| 0 | | | create_clock -period 1000.000000 -name | | | clk5 [get_nets \btn_dn_impl/n1404] | -| -| 0 | | | create_clock -period 1000.000000 -name | | | clk4 [get_nets BTN_UP_c] | -| -| 0 | | | create_clock -period 1000.000000 -name | | | clk3 [get_nets \btn_up_impl/n1527] | -| -| 0 | | | create_clock -period 1000.000000 -name | | | clk2 [get_nets GND_net] | -| -| 0 | | | create_clock -period 1000.000000 -name | | | clk1 [get_nets CLK_c] | 1.000 MHz| 93.853 MHz| 10 | | | create_clock -period 1000.000000 -name | | | clk0 [get_nets sub_sec[0]] | 1.000 MHz| 38.397 MHz| 8 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 41.879 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 6.188 secs --------------------------------------------------------------