Synthesis and Ngdbuild  Report
synthesis:  version Diamond_1.4_Production (87) 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp.   All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved. Copyright (c) 2001 Agere Systems   All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.
Wed Jun 20 22:09:10 2012 

Command Line:  synthesis -f qfn32samples_mcpu_efb_lattice.synproj 

-- all messages logged in file synthesis.log

Synthesis Options

INFO: Synthesis Options: (LSE-1022)
INFO: -a option is = MachXO2
INFO: -s option is = 4
INFO: -t option is = QFN32
INFO: -d option is = LCMXO2-256HC
INFO: Using package QFN32
INFO: Using performance grade 4
INFO:                                                           
INFO: ##########################################################
INFO: ### Lattice Family : MachXO2
INFO: ### Device  : LCMXO2-256HC
INFO: ### Package : QFN32
INFO: ### Speed   : 4
INFO: ##########################################################
INFO:                                                           
INFO: Optimization Goal = Area
INFO: -top option is not used
WARNING: Ignoring Frequency option in Area Mode, Setting to default frequency of 1.0 MHz
INFO: Target Frequency = 1.000000 MHz
INFO: Max Fanout = 1000
INFO: Timing Path count = 3
INFO: bram Utilization = 100.000000 %
INFO: dsp usage = TRUE (default)
INFO: dsp utilization = 100 (default)
INFO: fsm_encoding_style = auto
INFO: Mux style = Auto
INFO: Use Carry Chain = TRUE
INFO: carry_chain_length = 0
INFO: Use IO Insertion = TRUE
INFO: Use IO Reg = TRUE
INFO: Resource Sharing = TRUE
INFO: Propagate Constants = TRUE
INFO: Remove Duplicate Registers = TRUE
INFO: force_gsr = auto
INFO: ROM style = auto
INFO: RAM style = auto
INFO: -comp option is FALSE
INFO: -syn option is FALSE
INFO: -p C:/Documents and Settings/suz/My Documents/lattice/qfn32samples-05 (searchpath added)
INFO: -p C:/lscc/diamond/1.4/ispfpga/xo2c00/data (searchpath added)
INFO: -p C:/Documents and Settings/suz/My Documents/lattice/qfn32samples-05/mcpu_efb (searchpath added)
INFO: -p C:/Documents and Settings/suz/My Documents/lattice/qfn32samples-05 (searchpath added)
INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/lattice/qfn32samples-05/src/EFB_tc_i2c.v
INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/lattice/qfn32samples-05/src/mcpu1_efb.v
INFO: Ngd file = qfn32samples_mcpu_efb.ngd
INFO: -sdc option: sdc file input not used
INFO: -lpf option: output file option is OFF
INFO: hardtimer checking is enabled (default); -dt option not used
INFO: -r option is OFF [ Remove LOC Properties is OFF ]
-- Technology check ok...MachXO, MachXO2...
INFO: The default vhdl library search path is now "c:/lscc/diamond/1.4/cae_library/vhdl_packages/vdbs" (VHDL-1504)
INFO: * compile design *

Compile Design

INFO: Compile Design Begin
c:/documents and settings/suz/my documents/lattice/qfn32samples-05/src/mcpu1_efb.v(56): INFO: compiling module mcpu_efb (VERI-1018)
c:/documents and settings/suz/my documents/lattice/qfn32samples-05/src/efb_tc_i2c.v(8): INFO: compiling module EFB_tc_i2c (VERI-1018)
c:/documents and settings/suz/my documents/lattice/qfn32samples-05/src/mcpu1_efb.v(193): INFO: compiling module sram (VERI-1018)
c:/documents and settings/suz/my documents/lattice/qfn32samples-05/src/mcpu1_efb.v(231): INFO: compiling module rom (VERI-1018)
c:/documents and settings/suz/my documents/lattice/qfn32samples-05/src/mcpu1_efb.v(240): WARNING: ram mem_original_ramnet has no write-port on it (VDB-1038)
INFO: ######## Missing driver on net : \efb_impl/tc_ic, patching with GND... (LSE-1017)


WARNING: No available RAMs found... (LSE-1105)
WARNING: No available RAMs found... (LSE-1105)
INFO: ######## Found 1 RAM Nets in design (LSE-1115)
INFO: RAM \sram_impl/mem will be mapped to logic due to lack of resources. In order to map to EBR retarget to bigger part (LSE-1116)
INFO: ######## Mapping RAM Net \sram_impl/mem to 2 Distributed blocks in PSEUDO_DUAL_PORT Mode
WARNING: No available RAMs found... (LSE-1105)
WARNING: Skipping pad insertion on SCL due to black_box_pad_pin attribute (LSE-1155)
WARNING: Skipping pad insertion on SDA due to black_box_pad_pin attribute (LSE-1155)
INFO: GSR Instance connected to net: n1 (LSE-1148)
INFO: GSR will not be inferred since no asynchronous signal was found in netlist (LSE-1147)
WARNING: No lpf file will be written because -lpf option is not used or set to 0
INFO: Applying 1.000000 MHz constraint to all clocks (LSE-5000)
INFO: Results of ngd drc checks are available in mcpu_efb_drc.log
INFO: All blocks are expanded and NGD expansion is successful
INFO: Writing ngd file qfn32samples_mcpu_efb.ngd

################### Begin Area Report (mcpu_efb)######################
Number of register bits => 58 of 1090 (5 % )
BB => 2
CCU2D => 9
DPR16X4C => 2
EFB => 1
FD1P3IX => 9
FD1S3AX => 38
FD1S3IX => 9
FD1S3JX => 2
GSR => 1
IB => 2
INV => 3
L6MUX21 => 4
LUT4 => 64
OB => 15
PFUMX => 9
ROM64X1A => 5
################### End Area Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 3
  Net : CLK_3X_c, loads : 30
  Net : master_clk, loads : 28
  Net : n4, loads : 5
Clock Enable Nets
Number of Clock Enables: 2
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : r_addr_3, loads : 23
  Net : r_addr_1, loads : 23
  Net : RST_c, loads : 21
  Net : r_addr_2, loads : 21
  Net : r_addr_0, loads : 20
  Net : n788, loads : 16
  Net : r_addr_4, loads : 15
  Net : r_addr_5, loads : 10
  Net : n892, loads : 8
  Net : n1449, loads : 8
################### End Clock Report ##################

Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk1 [get_nets master_clk]              |    1.000 MHz|   66.041 MHz|     5  
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk0 [get_nets CLK_3X_c]                |    1.000 MHz|  182.815 MHz|     3  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.


Peak Memory Usage: 40.746  MB

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Elapsed CPU time for LSE flow : 6.469  secs
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