Synthesis and Ngdbuild Report synthesis: version Diamond_1.4_Production (87) Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Mon Jun 18 08:48:13 2012 Command Line: synthesis -f qfn32samples_mcpu_lattice.synproj -- all messages logged in file synthesis.log Synthesis Options INFO: Synthesis Options: (LSE-1022) INFO: -a option is = MachXO2 INFO: -s option is = 4 INFO: -t option is = QFN32 INFO: -d option is = LCMXO2-256HC INFO: Using package QFN32 INFO: Using performance grade 4 INFO: INFO: ########################################################## INFO: ### Lattice Family : MachXO2 INFO: ### Device : LCMXO2-256HC INFO: ### Package : QFN32 INFO: ### Speed : 4 INFO: ########################################################## INFO: INFO: Optimization Goal = Area INFO: -top option is not used WARNING: Ignoring Frequency option in Area Mode, Setting to default frequency of 1.0 MHz INFO: Target Frequency = 1.000000 MHz INFO: Max Fanout = 1000 INFO: Timing Path count = 3 INFO: bram Utilization = 100.000000 % INFO: dsp usage = TRUE (default) INFO: dsp utilization = 100 (default) INFO: fsm_encoding_style = auto INFO: Mux style = Auto INFO: Use Carry Chain = TRUE INFO: carry_chain_length = 0 INFO: Use IO Insertion = TRUE INFO: Use IO Reg = TRUE INFO: Resource Sharing = TRUE INFO: Propagate Constants = TRUE INFO: Remove Duplicate Registers = TRUE INFO: force_gsr = auto INFO: ROM style = auto INFO: RAM style = auto INFO: -comp option is FALSE INFO: -syn option is FALSE INFO: -p Z:/XC2C/xo2qfn (searchpath added) INFO: -p Y:/Program_Files/lscc/diamond/1.4/ispfpga/xo2c00/data (searchpath added) INFO: -p Z:/XC2C/xo2qfn/mcpu (searchpath added) INFO: -p Z:/XC2C/xo2qfn (searchpath added) INFO: Verilog design file = Z:/XC2C/xo2qfn/src/mcpu.v INFO: Ngd file = qfn32samples_mcpu.ngd INFO: -sdc option: sdc file input not used INFO: -lpf option: output file option is OFF INFO: hardtimer checking is enabled (default); -dt option not used INFO: -r option is OFF [ Remove LOC Properties is OFF ] -- Technology check ok...MachXO, MachXO2... INFO: The default vhdl library search path is now "y:/program_files/lscc/diamond/1.4/cae_library/vhdl_packages/vdbs" (VHDL-1504) INFO: * compile design * Compile Design INFO: Compile Design Begin z:/xc2c/xo2qfn/src/mcpu.v(52): INFO: compiling module mcpu (VERI-1018) z:/xc2c/xo2qfn/src/mcpu.v(112): INFO: compiling module sram (VERI-1018) INFO: ######## Found 1 RAM Nets in design (LSE-1115) INFO: RAM \sram_impl/mem will be mapped to logic due to lack of resources. In order to map to EBR retarget to bigger part (LSE-1116) INFO: ######## Mapping RAM Net \sram_impl/mem to 8 Distributed blocks in PSEUDO_DUAL_PORT Mode INFO: Combinational loop found : 1 INFO: Net states[0] INFO: Instance mux_25_i1 INFO: Net n380 INFO: Instance i129 INFO: Net \equal_110/n5 INFO: Instance equal_110_i5 INFO: Combinational loop found : 2 INFO: Net n380 INFO: Instance i129 INFO: Net \equal_110/n5 INFO: Instance equal_110_i5 INFO: Net states[1] INFO: Instance mux_25_i2 INFO: GSR Instance connected to net: RST_c (LSE-1148) WARNING: No lpf file will be written because -lpf option is not used or set to 0 INFO: Applying 1.000000 MHz constraint to all clocks (LSE-5000) INFO: Results of ngd drc checks are available in mcpu_drc.log INFO: All blocks are expanded and NGD expansion is successful INFO: Writing ngd file qfn32samples_mcpu.ngd ################### Begin Area Report (mcpu)###################### Number of register bits => 21 of 1090 (1 % ) CCU2D => 5 DPR16X4C => 8 FD1S1A => 9 FD1S1I => 6 FD1S3AX => 6 GSR => 1 IB => 2 INV => 4 LUT4 => 38 MUX41 => 8 OB => 1 ################### End Area Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 5 Net : n5, loads : 17 Net : n4, loads : 14 Net : n141, loads : 8 Net : n137, loads : 1 Net : CLK_c, loads : 1 Clock Enable Nets Number of Clock Enables: 0 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : RST_c, loads : 14 Net : adreg_0, loads : 10 Net : adreg_3, loads : 9 Net : adreg_2, loads : 9 Net : adreg_1, loads : 9 Net : n5_adj_1, loads : 9 Net : I_DATA_7, loads : 8 Net : r_addr_0, loads : 8 Net : r_addr_1, loads : 8 Net : r_addr_2, loads : 8 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 1000.000000 -name | | | clk3 [get_nets CLK_c] | -| -| 0 | | | create_clock -period 1000.000000 -name | | | clk2 [get_nets n137] | 1.000 MHz| 85.594 MHz| 7 | | | create_clock -period 1000.000000 -name | | | clk1 [get_nets n5] | 1.000 MHz| 123.229 MHz| 5 | | | create_clock -period 1000.000000 -name | | | clk0 [get_nets n141] | 1.000 MHz| 158.907 MHz| 6 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 39.605 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 2.625 secs --------------------------------------------------------------