Map TRACE Report
Loading design for application trce from file qfn32samples_clock1_map.ncd.
Design name: clock
NCD version: 3.2
Vendor: LATTICE
Device: LCMXO2-256HC
Package: QFN32
Performance: 4
Loading device for application trce from file 'xo2c256.nph' in environment: Y:/Program_Files/lscc/diamond/1.4/ispfpga.
Package Status: Advanced Version 1.34
Performance Hardware Data Status: Final) Version 22.4
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond_1.4_Production (87)
Fri Jun 15 15:12:22 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o qfn32samples_clock1.tw1 qfn32samples_clock1_map.ncd qfn32samples_clock1.prf
Design file: qfn32samples_clock1_map.ncd
Preference file: qfn32samples_clock1.prf
Device,speed: LCMXO2-256HC,4
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "sub_sec_0" 84.753000 MHz (368 errors)
1741 items scored, 368 timing errors detected.
Warning: 9.189MHz is the maximum frequency for this preference.
FREQUENCY NET "CLK_c" 132.066000 MHz (116 errors)
444 items scored, 116 timing errors detected.
Warning: 108.401MHz is the maximum frequency for this preference.
FREQUENCY NET "BTN_DN_c" 399.840000 MHz (0 errors) 1 item scored, 0 timing errors detected.
Report: 400.000MHz is the maximum frequency for this preference.
FREQUENCY NET "BTN_UP_c" 399.840000 MHz (0 errors) 0 items scored, 0 timing errors detected.
Report: 400.000MHz is the maximum frequency for this preference.
FREQUENCY NET "btn_up_impl/n1523" 399.840000 MHz (0 errors) 1 item scored, 0 timing errors detected.
Report: 400.000MHz is the maximum frequency for this preference.
Report Type: based on TRACE automatically generated preferences
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "sub_sec_0" 84.753000 MHz ;
1741 items scored, 368 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 3.635ns (weighted slack = -97.026ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sec_impl/sub_sec_484__i7 (from CLK_c -)
Destination: FF Data in sec_impl/sec_up_i_77 (to sub_sec_0 +)
Delay: 3.911ns (36.9% logic, 63.1% route), 3 logic levels.
Constraint Details:
3.911ns physical path delay sec_impl/SLICE_2 to SLICE_49 exceeds
(delay constraint based on source clock period of 7.571ns and destination clock period of 11.798ns)
0.442ns delay constraint less
0.166ns DIN_SET requirement (totaling 0.276ns) by 3.635ns
Physical Path Details:
Data path sec_impl/SLICE_2 to SLICE_49:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 *l/SLICE_2.CLK to *pl/SLICE_2.Q0 sec_impl/SLICE_2 (from CLK_c)
ROUTE 4 e 1.234 *pl/SLICE_2.Q0 to SLICE_47.D0 sub_sec_7
CTOF_DEL --- 0.495 SLICE_47.D0 to SLICE_47.F0 SLICE_47
ROUTE 1 e 1.234 SLICE_47.F0 to SLICE_49.B0 n4479
CTOF_DEL --- 0.495 SLICE_49.B0 to SLICE_49.F0 SLICE_49
ROUTE 1 e 0.001 SLICE_49.F0 to SLICE_49.DI0 n4218 (to sub_sec_0)
--------
3.911 (36.9% logic, 63.1% route), 3 logic levels.
Warning: 9.189MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "CLK_c" 132.066000 MHz ;
444 items scored, 116 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 1.654ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q pre_scaler_485__i3 (from CLK_c -)
Destination: FF Data in sec_impl/sub_sec_484__i7 (to CLK_c -)
Delay: 9.059ns (48.5% logic, 51.5% route), 10 logic levels.
Constraint Details:
9.059ns physical path delay SLICE_10 to sec_impl/SLICE_2 exceeds
7.571ns delay constraint less
0.166ns DIN_SET requirement (totaling 7.405ns) by 1.654ns
Physical Path Details:
Data path SLICE_10 to sec_impl/SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from CLK_c)
ROUTE 2 e 1.234 SLICE_10.Q0 to SLICE_99.C0 pre_scaler_3
CTOF_DEL --- 0.495 SLICE_99.C0 to SLICE_99.F0 SLICE_99
ROUTE 1 e 0.480 SLICE_99.F0 to SLICE_99.D1 n4283
CTOF_DEL --- 0.495 SLICE_99.D1 to SLICE_99.F1 SLICE_99
ROUTE 1 e 1.234 SLICE_99.F1 to SLICE_98.D1 n4284
CTOF_DEL --- 0.495 SLICE_98.D1 to SLICE_98.F1 SLICE_98
ROUTE 1 e 0.480 SLICE_98.F1 to SLICE_98.C0 n4285
CTOF_DEL --- 0.495 SLICE_98.C0 to SLICE_98.F0 SLICE_98
ROUTE 2 e 1.234 SLICE_98.F0 to *pl/SLICE_6.B1 n8
C1TOFCO_DE --- 0.889 *pl/SLICE_6.B1 to *l/SLICE_6.FCO sec_impl/SLICE_6
ROUTE 1 e 0.001 *l/SLICE_6.FCO to SLICE_5.FCI sec_impl/n3709
FCITOFCO_D --- 0.162 SLICE_5.FCI to SLICE_5.FCO SLICE_5
ROUTE 1 e 0.001 SLICE_5.FCO to *l/SLICE_4.FCI sec_impl/n3710
FCITOFCO_D --- 0.162 *l/SLICE_4.FCI to *l/SLICE_4.FCO sec_impl/SLICE_4
ROUTE 1 e 0.001 *l/SLICE_4.FCO to *l/SLICE_3.FCI sec_impl/n3711
FCITOFCO_D --- 0.162 *l/SLICE_3.FCI to *l/SLICE_3.FCO sec_impl/SLICE_3
ROUTE 1 e 0.001 *l/SLICE_3.FCO to *l/SLICE_2.FCI sec_impl/n3712
FCITOF0_DE --- 0.585 *l/SLICE_2.FCI to *pl/SLICE_2.F0 sec_impl/SLICE_2
ROUTE 1 e 0.001 *pl/SLICE_2.F0 to *l/SLICE_2.DI0 sec_impl/n39 (to CLK_c)
--------
9.059 (48.5% logic, 51.5% route), 10 logic levels.
Warning: 108.401MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "BTN_DN_c" 399.840000 MHz ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.001ns
The internal maximum frequency of the following component is 400.000 MHz
Logical Details: Cell type Pin name Component name
Destination: SLICE CLK SLICE_16
Delay: 2.500ns -- based on Minimum Pulse Width
Passed: The following path meets requirements by 0.082ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q btn_dn_impl/btn_dn_ack_82 (from sub_sec_0 +)
Destination: FF Data in btn_dn_impl/i1091 (to btn_dn_impl/n1400 +)
Delay: 1.686ns (26.8% logic, 73.2% route), 1 logic levels.
Constraint Details:
1.686ns physical path delay btn_dn_impl/SLICE_15 to SLICE_126 meets
(delay constraint based on source clock period of 11.798ns and destination clock period of 2.501ns)
2.501ns delay constraint less
0.733ns LSRREC_SET requirement (totaling 1.768ns) by 0.082ns
Physical Path Details:
Data path btn_dn_impl/SLICE_15 to SLICE_126:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 */SLICE_15.CLK to *l/SLICE_15.Q0 btn_dn_impl/SLICE_15 (from sub_sec_0)
ROUTE 7 e 1.234 *l/SLICE_15.Q0 to SLICE_126.LSR btn_dn_ack (to btn_dn_impl/n1400)
--------
1.686 (26.8% logic, 73.2% route), 1 logic levels.
Report: 400.000MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "BTN_UP_c" 399.840000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.001ns
The internal maximum frequency of the following component is 400.000 MHz
Logical Details: Cell type Pin name Component name
Destination: SLICE CLK SLICE_104
Delay: 2.500ns -- based on Minimum Pulse Width
Report: 400.000MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "btn_up_impl/n1523" 399.840000 MHz ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.001ns
The internal maximum frequency of the following component is 400.000 MHz
Logical Details: Cell type Pin name Component name
Destination: SLICE CLK SLICE_109
Delay: 2.500ns -- based on Minimum Pulse Width
Passed: The following path meets requirements by 0.082ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q btn_up_impl/btn_up_ack_79 (from sub_sec_0 +)
Destination: FF Data in btn_up_impl/i1083 (to btn_up_impl/n1523 +)
Delay: 1.686ns (26.8% logic, 73.2% route), 1 logic levels.
Constraint Details:
1.686ns physical path delay btn_up_impl/SLICE_23 to SLICE_109 meets
(delay constraint based on source clock period of 11.798ns and destination clock period of 2.501ns)
2.501ns delay constraint less
0.733ns LSRREC_SET requirement (totaling 1.768ns) by 0.082ns
Physical Path Details:
Data path btn_up_impl/SLICE_23 to SLICE_109:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 */SLICE_23.CLK to *l/SLICE_23.Q0 btn_up_impl/SLICE_23 (from sub_sec_0)
ROUTE 8 e 1.234 *l/SLICE_23.Q0 to SLICE_109.LSR btn_up_ack (to btn_up_impl/n1523)
--------
1.686 (26.8% logic, 73.2% route), 1 logic levels.
Report: 400.000MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "sub_sec_0" 84.753000 MHz | | |
; | 84.753 MHz| 9.189 MHz| 3 *
| | |
FREQUENCY NET "CLK_c" 132.066000 MHz ; | 132.066 MHz| 108.401 MHz| 10 *
| | |
FREQUENCY NET "BTN_DN_c" 399.840000 MHz | | |
; | 399.840 MHz| 400.000 MHz| 1
| | |
FREQUENCY NET "BTN_UP_c" 399.840000 MHz | | |
; | 399.840 MHz| 400.000 MHz| 0
| | |
FREQUENCY NET "btn_up_impl/n1523" | | |
399.840000 MHz ; | 399.840 MHz| 400.000 MHz| 1
| | |
----------------------------------------------------------------------------
2 preferences(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
n4284 | 1| 116| 23.97%
| | |
n8 | 2| 116| 23.97%
| | |
n4285 | 1| 116| 23.97%
| | |
set_mode_1 | 14| 106| 21.90%
| | |
set_mode_0 | 14| 106| 21.90%
| | |
n4489 | 16| 98| 20.25%
| | |
min_up | 9| 81| 16.74%
| | |
n102 | 2| 76| 15.70%
| | |
n4283 | 1| 68| 14.05%
| | |
hour_impl/n936 | 2| 64| 13.22%
| | |
alarm_mode | 41| 64| 13.22%
| | |
n4485 | 9| 63| 13.02%
| | |
n137 | 14| 60| 12.40%
| | |
btn_up_ack | 8| 59| 12.19%
| | |
min_impl/n28 | 18| 58| 11.98%
| | |
hour_impl/n1526 | 1| 56| 11.57%
| | |
hour_impl/n928 | 2| 56| 11.57%
| | |
sec_impl/n3709 | 1| 49| 10.12%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 8 clocks:
Clock Domain: sub_sec_0 Source: sec_impl/SLICE_6.Q1 Loads: 46
Covered under: FREQUENCY NET "sub_sec_0" 84.753000 MHz ;
Data transfers from:
Clock Domain: CLK_c Source: CLK.PAD
Covered under: FREQUENCY NET "sub_sec_0" 84.753000 MHz ; Transfers: 8
Clock Domain: btn_sel_impl/n1398 Source: SLICE_48.F1
Covered under: FREQUENCY NET "sub_sec_0" 84.753000 MHz ; Transfers: 1
Clock Domain: btn_dn_impl/n1400 Source: SLICE_126.F0
Covered under: FREQUENCY NET "sub_sec_0" 84.753000 MHz ; Transfers: 1
Clock Domain: btn_up_impl/n1523 Source: SLICE_47.F1
Covered under: FREQUENCY NET "sub_sec_0" 84.753000 MHz ; Transfers: 1
Clock Domain: CLK_c Source: CLK.PAD Loads: 14
Covered under: FREQUENCY NET "CLK_c" 132.066000 MHz ;
Clock Domain: BTN_DN_c Source: BTN_DN.PAD Loads: 4
No transfer within this clock domain is found
Clock Domain: BTN_UP_c Source: BTN_UP.PAD Loads: 4
No transfer within this clock domain is found
Clock Domain: BTN_SEL_c Source: BTN_SEL.PAD Loads: 4
No transfer within this clock domain is found
Clock Domain: btn_sel_impl/n1398 Source: SLICE_48.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: btn_dn_impl/n1400 Source: SLICE_126.F0 Loads: 2
No transfer within this clock domain is found
Data transfers from:
Clock Domain: sub_sec_0 Source: sec_impl/SLICE_6.Q1
Covered under: FREQUENCY NET "BTN_DN_c" 399.840000 MHz ; Transfers: 1
Clock Domain: btn_up_impl/n1523 Source: SLICE_47.F1 Loads: 2
No transfer within this clock domain is found
Data transfers from:
Clock Domain: sub_sec_0 Source: sec_impl/SLICE_6.Q1
Covered under: FREQUENCY NET "btn_up_impl/n1523" 399.840000 MHz ; Transfers: 1
Timing summary (Setup):
---------------
Timing errors: 484 Score: 2303391
Cumulative negative slack: 1536837
Constraints cover 2190 paths, 21 nets, and 791 connections (77.6% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond_1.4_Production (87)
Fri Jun 15 15:12:26 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o qfn32samples_clock1.tw1 qfn32samples_clock1_map.ncd qfn32samples_clock1.prf
Design file: qfn32samples_clock1_map.ncd
Preference file: qfn32samples_clock1.prf
Device,speed: LCMXO2-256HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "sub_sec_0" 84.753000 MHz (0 errors) 1741 items scored, 0 timing errors detected.
FREQUENCY NET "CLK_c" 132.066000 MHz (0 errors) 444 items scored, 0 timing errors detected.
FREQUENCY NET "BTN_DN_c" 399.840000 MHz (0 errors) 1 item scored, 0 timing errors detected.
FREQUENCY NET "BTN_UP_c" 399.840000 MHz (0 errors) 0 items scored, 0 timing errors detected.
FREQUENCY NET "btn_up_impl/n1523" 399.840000 MHz (0 errors) 1 item scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "sub_sec_0" 84.753000 MHz ;
1741 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.443ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q min_impl/alarm_mode_81 (from sub_sec_0 +)
Destination: FF Data in min_impl/alarm_mode_81 (to sub_sec_0 +)
Delay: 0.430ns (53.5% logic, 46.5% route), 2 logic levels.
Constraint Details:
0.430ns physical path delay SLICE_14 to SLICE_14 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.443ns
Physical Path Details:
Data path SLICE_14 to SLICE_14:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 SLICE_14.CLK to SLICE_14.Q0 SLICE_14 (from sub_sec_0)
ROUTE 41 e 0.199 SLICE_14.Q0 to SLICE_14.A0 alarm_mode
CTOF_DEL --- 0.099 SLICE_14.A0 to SLICE_14.F0 SLICE_14
ROUTE 3 e 0.001 SLICE_14.F0 to SLICE_14.DI0 n277 (to sub_sec_0)
--------
0.430 (53.5% logic, 46.5% route), 2 logic levels.
================================================================================
Preference: FREQUENCY NET "CLK_c" 132.066000 MHz ;
444 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.443ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q pre_scaler_485__i14 (from CLK_c -)
Destination: FF Data in pre_scaler_485__i14 (to CLK_c -)
Delay: 0.430ns (53.5% logic, 46.5% route), 2 logic levels.
Constraint Details:
0.430ns physical path delay SLICE_0 to SLICE_0 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.443ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 SLICE_0.CLK to SLICE_0.Q1 SLICE_0 (from CLK_c)
ROUTE 2 e 0.199 SLICE_0.Q1 to SLICE_0.A1 pre_scaler_14
CTOF_DEL --- 0.099 SLICE_0.A1 to SLICE_0.F1 SLICE_0
ROUTE 1 e 0.001 SLICE_0.F1 to SLICE_0.DI1 n72 (to CLK_c)
--------
0.430 (53.5% logic, 46.5% route), 2 logic levels.
================================================================================
Preference: FREQUENCY NET "BTN_DN_c" 399.840000 MHz ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.646ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q btn_dn_impl/btn_dn_ack_82 (from sub_sec_0 +)
Destination: FF Data in btn_dn_impl/i1091 (to btn_dn_impl/n1400 +)
Delay: 0.646ns (20.3% logic, 79.7% route), 1 logic levels.
Constraint Details:
0.646ns physical path delay btn_dn_impl/SLICE_15 to SLICE_126 meets
(delay constraint based on source clock period of 11.798ns and destination clock period of 2.501ns)
0.000ns LSRREC_HLD and
0.000ns delay constraint requirement (totaling 0.000ns) by 0.646ns
Physical Path Details:
Data path btn_dn_impl/SLICE_15 to SLICE_126:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 */SLICE_15.CLK to *l/SLICE_15.Q0 btn_dn_impl/SLICE_15 (from sub_sec_0)
ROUTE 7 e 0.515 *l/SLICE_15.Q0 to SLICE_126.LSR btn_dn_ack (to btn_dn_impl/n1400)
--------
0.646 (20.3% logic, 79.7% route), 1 logic levels.
================================================================================
Preference: FREQUENCY NET "BTN_UP_c" 399.840000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "btn_up_impl/n1523" 399.840000 MHz ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.646ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q btn_up_impl/btn_up_ack_79 (from sub_sec_0 +)
Destination: FF Data in btn_up_impl/i1083 (to btn_up_impl/n1523 +)
Delay: 0.646ns (20.3% logic, 79.7% route), 1 logic levels.
Constraint Details:
0.646ns physical path delay btn_up_impl/SLICE_23 to SLICE_109 meets
(delay constraint based on source clock period of 11.798ns and destination clock period of 2.501ns)
0.000ns LSRREC_HLD and
0.000ns delay constraint requirement (totaling 0.000ns) by 0.646ns
Physical Path Details:
Data path btn_up_impl/SLICE_23 to SLICE_109:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 */SLICE_23.CLK to *l/SLICE_23.Q0 btn_up_impl/SLICE_23 (from sub_sec_0)
ROUTE 8 e 0.515 *l/SLICE_23.Q0 to SLICE_109.LSR btn_up_ack (to btn_up_impl/n1523)
--------
0.646 (20.3% logic, 79.7% route), 1 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "sub_sec_0" 84.753000 MHz | | |
; | -| -| 2
| | |
FREQUENCY NET "CLK_c" 132.066000 MHz ; | -| -| 2
| | |
FREQUENCY NET "BTN_DN_c" 399.840000 MHz | | |
; | -| -| 1
| | |
FREQUENCY NET "BTN_UP_c" 399.840000 MHz | | |
; | -| -| 0
| | |
FREQUENCY NET "btn_up_impl/n1523" | | |
399.840000 MHz ; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 8 clocks:
Clock Domain: sub_sec_0 Source: sec_impl/SLICE_6.Q1 Loads: 46
Covered under: FREQUENCY NET "sub_sec_0" 84.753000 MHz ;
Data transfers from:
Clock Domain: CLK_c Source: CLK.PAD
Covered under: FREQUENCY NET "sub_sec_0" 84.753000 MHz ; Transfers: 8
Clock Domain: btn_sel_impl/n1398 Source: SLICE_48.F1
Covered under: FREQUENCY NET "sub_sec_0" 84.753000 MHz ; Transfers: 1
Clock Domain: btn_dn_impl/n1400 Source: SLICE_126.F0
Covered under: FREQUENCY NET "sub_sec_0" 84.753000 MHz ; Transfers: 1
Clock Domain: btn_up_impl/n1523 Source: SLICE_47.F1
Covered under: FREQUENCY NET "sub_sec_0" 84.753000 MHz ; Transfers: 1
Clock Domain: CLK_c Source: CLK.PAD Loads: 14
Covered under: FREQUENCY NET "CLK_c" 132.066000 MHz ;
Clock Domain: BTN_DN_c Source: BTN_DN.PAD Loads: 4
No transfer within this clock domain is found
Clock Domain: BTN_UP_c Source: BTN_UP.PAD Loads: 4
No transfer within this clock domain is found
Clock Domain: BTN_SEL_c Source: BTN_SEL.PAD Loads: 4
No transfer within this clock domain is found
Clock Domain: btn_sel_impl/n1398 Source: SLICE_48.F1 Loads: 2
No transfer within this clock domain is found
Clock Domain: btn_dn_impl/n1400 Source: SLICE_126.F0 Loads: 2
No transfer within this clock domain is found
Data transfers from:
Clock Domain: sub_sec_0 Source: sec_impl/SLICE_6.Q1
Covered under: FREQUENCY NET "BTN_DN_c" 399.840000 MHz ; Transfers: 1
Clock Domain: btn_up_impl/n1523 Source: SLICE_47.F1 Loads: 2
No transfer within this clock domain is found
Data transfers from:
Clock Domain: sub_sec_0 Source: sec_impl/SLICE_6.Q1
Covered under: FREQUENCY NET "btn_up_impl/n1523" 399.840000 MHz ; Transfers: 1
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 2190 paths, 21 nets, and 793 connections (77.8% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 484 (setup), 0 (hold)
Score: 2303391 (setup), 0 (hold)
Cumulative negative slack: 1536837 (1536837+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------