PAR: Place And Route Diamond_1.4_Production (87). Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Mon Jun 18 08:49:03 2012 Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_mcpu.p2t qfn32samples_mcpu_map.ncd qfn32samples_mcpu.dir qfn32samples_mcpu.prf Preference file: qfn32samples_mcpu.prf. Cost Table Summary Level/ Number Timing Run NCD Cost [ncd] Unrouted Score Time Status ---------- -------- -------- ----- ------------ 5_1 * 0 0 46 Complete * : Design saved. par done! Lattice Place and Route Report for Design "qfn32samples_mcpu_map.ncd" Mon Jun 18 08:49:03 2012 Best Par Run PAR: Place And Route Diamond_1.4_Production (87). Command Line: Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_mcpu.p2t qfn32samples_mcpu_map.ncd qfn32samples_mcpu.dir qfn32samples_mcpu.prf Preference file: qfn32samples_mcpu.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file qfn32samples_mcpu_map.ncd. Design name: mcpu NCD version: 3.2 Vendor: LATTICE Device: LCMXO2-256HC Package: QFN32 Performance: 4 Loading device for application par from file 'xo2c256.nph' in environment: Y:/Program_Files/lscc/diamond/1.4/ispfpga. Package Status: Advanced Version 1.34 Performance Hardware Data Status: Final) Version 22.4 License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 3/56 5% used 3/22 13% bonded SLICE 57/128 44% used GSR 1/1 100% used Number of Signals: 178 Number of Connections: 577 Pin Constraint Summary: 0 out of 3 pins locked (0% locked). No signal is selected as primary clock. No signal is selected as secondary clock. Signal RST_c is selected as Global Set/Reset. . Starting Placer Phase 0. ....... Finished Placer Phase 0. REAL time: 18 secs Starting Placer Phase 1. ................... Placer score = 14773. Finished Placer Phase 1. REAL time: 35 secs Starting Placer Phase 2. . Placer score = 14446 Finished Placer Phase 2. REAL time: 35 secs Clock Report Global Clock Resources: CLK_PIN : 0 out of 8 (0%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY : 0 out of 8 (0%) SECONDARY: 0 out of 8 (0%) I/O Usage Summary (final): 3 out of 56 (5.4%) PIO sites used. 3 out of 22 (13.6%) bonded PIO sites used. Number of PIO comps: 3; differential: 0 Number of Vref pins used: 0 I/O Bank Usage Summary: +----------+--------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+--------------+------------+-----------+ | 0 | 0 / 9 ( 0%) | - | - | | 1 | 0 / 2 ( 0%) | - | - | | 2 | 3 / 9 ( 33%) | 2.5V | - | | 3 | 0 / 2 ( 0%) | - | - | +----------+--------------+------------+-----------+ Total placer CPU time: 16 secs Dumping design to file qfn32samples_mcpu.dir/5_1.ncd. 0 connections routed; 577 unrouted. Starting router resource preassignment WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. Signal=n141 loads=4 clock_loads=4 Signal=n5 loads=21 clock_loads=4 Signal=n137 loads=1 clock_loads=1 Signal=CLK_c loads=19 clock_loads=3 Completed router resource preassignment. Real time: 37 secs Starting iterative routing. For each routing iteration the number inside the parenthesis is the total time (in picoseconds) the design is failing the timing constraints. For each routing iteration the router will attempt to reduce this number until the number of routing iterations is completed or the value is 0 meaning the design has fully met the timing constraints. End of iteration 1 577 successful; 0 unrouted; (0) real time: 38 secs Dumping design to file qfn32samples_mcpu.dir/5_1.ncd. Total CPU time 17 secs Total REAL time: 38 secs Completely routed. End of route. 577 routed (100.00%); 0 unrouted. Checking DRC ... No errors found. 4 potential circuit loops found in timing analysis. Timing score: 0 Total REAL time to completion: 46 secs Dumping design to file qfn32samples_mcpu.dir/5_1.ncd. All signals are completely routed. par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.