PAR: Place And Route Diamond_1.4_Production (87).
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.
Mon Jun 18 11:48:57 2012

Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_test.p2t
qfn32samples_test_map.ncd qfn32samples_test.dir qfn32samples_test.prf

Preference file: qfn32samples_test.prf.

Cost Table Summary
Level/      Number      Timing      Run         NCD
Cost [ncd]  Unrouted    Score       Time        Status
----------  --------    --------    -----       ------------
5_1   *     0           0           56          Complete        


* : Design saved.

par done!

Lattice Place and Route Report for Design "qfn32samples_test_map.ncd"
Mon Jun 18 11:48:57 2012


Best Par Run
PAR: Place And Route Diamond_1.4_Production (87).
Command Line: Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f qfn32samples_test.p2t
qfn32samples_test_map.ncd qfn32samples_test.dir qfn32samples_test.prf
Preference file: qfn32samples_test.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file qfn32samples_test_map.ncd.
Design name: ADC_top
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-256HC
Package:     QFN32
Performance: 4
Loading device for application par from file 'xo2c256.nph' in environment: Y:/Program_Files/lscc/diamond/1.4/ispfpga.
Package Status:                     Advanced       Version 1.34
Performance Hardware Data Status:   Final)         Version 22.4
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)      13/56           23% used
                     13/22           59% bonded
   IOLOGIC           10/56           17% used

   SLICE             29/128          22% used

   GSR                1/1           100% used


Number of Signals: 126
Number of Connections: 264

Pin Constraint Summary:
   0 out of 13 pins locked (0% locked).

The following 1 signal is selected to use the primary clock routing resources:
    clk_in_c (driver: clk_in, clk load #: 39)


No signal is selected as secondary clock.

Signal rstn_c is selected as Global Set/Reset.
.
Starting Placer Phase 0.
...........
Finished Placer Phase 0.  REAL time: 16 secs 

Starting Placer Phase 1.
..................
Placer score = 5890.
Finished Placer Phase 1.  REAL time: 48 secs 

Starting Placer Phase 2.
.
Placer score =  5890
Finished Placer Phase 2.  REAL time: 48 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 1 out of 8 (12%)
  DCM        : 0 out of 2 (0%)
  DCC        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "clk_in_c" from comp "clk_in" on CLK_PIN site "13 (PB4C)", clk load = 39

  PRIMARY  : 1 out of 8 (12%)
  SECONDARY: 0 out of 8 (0%)




I/O Usage Summary (final):
   13 out of 56 (23.2%) PIO sites used.
   13 out of 22 (59.1%) bonded PIO sites used.
   Number of PIO comps: 13; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
+----------+--------------+------------+-----------+
| I/O Bank | Usage        | Bank Vccio | Bank Vref |
+----------+--------------+------------+-----------+
| 0        | 5 / 9 ( 55%) | 2.5V       | -         |
| 1        | 2 / 2 (100%) | 2.5V       | -         |
| 2        | 5 / 9 ( 55%) | 2.5V       | -         |
| 3        | 1 / 2 ( 50%) | 2.5V       | -         |
+----------+--------------+------------+-----------+

Total placer CPU time: 29 secs 

Dumping design to file qfn32samples_test.dir/5_1.ncd.

0 connections routed; 264 unrouted.
Starting router resource preassignment

Completed router resource preassignment. Real time: 50 secs 
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
264 successful; 0 unrouted; (0) real time: 50 secs 
Dumping design to file qfn32samples_test.dir/5_1.ncd.
Total CPU time 29 secs 
Total REAL time: 50 secs 
Completely routed.
End of route.  264 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.

Timing score: 0 

Total REAL time to completion: 56 secs 

Dumping design to file qfn32samples_test.dir/5_1.ncd.


All signals are completely routed.


par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.