Lattice Mapping Report File for Design Module 'tool_test'


Design Information

Command line:   map -a MachXO2 -p LCMXO2-256HC -t QFN32 -s 4 -oc Commercial
     qfn32samples_jtag_comm.ngd -o qfn32samples_jtag_comm_map.ncd -pr
     qfn32samples_jtag_comm.prf -mp qfn32samples_jtag_comm.mrp
     Z:/XC2C/xo2qfn/src/jtag_comm.lpf -c 0
Target Vendor:  LATTICE
Target Device:  LCMXO2-256HCQFN32
Target Performance:   4
Mapper:  xo2c00,  version:  Diamond_1.4_Production (87)
Mapped on:  06/18/12  11:34:30


Design Summary
   Number of registers:    38
      PFU registers:    38
      PIO registers:    0
   Number of SLICEs:            26 out of   128 (20%)
      SLICEs(logic/ROM):        26 out of    32 (81%)
      SLICEs(logic/ROM/RAM):     0 out of    96 (0%)
          As RAM:            0 out of    96 (0%)
          As Logic/ROM:      0 out of    96 (0%)
   Number of logic LUT4s:      39
   Number of distributed RAM:   0 (0 LUT4s)
   Number of ripple logic:      0 (0 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:      39
   Number of PIO sites used: 8 out of 22 (36%)
   Number of block RAMs:  0 out of 0
   Number of GSRs:  1 out of 1 (100%)
   EFB used :       Yes
   JTAG used :      Yes
   Readback used :  No
   Oscillator used :  Yes
   Startup used :   No
   POR :            On
   Bandgap :        On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  1 out of 2 (50%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  2
     Net CLK: 27 loads, 16 rising, 11 falling (Driver: clk_selector )
     Net i2c1_scli: 1 loads, 1 rising, 0 falling (Driver: PIO SCL )
   Number of Clock Enables:  12
     Net n221: 4 loads, 4 LSLICEs
     Net n368: 1 loads, 1 LSLICEs
     Net n19: 1 loads, 1 LSLICEs
     Net n365: 1 loads, 1 LSLICEs
     Net n755: 1 loads, 1 LSLICEs
     Net n370: 1 loads, 1 LSLICEs

     Net n757: 1 loads, 1 LSLICEs
     Net n1_adj_1: 1 loads, 1 LSLICEs
     Net JTAG_SPI/n6: 1 loads, 1 LSLICEs
     Net JTAG_SPI/n9: 1 loads, 1 LSLICEs
     Net JTAG_SPI/n231: 4 loads, 4 LSLICEs
     Net n233: 1 loads, 1 LSLICEs
   Number of local set/reset loads for net RESET merged into GSR:  1
   Number of LSRs:  4
     Net n719: 1 loads, 1 LSLICEs
     Net r_cs1: 5 loads, 5 LSLICEs
     Net n344: 1 loads, 1 LSLICEs
     Net n220: 2 loads, 2 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net r_jtck: 10 loads
     Net JTAG_SPI/r_sck: 8 loads
     Net r_cs1: 8 loads
     Net wb_stat_0: 8 loads
     Net wb_stat_1: 8 loads
     Net SPI_DATA_REQ: 6 loads
     Net reset_cnt_0: 5 loads
     Net n221: 4 loads
     Net RESET: 4 loads
     Net reset_cnt_1: 4 loads




   Number of warnings:  2
   Number of errors:    0




Design Errors/Warnings

WARNING: OSCH 'osc_internal' has mismatching FREQUENCY preference value of 2.08
     MHz and NOM_FREQ value of 24.18 MHz.
WARNING: Using local reset signal 'RESET' to infer global GSR net.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| EXTOSC_EN           | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| SDA                 | BIDIR     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| SCL                 | BIDIR     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| TOP_TDO             | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| TOP_TDI             | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| TOP_TCK             | INPUT     | LVCMOS25  |            |

+---------------------+-----------+-----------+------------+
| TOP_TMS             | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| EXTOSC              | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+



Removed logic

Signal n4 was merged into signal CLK
Signal VCC_net undriven or does not drive anything - clipped.
Signal efb_impl/VCC_net undriven or does not drive anything - clipped.
Block JTAG_SPI/i4 was optimized away.
Block i709 was optimized away.
Block efb_impl/i1 was optimized away.



Memory Usage


OSC Summary
-----------

OSC 1:                                     Pin/Node Value
  OSC Instance Name:                                osc_internal
  OSC Type:                                         OSCH
  STDBY Input:                                      NONE
  OSC Output:                              NODE     CLK_INT
  OSC Nominal Frequency (MHz):                      24.18

DCMA Summary
------------

DCMA 1:                                     Pin/Node Value
  DCMA Instance Name:                                clk_selector
  DCMA Type:                                         DCMA
  CLK0 Input:                              NODE     CLK_INT
  CLK1 Input:                              PIN      EXTOSC_c
  SEL Input:                                        NONE
  DCMOUT Output:                           NODE     CLK

Embedded Functional Block Connection Summary:
---------------------------------------------

   Desired WISHBONE clock frequency: 50.0 MHz
   Clock source:                     CLK
   Reset source:                     NONE
   Functions mode:
      I2C #1 (Primary) Function:     ENABLED
      I2C #2 (Secondary) Function:   DISABLED
      SPI Function:                  DISABLED
      Timer/Counter Function:        ENABLED
      Timer/Counter Mode:            WB
      UFM Connection:                DISABLED
      PLL0 Connection:               DISABLED

      PLL1 Connection:               DISABLED
   I2C Function Summary:
   --------------------
      I2C Component:          PRIMARY
      I2C Addressing:         7BIT
      I2C Performance:        400kHz
      Slave Address:          0b1010001
      General Call:           DISABLED
      I2C Wake Up:            DISABLED
      I2C Component:          UFM/Configuration
      I2C Addressing:         7BIT
      I2C Performance:        400kHz
      Slave Address:          0b1010000
   SPI Function Summary:
   --------------------
      None
   Timer/Counter Function Summary:
   ------------------------------
      TC_MODE:                CTCM
      TC_SCLK_SEL:            Positive Edge
      TC_CCLK_SEL:            1
      GSR:                    ENABLED
      TC_TOP_SET:             65535
      TC_OCR_SET:             32767
      TC_OC_MODE:             TOGGLE
      TC_RESETN:              DISABLED
      TC_TOP_SEL:             ON
      TC_OV_INT:              OFF
      TC_OCR_INT:             OFF
      TC_ICR_INT:             OFF
      TC_OVERFLOW:            DISABLED
      TC_ICAPTURE:            DISABLED
   UFM Function Summary:
   --------------------
      UFM Utilization:        General Purpose Flash Memory
      Available General
      Purpose Flash Memory:   0 Pages (0*128 Bits)

      EBR Blocks with Unique
      Initialization Data:    0

      WID		EBR Instance
      ---		------------



ASIC Components
---------------

Instance Name: bscan
         Type: JTAGF
Instance Name: efb_impl/EFBInst_0
         Type: EFB
Instance Name: osc_internal
         Type: OSCH
Instance Name: clk_selector
         Type: DCMA





GSR Usage
---------

GSR Component:
   The local reset signal 'RESET' of the design has been inferred as Global Set
        Reset (GSR). The reset signal used for GSR control is 'RESET'.

GSR Property:
   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.



Run Time and Memory Usage
-------------------------

   Total CPU Time: 1 secs
   Total REAL Time: 13 secs
   Peak Memory Usage: 25 MB












































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