Lattice Mapping Report File for Design Module 'clock'


Design Information

Command line:   map -a MachXO2 -p LCMXO2-256HC -t QFN32 -s 4 -oc Commercial
     qfn32samples_clock1.ngd -o qfn32samples_clock1_map.ncd -pr
     qfn32samples_clock1.prf -mp qfn32samples_clock1.mrp
     Z:/XC2C/qfn32samples-03/src/clock1.lpf -c 0
Target Vendor:  LATTICE
Target Device:  LCMXO2-256HCQFN32
Target Performance:   4
Mapper:  xo2c00,  version:  Diamond_1.4_Production (87)
Mapped on:  06/15/12  15:24:15


Design Summary
   Number of registers:    85
      PFU registers:    85
      PIO registers:    0
   Number of SLICEs:           122 out of   128 (95%)
      SLICEs(logic/ROM):        32 out of    32 (100%)
      SLICEs(logic/ROM/RAM):    90 out of    96 (94%)
          As RAM:            0 out of    96 (0%)
          As Logic/ROM:     90 out of    96 (94%)
   Number of logic LUT4s:     211
   Number of distributed RAM:   0 (0 LUT4s)
   Number of ripple logic:     14 (28 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:     239
   Number of PIO sites used: 17 out of 22 (77%)
   Number of block RAMs:  0 out of 0
   Number of GSRs:  1 out of 1 (100%)
   EFB used :       No
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   POR :            On
   Bandgap :        On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  8
     Net CLK_c: 14 loads, 0 rising, 14 falling (Driver: PIO CLK )
     Net BTN_DN_c: 1 loads, 1 rising, 0 falling (Driver: PIO BTN_DN )
     Net BTN_UP_c: 1 loads, 1 rising, 0 falling (Driver: PIO BTN_UP )
     Net BTN_SEL_c: 1 loads, 1 rising, 0 falling (Driver: PIO BTN_SEL )
     Net sub_sec_0: 43 loads, 6 rising, 37 falling (Driver:
     sec_impl/sub_sec_488__i0 )
     Net btn_sel_impl/n1402: 1 loads, 1 rising, 0 falling (Driver:
     btn_sel_impl/i2_4_lut )
     Net btn_dn_impl/n1404: 1 loads, 1 rising, 0 falling (Driver:

     btn_dn_impl/i1_4_lut )
     Net btn_up_impl/n1527: 1 loads, 1 rising, 0 falling (Driver:
     btn_up_impl/i1_4_lut )
   Number of Clock Enables:  6
     Net btn_sel_req: 2 loads, 2 LSLICEs
     Net sec_impl/sec_up_i: 4 loads, 4 LSLICEs
     Net n3_adj_117: 8 loads, 8 LSLICEs
     Net min_impl/n3_adj_16: 7 loads, 7 LSLICEs
     Net n3: 8 loads, 8 LSLICEs
     Net hour_impl/n3_adj_2: 8 loads, 8 LSLICEs
   Number of LSRs:  19
     Net BTN_DN_c: 2 loads, 2 LSLICEs
     Net BTN_UP_c: 2 loads, 2 LSLICEs
     Net BTN_SEL_c: 2 loads, 2 LSLICEs
     Net n4466: 9 loads, 9 LSLICEs
     Net n3341: 2 loads, 2 LSLICEs
     Net btn_up_ack: 1 loads, 1 LSLICEs
     Net sec_impl/sec_up_i: 1 loads, 1 LSLICEs
     Net sec_impl/n1592: 2 loads, 2 LSLICEs
     Net sec_impl/n1596: 2 loads, 2 LSLICEs
     Net btn_dn_ack: 1 loads, 1 LSLICEs
     Net btn_sel_impl/n1402: 1 loads, 1 LSLICEs
     Net btn_dn_impl/n1404: 1 loads, 1 LSLICEs
     Net min_impl/n1612: 2 loads, 2 LSLICEs
     Net min_impl/n1610: 2 loads, 2 LSLICEs
     Net min_impl/n1608: 2 loads, 2 LSLICEs
     Net min_impl/n1599: 1 loads, 1 LSLICEs
     Net btn_up_impl/n1527: 1 loads, 1 LSLICEs
     Net hour_impl/n1607: 3 loads, 3 LSLICEs
     Net hour_impl/n1605: 3 loads, 3 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net alarm_mode: 50 loads
     Net sub_sec_1: 30 loads
     Net n4468: 18 loads
     Net set_mode_0: 14 loads
     Net set_mode_1: 14 loads
     Net hour_impl/n1: 12 loads
     Net lower_a_0_adj_107: 12 loads
     Net hour_impl/n137: 11 loads
     Net lower_0_adj_99: 11 loads
     Net lower_a_1_adj_106: 11 loads




   Number of warnings:  8
   Number of errors:    0




Design Errors/Warnings

WARNING: logical net 'sec_impl/sub_sec_488_add_4_1/CI' has no driver
WARNING: logical net 'pre_scaler_489_add_4_1/CI' has no driver
WARNING: Register btn_sel_impl/r_btn_stat_set has a clock signal tied to GND.
WARNING: Register btn_sel_impl/prev_stat_set has a clock signal tied to GND.

WARNING: Register btn_dn_impl/prev_stat_set has a clock signal tied to GND.
WARNING: Register btn_dn_impl/r_btn_stat_set has a clock signal tied to GND.
WARNING: Register btn_up_impl/r_btn_stat_set has a clock signal tied to GND.
WARNING: Register btn_up_impl/prev_stat_set has a clock signal tied to GND.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| CLK                 | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| BTN_DN              | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| BTN_UP              | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| BTN_SEL             | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| DIG4                | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| DIG3                | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| DIG2                | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| DIG1                | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| CLK_1HZ             | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| G                   | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| F                   | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| D                   | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| C                   | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| B                   | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| A                   | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| CLK_OUT             | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| E                   | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+



Removed logic

Signal n25 was merged into signal sub_sec_0
Signal n4 was merged into signal CLK_c
Signal btn_up_impl/n4 was merged into signal BTN_UP_c
Signal btn_dn_impl/n4 was merged into signal BTN_DN_c
Signal n4457 was merged into signal btn_sel_impl/btn_sel_ack
Signal btn_sel_impl/n4 was merged into signal BTN_SEL_c

Signal sec_impl/n1593 was merged into signal sec_impl/sec_up_i
Signal VCC_net undriven or does not drive anything - clipped.
Signal pre_scaler_489_add_4_17/S1 undriven or does not drive anything - clipped.
Signal pre_scaler_489_add_4_17/CO undriven or does not drive anything - clipped.
Signal pre_scaler_489_add_4_1/S0 undriven or does not drive anything - clipped.
Signal pre_scaler_489_add_4_1/CI undriven or does not drive anything - clipped.
Signal sec_impl/sub_sec_488_add_4_1/S0 undriven or does not drive anything -
     clipped.
Signal sec_impl/sub_sec_488_add_4_1/CI undriven or does not drive anything -
     clipped.
Signal sec_impl/sub_sec_488_add_4_9/S1 undriven or does not drive anything -
     clipped.
Signal sec_impl/sub_sec_488_add_4_9/CO undriven or does not drive anything -
     clipped.
Block i812 was optimized away.
Block i4 was optimized away.
Block btn_up_impl/equal_34_i2 was optimized away.
Block btn_dn_impl/equal_34_i2 was optimized away.
Block btn_sel_impl/i32 was optimized away.
Block btn_sel_impl/equal_34_i2 was optimized away.
Block sec_impl/i1104 was optimized away.
Block i2 was optimized away.



Memory Usage




GSR Usage
---------

GSR Component:
   The Global Set Reset (GSR) resource has been used to implement a global reset
        of the design. The reset signal used for GSR control is
        'btn_sel_impl/btn_sel_ack'.

GSR Property:
   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.

Components with disabled GSR Property
-------------------------------------

These components have the GSR property set to DISABLED. The components will not
     respond to the reset signal 'btn_sel_impl/btn_sel_ack' via the GSR
     component.

Type and number of components of the type:
   Register = 84

Type and instance name of component:
   Register : sub_sec_488__i2
   Register : pre_scaler_489__i15
   Register : pre_scaler_489__i14
   Register : pre_scaler_489__i0
   Register : pre_scaler_489__i13
   Register : pre_scaler_489__i12
   Register : pre_scaler_489__i11
   Register : pre_scaler_489__i10
   Register : pre_scaler_489__i9

   Register : pre_scaler_489__i8
   Register : pre_scaler_489__i7
   Register : pre_scaler_489__i6
   Register : pre_scaler_489__i5
   Register : pre_scaler_489__i4
   Register : pre_scaler_489__i3
   Register : pre_scaler_489__i2
   Register : pre_scaler_489__i1
   Register : set_mode_i0_i1
   Register : set_mode_i0_i0
   Register : sec_impl/sec_up_i_82
   Register : sec_impl/sub_sec_488__i7
   Register : sec_impl/sub_sec_488__i6
   Register : sec_impl/sub_sec_488__i5
   Register : sec_impl/sub_sec_488__i4
   Register : sec_impl/sub_sec_488__i3
   Register : sec_impl/sub_sec_488__i1
   Register : sec_impl/lower_491__i0
   Register : sec_impl/upper_490__i0
   Register : sec_impl/sub_sec_488__i0
   Register : sec_impl/upper_490__i1
   Register : sec_impl/upper_490__i2
   Register : sec_impl/upper_490__i3
   Register : sec_impl/r_ovr_77
   Register : sec_impl/lower_491__i1
   Register : sec_impl/lower_491__i2
   Register : sec_impl/lower_491__i3
   Register : btn_sel_impl/btn_sel_ack_83
   Register : btn_sel_impl/r_btn_stat_set
   Register : btn_sel_impl/prev_stat_set
   Register : btn_sel_impl/i1075
   Register : btn_dn_impl/prev_stat_set
   Register : btn_dn_impl/i1091
   Register : btn_dn_impl/i1095
   Register : btn_dn_impl/btn_dn_ack_81
   Register : btn_dn_impl/r_btn_stat_set
   Register : min_impl/lower_i0_i0
   Register : min_impl/upper_i0_i0
   Register : min_impl/alarm_mode_86
   Register : min_impl/upper_a_i0_i1
   Register : min_impl/upper_a_i0_i3
   Register : min_impl/lower_i0_i1
   Register : min_impl/r_ovr_77
   Register : min_impl/lower_i0_i2
   Register : min_impl/upper_i0_i1
   Register : min_impl/lower_a_i0_i0
   Register : min_impl/upper_i0_i3
   Register : min_impl/lower_a_i0_i3
   Register : min_impl/upper_i0_i2
   Register : min_impl/lower_i0_i3
   Register : min_impl/lower_a_i0_i1
   Register : min_impl/lower_a_i0_i2
   Register : min_impl/upper_a_i0_i2
   Register : min_impl/upper_a_i0_i0
   Register : btn_up_impl/btn_up_ack_84
   Register : btn_up_impl/i1083

   Register : btn_up_impl/i1087
   Register : btn_up_impl/r_btn_stat_set
   Register : btn_up_impl/prev_stat_set
   Register : hour_impl/lower_a_494__i3
   Register : hour_impl/lower_a_494__i2
   Register : hour_impl/lower_a_494__i1
   Register : hour_impl/lower_493__i3
   Register : hour_impl/lower_493__i2
   Register : hour_impl/lower_493__i1
   Register : hour_impl/upper_a_i0_i2
   Register : hour_impl/upper_a_i0_i3
   Register : hour_impl/upper_i0_i2
   Register : hour_impl/upper_i0_i3
   Register : hour_impl/upper_i0_i1
   Register : hour_impl/upper_a_i0_i1
   Register : hour_impl/lower_493__i0
   Register : hour_impl/upper_i0_i0
   Register : hour_impl/upper_a_i0_i0
   Register : hour_impl/lower_a_494__i0



Run Time and Memory Usage
-------------------------

   Total CPU Time: 2 secs
   Total REAL Time: 21 secs
   Peak Memory Usage: 26 MB

































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