Synthesis and Ngdbuild Report synthesis: version Diamond_1.4_Production (87) Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Sun Jun 17 09:16:45 2012 Command Line: synthesis -f qfn32samples_test_lattice.synproj -- all messages logged in file synthesis.log Synthesis Options INFO: Synthesis Options: (LSE-1022) INFO: -a option is = MachXO2 INFO: -s option is = 4 INFO: -t option is = QFN32 INFO: -d option is = LCMXO2-256HC INFO: Using package QFN32 INFO: Using performance grade 4 INFO: INFO: ########################################################## INFO: ### Lattice Family : MachXO2 INFO: ### Device : LCMXO2-256HC INFO: ### Package : QFN32 INFO: ### Speed : 4 INFO: ########################################################## INFO: INFO: Optimization Goal = Area INFO: -top option is not used WARNING: Ignoring Frequency option in Area Mode, Setting to default frequency of 1.0 MHz INFO: Target Frequency = 1.000000 MHz INFO: Max Fanout = 1000 INFO: Timing Path count = 3 INFO: bram Utilization = 100.000000 % INFO: dsp usage = TRUE (default) INFO: dsp utilization = 100 (default) INFO: fsm_encoding_style = auto INFO: Mux style = Auto INFO: Use Carry Chain = TRUE INFO: carry_chain_length = 0 INFO: Use IO Insertion = TRUE INFO: Use IO Reg = TRUE INFO: Resource Sharing = TRUE INFO: Propagate Constants = TRUE INFO: Remove Duplicate Registers = TRUE INFO: force_gsr = auto INFO: ROM style = auto INFO: RAM style = auto INFO: -comp option is FALSE INFO: -syn option is FALSE INFO: -p C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-04 (searchpath added) INFO: -p C:/lscc/diamond/1.4/ispfpga/xo2c00/data (searchpath added) INFO: -p C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-04/test (searchpath added) INFO: -p C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-04 (searchpath added) INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-04/src/EFB_tc_i2c.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-04/src/mcpu_efb.v INFO: Ngd file = qfn32samples_test.ngd INFO: -sdc option: sdc file input not used INFO: -lpf option: output file option is OFF INFO: hardtimer checking is enabled (default); -dt option not used INFO: -r option is OFF [ Remove LOC Properties is OFF ] -- Technology check ok...MachXO, MachXO2... INFO: The default vhdl library search path is now "c:/lscc/diamond/1.4/cae_library/vhdl_packages/vdbs" (VHDL-1504) INFO: ** Recompile design ** -- Technology check ok...MachXO, MachXO2... Compile Design INFO: Compile Design Begin c:/documents and settings/suz/my documents/lattice/xo2qfn-04/src/mcpu_efb.v(52): INFO: compiling module mcpu_efb (VERI-1018) c:/documents and settings/suz/my documents/lattice/xo2qfn-04/src/efb_tc_i2c.v(8): INFO: compiling module EFB_tc_i2c (VERI-1018) c:/documents and settings/suz/my documents/lattice/xo2qfn-04/src/mcpu_efb.v(162): INFO: compiling module sram (VERI-1018) c:/documents and settings/suz/my documents/lattice/xo2qfn-04/src/mcpu_efb.v(201): INFO: compiling module rom (VERI-1018) c:/documents and settings/suz/my documents/lattice/xo2qfn-04/src/mcpu_efb.v(211): WARNING: ram mem_original_ramnet has no write-port on it (VDB-1038) INFO: ######## Missing driver on net : \efb_impl/tc_ic, patching with GND... (LSE-1017) WARNING: No available RAMs found... (LSE-1105) WARNING: No available RAMs found... (LSE-1105) WARNING: Unsupported retiming instance (LSE-1120) WARNING: Unsupported retiming instance (LSE-1120) INFO: ######## Found 1 RAM Nets in design (LSE-1115) INFO: ######## Mapping RAM Net \sram_impl/mem to 2 Distributed blocks in SINGLE_PORT Mode WARNING: Skipping pad insertion on SCL due to black_box_pad_pin attribute (LSE-1155) WARNING: Skipping pad insertion on SDA due to black_box_pad_pin attribute (LSE-1155) INFO: Combinational loop found : 1 INFO: Net \equal_173/n5 INFO: Instance equal_173_i5 INFO: Net states[0] INFO: Instance mux_42_i1 INFO: Net n840 INFO: Instance i162 INFO: GSR Instance connected to net: RST_c (LSE-1148) WARNING: No lpf file will be written because -lpf option is not used or set to 0 INFO: Applying 1.000000 MHz constraint to all clocks (LSE-5000) INFO: Results of ngd drc checks are available in mcpu_efb_drc.log INFO: All blocks are expanded and NGD expansion is successful INFO: Writing ngd file qfn32samples_test.ngd ################### Begin Area Report (mcpu_efb)###################### Number of register bits => 32 of 1090 (2 % ) BB => 2 CCU2D => 5 EFB => 1 FD1P3AX => 8 FD1S1A => 9 FD1S1I => 6 FD1S3AX => 7 FD1S3IX => 1 FD1S3JX => 1 GSR => 1 IB => 2 INV => 4 L6MUX21 => 4 LUT4 => 67 OB => 1 PFUMX => 9 ROM64X1A => 2 SPR16X4C => 2 ################### End Area Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 6 Net : n5_adj_5, loads : 12 Net : CLK_3X_c, loads : 12 Net : n212, loads : 9 Net : master_clk, loads : 2 Net : GND_net, loads : 2 Net : n208, loads : 1 Clock Enable Nets Number of Clock Enables: 1 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : r_addr_3, loads : 21 Net : r_addr_1, loads : 21 Net : r_addr_2, loads : 18 Net : r_addr_0, loads : 17 Net : RST_c, loads : 12 Net : n105, loads : 12 Net : r_addr_4, loads : 12 Net : wb_stat_1, loads : 10 Net : adreg_5, loads : 9 Net : n1630, loads : 9 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 1000.000000 -name | | | clk4 [get_nets master_clk] | 1.000 MHz| 53.651 MHz| 10 | | | create_clock -period 1000.000000 -name | | | clk3 [get_nets n5_adj_5] | 1.000 MHz| 123.229 MHz| 5 | | | create_clock -period 1000.000000 -name | | | clk2 [get_nets n212] | 1.000 MHz| 161.917 MHz| 6 | | | create_clock -period 1000.000000 -name | | | clk1 [get_nets n208] | -| -| 0 | | | create_clock -period 1000.000000 -name | | | clk0 [get_nets CLK_3X_c] | 1.000 MHz| 248.942 MHz| 2 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 40.699 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 4.875 secs --------------------------------------------------------------