Lattice Mapping Report File for Design Module 'mcpu_efb'


Design Information

Command line:   map -a MachXO2 -p LCMXO2-256HC -t QFN32 -s 4 -oc Commercial
     qfn32samples_test.ngd -o qfn32samples_test_map.ncd -pr
     qfn32samples_test.prf -mp qfn32samples_test.mrp C:/Documents and
     Settings/suz/My Documents/lattice/xo2qfn-04/qfn32samples.lpf -c 0
Target Vendor:  LATTICE
Target Device:  LCMXO2-256HCQFN32
Target Performance:   4
Mapper:  xo2c00,  version:  Diamond_1.4_Production (87)
Mapped on:  06/17/12  09:16:52


Design Summary
   Number of registers:    32
      PFU registers:    32
      PIO registers:    0
   Number of SLICEs:            51 out of   128 (40%)
      SLICEs(logic/ROM):        32 out of    32 (100%)
      SLICEs(logic/ROM/RAM):    19 out of    96 (20%)
          As RAM:            6 out of    96 (6%)
          As Logic/ROM:     13 out of    96 (14%)
   Number of logic LUT4s:      77
   Number of distributed RAM:   6 (12 LUT4s)
   Number of ripple logic:      5 (10 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:      99
   Number of PIO sites used: 5 out of 22 (23%)
   Number of block RAMs:  0 out of 0
   Number of GSRs:  1 out of 1 (100%)
   EFB used :       Yes
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   POR :            On
   Bandgap :        On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  6
     Net CLK_3X_c: 8 loads, 8 rising, 0 falling (Driver: PIO CLK_3X )
     Net n208: 1 loads, 1 rising, 0 falling (Driver: rom_impl/i635_3_lut_4_lut )
     Net n5_adj_5: 4 loads, 4 rising, 0 falling (Driver: i972_2_lut )
     Net n212: 4 loads, 4 rising, 0 falling (Driver: i962_2_lut )
     Net master_clk: 4 loads, 1 rising, 3 falling (Driver: master_clk_104 )
     Net i2c1_scli: 1 loads, 1 rising, 0 falling (Driver: PIO SCL )
   Number of Clock Enables:  1
     Net wb_stat_1: 4 loads, 4 LSLICEs
   Number of local set/reset loads for net RST_c merged into GSR:  1

   Number of LSRs:  4
     Net n63: 2 loads, 2 LSLICEs
     Net n1630: 1 loads, 1 LSLICEs
     Net RST_c: 3 loads, 3 LSLICEs
     Net RST_NEG: 1 loads, 0 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net r_addr_1: 27 loads
     Net r_addr_3: 27 loads
     Net r_addr_2: 25 loads
     Net r_addr_4: 19 loads
     Net r_addr_0: 18 loads
     Net RST_c: 15 loads
     Net adreg_0: 12 loads
     Net adreg_2: 12 loads
     Net adreg_3: 12 loads
     Net n105: 12 loads




   Number of warnings:  1
   Number of errors:    0




Design Errors/Warnings

WARNING: logical net 'add_210_2/CI' has no driver



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| SDA                 | BIDIR     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| SCL                 | BIDIR     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| CLK_3X              | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| WE                  | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| RST                 | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+



Removed logic

Signal rom_impl/n4 was merged into signal master_clk
Signal GND_net undriven or does not drive anything - clipped.
Signal add_210_2/S0 undriven or does not drive anything - clipped.
Signal add_210_2/CI undriven or does not drive anything - clipped.
Signal add_210_cout/S1 undriven or does not drive anything - clipped.
Signal add_210_cout/CO undriven or does not drive anything - clipped.

Block rom_impl/i4 was optimized away.
Block i1 was optimized away.



Memory Usage

/sram_impl/mem0:
    EBRs: 0
    RAM SLICEs: 3
    Logic SLICEs: 0
    PFU Registers: 0
/sram_impl/mem1:
    EBRs: 0
    RAM SLICEs: 3
    Logic SLICEs: 0
    PFU Registers: 0

Embedded Functional Block Connection Summary:
---------------------------------------------

   Desired WISHBONE clock frequency: 50.0 MHz
   Clock source:                     CLK_3X_c
   Reset source:                     NONE
   Functions mode:
      I2C #1 (Primary) Function:     ENABLED
      I2C #2 (Secondary) Function:   DISABLED
      SPI Function:                  DISABLED
      Timer/Counter Function:        ENABLED
      Timer/Counter Mode:            WB
      UFM Connection:                DISABLED
      PLL0 Connection:               DISABLED
      PLL1 Connection:               DISABLED
   I2C Function Summary:
   --------------------
      I2C Component:          PRIMARY
      I2C Addressing:         7BIT
      I2C Performance:        400kHz
      Slave Address:          0b1010001
      General Call:           DISABLED
      I2C Wake Up:            DISABLED
      I2C Component:          UFM/Configuration
      I2C Addressing:         7BIT
      I2C Performance:        400kHz
      Slave Address:          0b1010000
   SPI Function Summary:
   --------------------
      None
   Timer/Counter Function Summary:
   ------------------------------
      TC_MODE:                CTCM
      TC_SCLK_SEL:            Positive Edge
      TC_CCLK_SEL:            1
      GSR:                    ENABLED
      TC_TOP_SET:             65535
      TC_OCR_SET:             32767

      TC_OC_MODE:             TOGGLE
      TC_RESETN:              ENABLED
      TC_TOP_SEL:             ON
      TC_OV_INT:              OFF
      TC_OCR_INT:             OFF
      TC_ICR_INT:             OFF
      TC_OVERFLOW:            DISABLED
      TC_ICAPTURE:            DISABLED
   UFM Function Summary:
   --------------------
      UFM Utilization:        General Purpose Flash Memory
      Available General
      Purpose Flash Memory:   0 Pages (0*128 Bits)

      EBR Blocks with Unique
      Initialization Data:    0

      WID		EBR Instance
      ---		------------



ASIC Components
---------------

Instance Name: efb_impl/EFBInst_0
         Type: EFB



GSR Usage
---------

GSR Component:
   The Global Set Reset (GSR) resource has been used to implement a global reset
        of the design. The reset signal used for GSR control is 'RST_c'.

GSR Property:
   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.

Components with disabled GSR Property
-------------------------------------

These components have the GSR property set to DISABLED. The components will not
     respond to the reset signal 'RST_c' via the GSR component.

Type and number of components of the type:
   Register = 17

Type and instance name of component:
   Register : wb_stat_i0
   Register : I_DATA_i0_i3
   Register : I_DATA_i0_i2
   Register : master_clk_104
   Register : I_DATA_i0_i6
   Register : I_DATA_i0_i1
   Register : I_DATA_i0_i5
   Register : rom_impl/r_addr_i1
   Register : rom_impl/r_addr_i6
   Register : rom_impl/r_addr_i5
   Register : rom_impl/r_addr_i4
   Register : rom_impl/r_addr_i3
   Register : rom_impl/r_addr_i2
   Register : wb_stat_i1

   Register : I_DATA_i0_i0
   Register : I_DATA_i0_i7
   Register : I_DATA_i0_i4

Components with synchronous local reset also reset by asynchronous GSR
----------------------------------------------------------------------

These components have the GSR property set to ENABLED and the local reset is
     synchronous. The components will respond to the synchronous local reset and
     to the unrelated asynchronous reset signal 'RST_c' via the GSR component.

Type and number of components of the type:
   Register = 6

Type and instance name of component:
   Register : akku_8
   Register : dlatchrs_121_i2
   Register : dlatchrs_121_i3
   Register : dlatchrs_121_i4
   Register : dlatchrs_121_i5
   Register : dlatchrs_121_i6



Run Time and Memory Usage
-------------------------

   Total CPU Time: 1 secs
   Total REAL Time: 0 secs
   Peak Memory Usage: 23 MB



































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