Lattice Mapping Report File for Design Module 'mcpu' Design Information Command line: map -a MachXO2 -p LCMXO2-256HC -t QFN32 -s 4 -oc Commercial qfn32samples_mcpu.ngd -o qfn32samples_mcpu_map.ncd -pr qfn32samples_mcpu.prf -mp qfn32samples_mcpu.mrp C:/Documents and Settings/suz/My Documents/lattice/xo2qfn-04/qfn32samples.lpf -c 0 Target Vendor: LATTICE Target Device: LCMXO2-256HCQFN32 Target Performance: 4 Mapper: xo2c00, version: Diamond_1.4_Production (87) Mapped on: 06/17/12 09:59:37 Design Summary Number of registers: 21 PFU registers: 21 PIO registers: 0 Number of SLICEs: 57 out of 128 (45%) SLICEs(logic/ROM): 32 out of 32 (100%) SLICEs(logic/ROM/RAM): 25 out of 96 (26%) As RAM: 24 out of 96 (25%) As Logic/ROM: 1 out of 96 (1%) Number of logic LUT4s: 55 Number of distributed RAM: 24 (48 LUT4s) Number of ripple logic: 5 (10 LUT4s) Number of shift registers: 0 Total number of LUT4s: 113 Number of PIO sites used: 3 out of 22 (14%) Number of block RAMs: 0 out of 0 Number of GSRs: 1 out of 1 (100%) EFB used : No JTAG used : No Readback used : No Oscillator used : No Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 4 Net n141: 4 loads, 4 rising, 0 falling (Driver: i702_2_lut_3_lut ) Net n5: 4 loads, 4 rising, 0 falling (Driver: i698_2_lut_3_lut_4_lut ) Net n137: 1 loads, 1 rising, 0 falling (Driver: i362_4_lut_3_lut_4_lut ) Net CLK_c: 3 loads, 0 rising, 3 falling (Driver: PIO CLK ) Number of Clock Enables: 0 Number of LSRs: 2 Net RST_c: 3 loads, 3 LSLICEs Net n5_adj_1: 1 loads, 1 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net sram_impl/r_addr_0: 32 loads Net sram_impl/r_addr_1: 32 loads Net sram_impl/r_addr_2: 32 loads Net sram_impl/r_addr_3: 32 loads Net RST_c: 17 loads Net sram_impl/r_addr_4: 16 loads Net adreg_0: 9 loads Net adreg_1: 9 loads Net adreg_2: 9 loads Net adreg_3: 9 loads Number of warnings: 1 Number of errors: 0 Design Errors/Warnings WARNING: logical net 'add_139_2/CI' has no driver IO (PIO) Attributes +---------------------+-----------+-----------+------------+ | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | +---------------------+-----------+-----------+------------+ | CLK | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WE | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | RST | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ Removed logic Block i721 undriven or does not drive anything - clipped. Signal n15 was merged into signal RST_c Signal sram_impl/n4 was merged into signal CLK_c Signal GND_net undriven or does not drive anything - clipped. Signal VCC_net undriven or does not drive anything - clipped. Signal add_139_cout/S1 undriven or does not drive anything - clipped. Signal add_139_cout/CO undriven or does not drive anything - clipped. Signal add_139_2/S0 undriven or does not drive anything - clipped. Signal add_139_2/CI undriven or does not drive anything - clipped. Block i356 was optimized away. Block sram_impl/i4 was optimized away. Block i1 was optimized away. Memory Usage /sram_impl/mem0: EBRs: 0 RAM SLICEs: 3 Logic SLICEs: 0 PFU Registers: 0 /sram_impl/mem1: EBRs: 0 RAM SLICEs: 3 Logic SLICEs: 0 PFU Registers: 0 /sram_impl/mem2: EBRs: 0 RAM SLICEs: 3 Logic SLICEs: 0 PFU Registers: 0 /sram_impl/mem3: EBRs: 0 RAM SLICEs: 3 Logic SLICEs: 0 PFU Registers: 0 /sram_impl/mem4: EBRs: 0 RAM SLICEs: 3 Logic SLICEs: 0 PFU Registers: 0 /sram_impl/mem5: EBRs: 0 RAM SLICEs: 3 Logic SLICEs: 0 PFU Registers: 0 /sram_impl/mem6: EBRs: 0 RAM SLICEs: 3 Logic SLICEs: 0 PFU Registers: 0 /sram_impl/mem7: EBRs: 0 RAM SLICEs: 3 Logic SLICEs: 0 PFU Registers: 0 GSR Usage --------- GSR Component: The Global Set Reset (GSR) resource has been used to implement a global reset of the design. The reset signal used for GSR control is 'RST_c'. GSR Property: The design components with GSR property set to ENABLED will respond to global set reset while the components with GSR property set to DISABLED will not. Components with disabled GSR Property ------------------------------------- These components have the GSR property set to DISABLED. The components will not respond to the reset signal 'RST_c' via the GSR component. Type and number of components of the type: Register = 6 Type and instance name of component: Register : sram_impl/r_addr_i1 Register : sram_impl/r_addr_i3 Register : sram_impl/r_addr_i2 Register : sram_impl/r_addr_i4 Register : sram_impl/r_addr_i5 Register : sram_impl/r_addr_i6 Components with synchronous local reset also reset by asynchronous GSR ---------------------------------------------------------------------- These components have the GSR property set to ENABLED and the local reset is synchronous. The components will respond to the synchronous local reset and to the unrelated asynchronous reset signal 'RST_c' via the GSR component. Type and number of components of the type: Register = 6 Type and instance name of component: Register : akku_8 Register : dlatchrs_101_i2 Register : dlatchrs_101_i3 Register : dlatchrs_101_i4 Register : dlatchrs_101_i5 Register : dlatchrs_101_i6 Run Time and Memory Usage ------------------------- Total CPU Time: 1 secs Total REAL Time: 0 secs Peak Memory Usage: 22 MB Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.