/*
 * Copyright (C) 2011 Koji Suzuki
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2.1 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

`include "rtavr_defs.v"

// global defines : OUTPUT_MUX_TRI

//`define OUTPUT_MUX_NONE
//`define OUTPUT_MUX_TRI

// Module Name: rtavr_ram_2KB
//  ver 005
// 
// Target Device:   xc3s200a-4ft256
// Product Version: ISE 12.4
// Design Goal:     Balanced
//
//                                NORMAL  MUX_TRI(FAKE) MUX_OR      
// Number of Slice Flip Flops:      8          0          0   
// Number of 4 input LUTs:          4          0          0
// Number of occupied Slices:       4          0          0
// Total Number of 4 input LUTs:    8          0          0
// Number of bonded IOBs :         58         58         57
//   IOB Flip Flops :               -          -          -
// Number of BUFGMUXs :             1          1          1
// Number of RAMB16BWEs :           1          1          1
// Clock to Setup 
//on destination clock CLK          ?          ?          ?

module rtavr_sram_2KB(
		input CLK,

		input WEA,
		input [10:0] ADDRA,
		input [7:0] DIA,
		output [7:0] DOA,
		
		input WEB,
`ifdef OUTPUT_MUX_NONE
`else
		input OE,
`endif
		input [10:0] ADDRB,
		input [7:0] DIB,
		output [7:0] DOB
		);
		
  reg  [7:0] mem [0:2048-1];
  reg  [10:0] r_addra;
 
  always @(posedge CLK)
  begin
    if(WEA) mem[ADDRA] <= DIA;
    r_addra <= ADDRA;
  end
 assign DOA = mem[r_addra];
 
  reg  [10:0] r_addrb;

  always @(posedge CLK)
  begin
	if(WEB) mem[ADDRB] <= DIB;
	r_addrb <= ADDRB;
  end
`ifdef OUTPUT_MUX_NONE
  assign DOB = mem[r_addrb];
`elsif OUTPUT_MUX_TRI
  bufif1(DOB, mem[r_addrb], OE);
`else
  assign DOB = OE? mem[r_addrb] : 0;
`endif
endmodule