`define OUTPUT_MUX_T1

// Module Name: rtavr_ram_2KB
// 
// Target Device:   xc3s200a-4ft256
// Product Version: ISE 12.4
// Design Goal:     Balanced
//
//                          DO:  NORMAL    TRISTATE(FAKE)   
// Number of Slice Flip Flops:      8          0   
// Number of 4 input LUTs:          4          0
// Number of occupied Slices:       4          0
// Total Number of 4 input LUTs:    8          0 
// Number of bonded IOBs :         58         58
//   IOB Flip Flops :              -          -
// Number of BUFGMUXs :             1          1
// Number of RAMB16BWEs :           1          1
// Clock to Setup 
//on destination clock CLK          ?          ?

module rtavr_sram_2KB(
		input CLK,WEA,
		input [10:0] ADDRA,
		input [7:0] DIA,
		output [7:0] DOA,

		input WEB, OE,
		input [10:0] ADDRB,
		input [7:0] DIB,
		output [7:0] DOB
		);
		
  reg  [7:0] mem [0:2048-1];
  reg  [7:0] i_doa;
  assign DOA = i_doa;

  always @(posedge CLK)
  begin
    if(WEA) mem[ADDRA] <= DIA;
    i_doa <= mem[ADDRA];
  end

  reg  [7:0] i_dob;

`ifdef OUTPUT_MUX_T1
  bufif1(DOB, i_dob, OE);
`else
  assign DOB = OE? i_dob : 0;
`endif
  always @(posedge CLK)
  begin
     if(WEB) mem[ADDRB] <= DIB;
     i_dob <= mem[ADDRB];
  end

endmodule