`define TEST2

module rtavr_sram_2KB(
		input CLK,WEA,
		input [10:0] ADDRA,
		input [7:0] DIA,
		output [7:0] DOA,
`ifdef TEST1
		input WEB,
		input [10:0] ADDRB,
		input [7:0] DIB,
		output [7:0] DOB
`elsif TEST2
		input WEB,OE,
		input [10:0] ADDRB,
		inout wire[7:0] DBUS
`else
`endif
		);
		
  reg  [7:0] mem [0:2048-1];
  reg  [7:0] i_doa;
  assign DOA = i_doa;

  always @(posedge CLK)
  begin
    if(WEA) mem[ADDRA] <= DIA;
    i_doa <= mem[ADDRA];
  end

`ifdef TEST1
  reg  [7:0] i_dob;
  assign DOB = i_dob;
  
  always @(posedge CLK)
  begin
     if(WEB) mem[ADDRB] <= DIB;
     i_dob <= mem[ADDRB];
  end
`elsif TEST2
  reg  [7:0] i_dob;

  bufif1(DBUS,i_dob,OE);

  always @(posedge CLK)
  begin
     if(WEB) mem[ADDRB] <= DBUS;
     i_dob <= mem[ADDRB];
  end
`else
`endif
endmodule