module rtavr_sram_2KB(
		input CLK,WEA,WEB,
		input [10:0] ADDRA,ADDRB,
		input [7:0] DIA,DIB,
		output [7:0] DOA,DOB
		);
		
  reg  [7:0] i_doa;
  reg  [7:0] i_dob;
  reg  [7:0] mem [0:2048-1];

  assign DOA = i_doa;
  assign DOB = i_dob;
  
  always @(posedge CLK)
  begin
    if(WEA) mem[ADDRA] <= DIA;
    i_doa <= mem[ADDRA];
  end

  always @(posedge CLK)
  begin
     if(WEB) mem[ADDRB] <= DIB;
     i_dob <= mem[ADDRB];
  end
endmodule