//`define NO_ROM
//`define NO_EXACC
// Module Name: rtavr_s0_fetch
// 
// Target Device:   xc3s200a-4ft256
// Product Version: ISE 12.4
// Design Goal:     Balanced
//
//            -  with 8KB ROM -  NORMAL   NO_EXACC
// Number of Slice Flip Flops:     34         24
// Number of 4 input LUTs:         47         39
// Number of occupied Slices:      39         33
// Total Number of 4 input LUTs:   50         39 
// Number of bonded IOBs :         92         84
//   IOB Flip Flops :               -         -
// Number of BUFGMUXs :             1          1
// Number of RAMB16BWEs :           4          4
// Clock to Setup 
//on destination clock CLK      4.436      3.660

module rtavr_s0_fetch (
		input CLK,
`ifdef NO_EXACC
`else
		input EXACC_IOR,EXACC_GPR,
		input [5:0] EXACC_ADDR,
`endif
`ifdef NO_ROM
		input [15:0] PM_OUT,
`else
		input [11:0] PC,
		input WEB, OE, 
		input [12:0] ADDRB,
		input [7:0] DIB, 
		output[7:0] DOB,
`endif
		output [15:0] INST,
		output[3:0] GPR_ADDRAL,
		output[3:0] GPR_ADDRAH,
		output[3:0] GPR_ADDRBL,
		output[3:0] GPR_ADDRBH,
		output GPR_PREDEC, GPR_POSTINC, 
		output[5:0] IOR_ADDR
		);

  reg [15:0] i_inst;
  assign INST = i_inst;
`ifdef NO_ROM
`else
  wire [15:0] PM_OUT;
  rtavr_rom_8KB PM(.CLK(CLK) , .ADDRA(PC), .DOA(PM_OUT) , 
		 .WEB(WEB) , .OE(OE) , .ADDRB(ADDRB),
		 .DIB(DIB), .DOB(DOB) 
		);
`endif
		
  wire i_predec = ( PM_OUT[15:10] == 6'b100100 ) & ( PM_OUT[1:0] == 2'b10 );
//         LD.Rd.--X	1001:000d:dddd:1110
//         ST.--X.Rr	1001:001r:rrrr:1110
//         LD.Rd.--Y	1001:000d:dddd:1010
//         ST.--Y.Rr	1001:001r:rrrr:1010
//         LD.Rd.--Z	1001:000d:dddd:0010
//         ST.--Z.Rr	1001:001r:rrrr:0010
//         ELPM.Rd.Z    1001:000d:dddd:0110  << undefined instruction
  wire i_postinc = ( PM_OUT[15:10] == 6'b100100 ) & ( PM_OUT[1:0] == 2'b01 );
//         LD.Rd.X++	1001:000d:dddd:1101
//         ST.X++.Rr	1001:001r:rrrr:1101
//         LD.Rd.Y++	1001:000d:dddd:1001
//         ST.Y++.Rr	1001:001r:rrrr:1001
//         LD.Rd.Z++	1001:000d:dddd:0001
//         ST.Z++.Rr	1001:001r:rrrr:0001
//         LPM.Rd.Z++   1001:000d:dddd:0101  << undefined instruction
  wire i_xreg = ( PM_OUT[15:10] == 6'b100100 ) & ( PM_OUT[3:2] == 2'b11 )
                  & ( PM_OUT[1:0] != 2'b11 );
//       0xa,0xb: (26 - 16, 27 - 16)
//         LD.Rd.X	1001:000d:dddd:1100
//         ST.X.Rr	1001:001r:rrrr:1100
//         LD.Rd.X++	1001:000d:dddd:1101
//         ST.X++.Rr	1001:001r:rrrr:1101
//         LD.Rd.--X	1001:000d:dddd:1110
//         ST.--X.Rr	1001:001r:rrrr:1110
//         POP          1001:000d:dddd:1111  <<<
//         PUSH         1001:001d:dddd:1111  <<<
  wire i_yreg = ( PM_OUT[15:10] == 6'b100100 ) & ( PM_OUT[3:2] == 2'b10 );
//       0xc,0xd:(28 - 16, 29 - 16)
//         LD.Rd.Y	1000:000d:dddd:1000
//         ST.Y.Rr	1000:001r:rrrr:1000
//         LD.Rd.Y++	1001:000d:dddd:1001
//         ST.Y++.Rr	1001:001r:rrrr:1001
//         LD.Rd.--Y	1001:000d:dddd:1010
//         ST.--Y.Rr	1001:001r:rrrr:1010
  wire i_zreg = ( PM_OUT[15:10] == 6'b100100 ) & ( PM_OUT[3:2] == 2'b00 );
//       0xe,0xf:(30 - 16, 31 - 16)
//         LD.Rd.Z	1000:000d:dddd:0000
//         ST.Z.Rr	1000:001r:rrrr:0000
//         LD.Rd.Z++	1001:000d:dddd:0001
//         ST.Z++.Rr	1001:001r:rrrr:0001
//         LD.Rd.--Z	1001:000d:dddd:0010
//         ST.--Z.Rr	1001:001r:rrrr:0010
  wire i_icall = ( PM_OUT[15:10] == 6'b100101 ) & ( PM_OUT[3:0] == 4'b1001 );
//        0xe,0xf:(30 - 16, 31 - 16)
//          IJMP	1001:0100:0000:1001
//          ICALL	1001:0101:0000:1001
//          EIJMP       1001:0100:0001:1001  << undefined instruction
//          EICALL      1001:0101:0001:1001  << undefined instruction
  wire i_inout = ( PM_OUT[15:12] == 4'b1011 );
//      { PM_OUT[10:9], PM_OUT[3:0] }
//         IN           1011:0AAd:dddd:AAAA
//         OUT          1011:1AAr:rrrr:AAAA
  wire i_xbi = ( PM_OUT[15:10] == 6'b100110 );
//      { 1'b0 , PM_OUT[7:3] }
//         CBI	        1001:1000:AAAA:Abbb
//         SBIC	        1001:1001:AAAA:Abbb
//         SBI	        1001:1010:AAAA:Abbb
//         SBIS	        1001:1011:AAAA:Abbb
//  wire i_sreg 
//          63
//         BRBC		1111:01kk:kkkk:ksss
//         BRBS		1111:00kk:kkkk:ksss
//         BSET		1001:0100:0sss:1000
//         BCLR		1001:0100:1sss:1000

assign GPR_PREDEC  = i_predec;
assign GPR_POSTINC = i_postinc;
assign GPR_ADDRAL   = i_xreg ? (26 - 16) : i_yreg ? (28 - 16)
                    : i_zreg ? (30 - 16) : PM_OUT[7:4];
assign GPR_ADDRAH   = 
`ifdef NO_EXACC
`else
                    EXACC_GPR ? EXACC_ADDR[3:0] : 
`endif
                      i_xreg ? (27 - 16) : i_yreg ? (29 - 16)
                    : i_zreg ? (31 - 16) : INST[7:4];
assign GPR_ADDRBL   = i_icall ? (30 - 16) : PM_OUT[3:0];
assign GPR_ADDRBH   = i_icall ? (31 - 16) : PM_OUT[3:0];
		   
assign IOR_ADDR    = 
`ifdef NO_EXACC
`else
                    EXACC_IOR ? EXACC_ADDR[5:0] : 
`endif
                      i_inout ? { PM_OUT[10:9], PM_OUT[3:0] }
                    : i_xbi  ? { 1'b0 , PM_OUT[7:3] }
		    : 63 ;

  always @(posedge CLK)
  begin
    i_inst <= PM_OUT;
  end

endmodule