/*
 * Copyright (C) 2011 Koji Suzuki
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, version 2.1 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

`include "rtavr_defs.v"
// global defines : OUTPUT_MUX_TRI 

//`define OUTPUT_MUX_NONE
//`define OUTPUT_MUX_TRI

// Module Name: rtavr_rom
//  ver 005
// 
// Target Device:   xc3s200a-4ft256
// Product Version: ISE 12.4
// Design Goal:     Balanced
//
//                   (1KW)       NORMAL MUX_TRI(FAKE) MUX_NONE  
// Number of Slice Flip Flops:      9          9         9    
// Number of 4 input LUTs:         10         10        10
// Number of occupied Slices:      10         10        10
// Total Number of 4 input LUTs:   10         10        10
// Number of bonded IOBs :         56         56        55
//   IOB Flip Flops :               -          -         -
// Number of BUFGMUXs :             1          1         1
// Number of RAMB16BWEs :           1          1         1
// Clock to Setup 
//on destination clock CLK          ?          ?         ?
// WARNING:Xst:647 - Input <ADDRA<11:10>> is never used. ..
// WARNING:Xst:646 - Signal <r_addrb<11:10>> is assigned but ..

module rtavr_rom # (
		parameter SIZE = 1024
//		parameter SIZE = 2048
//		parameter SIZE = 4096
) (
		input CLK,

		input [11:0] ADDRA,
		output [15:0] DOA,

		input WEB,
`ifdef OUTPUT_MUX_NONE
`else
		input OE,
`endif
		input [12:0] ADDRB,
		input [7:0] DIB, 
		output[7:0] DOB
		);
		
  reg  [15:0] mem [0:SIZE-1];
  reg  [11:0] r_addra;

  always @(posedge CLK)
  begin
	r_addra <= ADDRA;
  end
  assign DOA = mem[r_addra];

// PORTB 
  reg [11:0] r_addrb;
  reg r_doh;
  reg  [7:0] r_tmp;
  
  wire WEBH = ADDRB[0] & WEB;
  wire WEBL = ~ADDRB[0] & WEB;
  
  always @(posedge CLK)
  begin
	if(WEBL) r_tmp <=  DIB;
	if(WEBH) mem[ADDRB[12:1]] <=  { DIB , r_tmp };
	r_addrb <= ADDRB[12:1];
	r_doh <= ADDRB[0];
  end
`ifdef OUTPUT_MUX_NONE
  assign DOB = (r_doh)? mem[r_addrb][15:8]: mem[r_addrb][7:0];
`elsif OUTPUT_MUX_TRI  
  bufif1(DOB, (r_doh)? mem[r_addrb][15:8] : mem[r_addrb][7:0], OE);
`else 
  assign DOB = ~OE ? 0 : (r_doh)? mem[r_addrb][15:8]: mem[r_addrb][7:0];
`endif

endmodule