//`define OUTPUT_MUX_T1 // Module Name: rtavr_rom_8KB // // Target Device: xc3s200a-4ft256 // Product Version: ISE 12.4 // Design Goal: Balanced // // DO: NORMAL TRISTATE(FAKE) // Number of Slice Flip Flops: 8 9 // Number of 4 input LUTs: 12 10 // Number of occupied Slices: 11 9 // Total Number of 4 input LUTs: 12 10 // Number of bonded IOBs : 60 60 // IOB Flip Flops : - - // Number of BUFGMUXs : 1 1 // Number of RAMB16BWEs : 4 4 // Clock to Setup //on destination clock CLK 1.881 2.101 module rtavr_rom_8KB( input CLK, input [11:0] ADDRA, output [15:0] DOA, input WEB,OE, input [12:0] ADDRB, input [7:0] DIB, output[7:0] DOB ); reg [15:0] mem [0:4096-1]; reg [15:0] i_doa; assign DOA = i_doa; always @(posedge CLK) begin i_doa <= mem[ADDRA]; end reg [7:0] i_tmp; reg [15:0] i_dob; wire [11:0] i_addrb = ADDRB[12:1]; wire WEBH = ADDRB[1:0] & WEB; wire WEBL = ~ADDRB[1:0] & WEB; `ifdef OUTPUT_MUX_T1 bufif1(DOB, (ADDRB[1:0])? i_dob[15:8]: i_dob[7:0], OE); `else assign DOB = ~OE ? 0 : (ADDRB[1:0])? i_dob[15:8]: i_dob[7:0]; `endif always @(posedge CLK) begin if(WEBL) i_tmp <= DIB; if(WEBH) mem[i_addrb] <= { DIB , i_tmp }; i_dob <= mem[i_addrb]; end endmodule