`define TEST3

module rtavr_rom_8KB(
		input CLK,
		input [11:0] ADDRA,
		output [15:0] DOA,
`ifdef TEST1
		input WEB,
		input [11:0] ADDRB,
		input [15:0] DIB,
		output [15:0] DOB
`elsif TEST2
		input WEB,OE, 
		input [11:0] ADDRB,
		inout wire [15:0] DBUS16
`elsif TEST3
		input WEB,OE, 
		input [12:0] ADDRB,
		inout wire [7:0] DBUS
`else
`endif
		);
		
  reg  [15:0] mem [0:4096-1];
  reg  [15:0] i_doa;
  assign DOA = i_doa;

  always @(posedge CLK)
  begin
    i_doa <= mem[ADDRA];
  end
`ifdef TEST1  
  reg  [15:0] i_dob;
  assign DOB = i_dob;

  always @(posedge CLK)
  begin
     if(WEB) mem[ADDRB] <= DIB;
     i_dob <= mem[ADDRB];
  end
`elsif TEST2
  reg  [15:0] i_dob;

  bufif1(DBUS16,i_dob,OE);

  always @(posedge CLK)
  begin
     if(WEB) mem[ADDRB] <= DBUS16;
     i_dob <= mem[ADDRB];
  end
`elsif TEST3
  reg  [7:0] i_tmp;
  reg  [15:0] i_dob;
  
  wire [11:0] i_addrb = ADDRB[12:1]; 
  wire WEBH = ADDRB[1:0] & WEB;
  wire WEBL = ~ADDRB[1:0] & WEB;
  wire OEH = ADDRB[1:0] & OE;
  wire OEL = ~ADDRB[1:0] & OE;
  
  bufif1(DBUS,i_dob[7:0],OEL);
  bufif1(DBUS,i_dob[15:8],OEH);
  
  always @(posedge CLK)
  begin
     if(WEBL) i_tmp <=  DBUS;
     if(WEBH) mem[i_addrb] <=  { DBUS , i_tmp };
     i_dob <= mem[i_addrb];
  end
`else
`endif

endmodule