module rtavr_ior_port(
		input CLK,
		input WR,RD, 
		input [7:0] DI,
		input [4:0] ADDR,
		inout [7:0] DO
		// external I/O
		, inout [7:0] PORT
		);
  parameter BASE_ADDR = 0; // PORTA 0x00
//  parameter BASE_ADDR = 4; // PORTB 0x04
//  parameter BASE_ADDR = 27; // PORTC 0x1b

  reg  [7:0] i_pin;
  reg  [7:0] i_ddr;
  reg  [7:0] i_port;

  wire OE_pin = RD & (ADDR == BASE_ADDR); 
  wire OE_ddr = RD & (ADDR == (BASE_ADDR + 1)); 
  wire OE_port = RD & (ADDR == (BASE_ADDR + 2)); 
  //wire WE_pin = WR & (ADDR == BASE_ADDR); 
  wire WE_ddr = WR & (ADDR == (BASE_ADDR + 1)); 
  wire WE_port = WR & (ADDR == (BASE_ADDR + 2));

  bufif1(DO,i_pin,OE_pin);
  bufif1(DO,i_ddr,OE_ddr);
  bufif1(DO,i_port,OE_port);

  always @(posedge CLK)
  begin
    //if(WE_pin) i_pin <= DI;
    if(WE_ddr) i_ddr <= DI;
    if(WE_port) i_port <= DI;
    i_pin <= PORT;
  end
  generate 
       genvar i;
       for (i=0; i<8; i=i+1)
       begin : port_out
          bufif1(PORT[i],i_port[i],i_ddr[i]);
       end
  endgenerate
endmodule