// GPR modele for the Reduced Core TinyAVR (attiny10) 
// version 003 -- test code
// 
// Target Device: xc3s200a-4ft256
// Product Version: ISE 12.4
// Design Goal: Balanced
// TEST2 : No WriteBack and No OPs
// TEST3 : No WriteBack and PreDec
// TEST5 : with WriteBack and PreDec
// TEST6 : Implement Post-Incliment
// TEST7 : Insert LATCHes for Timing
//                                  TEST2  TEST3   TEST5    TEST6    TEST7
// Number of Slice Flip Flops:        36     36      35       45       61
// Number of 4 input LUTs:            27     37      51       93       93
// Number of occupied Slices:         24     33      40       62       70
// Total Number of 4 input LUTs:      27     44(+17) 60(+16) 100(+40) 100
// Number used for Dual Port RAMs:    16     16      16       16       16
// Number of bonded IOBs:             58     59      60       61       61
// Post-PAR Static Timing Report
// Clock to Setup                  5.084  7.782   8.688    9.022   10.302

`define USE_DMY_CLOCK
//`define OUTPUT_WB_ADDR
`define TEST7

module rtavr_gpr_16(
				input CLK2X,
`ifdef USE_DMY_CLOCK
`else
				input CLK,
`endif
				input WE,
				input PREDEC, POSTINC, 
				input [7:0] DI,
				input [3:0] ADDRAL, ADDRAH, ADDRBL, ADDRBH,
				output [7:0] DOAL, DOAH, DOBL, DOBH
				, output WB_VALID
`ifdef OUTPUT_WB_ADDR
				, output [3:0] WB_ADDR
`endif
				);
// Timing MEMO:
//
// CLK2X    1       0       1        0        1       0        1       0
// CLK           1               0                1                0
//      |  ALL input    |   ALL input     |               |                |
//      |               |   (no change)   |               |                |
//                                        |   WB_VALID , WB_ADDR           |
//                                        |  DOAH , DOBH                   |
//    -- TEST6          |   DOAL,DOBL,                    |
//       TEST7                            | DOAL,DOBL,                     |
`ifdef USE_DMY_CLOCK
  reg CLK;
`endif

  reg  [7:0] i_DOAL,i_DOAH;
  reg  [7:0] i_DOBL,i_DOBH;
  reg  [7:0] gpr [0:15];

  assign DOAL = i_DOAL;
  assign DOAH = i_DOAH;
  assign DOBL = i_DOBL;
  assign DOBH = i_DOBH;

`ifdef TEST1
`elsif TEST2
  wire [3:0] ADDRA = (CLK == 1) ? ADDRAL : ADDRAH;
  wire [3:0] ADDRB = (CLK == 1) ? ADDRBL : ADDRBH;
`elsif TEST3
  wire [3:0] ADDRA = (CLK == 1) ? ADDRAL : ADDRAH;
  wire [3:0] ADDRB = (CLK == 1) ? ADDRBL : ADDRBH;
  wire [8:0] DOA = { 0, gpr[ADDRA] };
  reg   c;
  wire [8:0] DOA2 = PREDEC ? DOA-(~CLK | c): DOA;
`elsif TEST4
`elsif TEST5
  wire [3:0] ADDRA = (CLK == 1) ? ADDRAL : ADDRAH;
  wire [3:0] ADDRB = (CLK == 1) ? ADDRBL : ADDRBH;
  wire [8:0] DOA = { 0, gpr[ADDRA] };
  reg  c;
  reg  i_wb_valid;
  wire [8:0] DOA2 = PREDEC ? DOA-(~CLK | c) : DOA;
  wire WE2 = (CLK == 0) ? (WE | i_wb_valid) : PREDEC ;
  wire [7:0] DI2 = (WE == 1) ? DI : (i_wb_valid == 1) ? i_DOAH : DOA2 ;
  assign WB_VALID = i_wb_valid;
`elsif TEST6
  wire [3:0] ADDRA = (CLK == 1) ? ADDRAL : ADDRAH;
  wire [3:0] ADDRB = (CLK == 1) ? ADDRBL : ADDRBH;
  wire [8:0] DOA = { 0, gpr[ADDRA] };
  reg  c;
  reg  i_wb_valid;
  wire WB = (PREDEC | POSTINC);
  `ifdef OUTPUT_WB_ADDR
    reg  [3:0] i_wb_addr;
    assign WB_ADDR = i_wb_addr;
  `endif
  reg  [7:0] i_wb_data;

  wire [8:0] DOA2 =  PREDEC ? DOA-(~CLK | c) : DOA;
  wire [8:0] WB_DATA = POSTINC ? DOA+(~CLK | c): DOA2;
  
  wire WE2 = (CLK == 0) ? (WE | i_wb_valid) : WB ;
  wire [7:0] DI2 = (WE == 1) ? DI : (i_wb_valid == 1) ? i_wb_data: WB_DATA ;
  assign WB_VALID = i_wb_valid;
`elsif TEST7
  wire [3:0] ADDRA = (CLK == 1) ? ADDRAL : ADDRAH;
  wire [3:0] ADDRB = (CLK == 1) ? ADDRBL : ADDRBH;
  wire [8:0] DOA = { 0, gpr[ADDRA] };
  reg  c;
  reg  i_wb_valid;
  wire WB = (PREDEC | POSTINC);
  reg  [7:0] i0_DOAL,i0_DOBL;

  `ifdef OUTPUT_WB_ADDR
    reg  [3:0] i_wb_addr;
    assign WB_ADDR = i_wb_addr;
  `endif
  reg  [7:0] i_wb_data;

  wire [8:0] DOA2 =  PREDEC ? DOA-(~CLK | c) : DOA;
  wire [8:0] WB_DATA = POSTINC ? DOA+(~CLK | c): DOA2;
  
  wire WE2 = (CLK == 0) ? (WE | i_wb_valid) : WB ;
  wire [7:0] DI2 = (WE == 1) ? DI : (i_wb_valid == 1) ? i_wb_data: WB_DATA ;
  assign WB_VALID = i_wb_valid;
`else
`endif

`ifdef USE_DMY_CLOCK
always @(posedge CLK2X)
  begin
     CLK <= ~CLK;
  end
`endif

always @(posedge CLK2X)
  begin
`ifdef TEST2
     if (CLK == 1) i_DOAL <= gpr[ADDRA];
     if (CLK == 1) i_DOBL <= gpr[ADDRB];
	  
	  if (CLK == 0) i_DOAH <= gpr[ADDRA];
     if (CLK == 0) i_DOBH <= gpr[ADDRB];

     if ((CLK == 0) && WE) gpr[ADDRA] <= DI;
`elsif TEST3
     if (CLK == 1) i_DOAL <= DOA2[7:0];
     if (CLK == 1) i_DOBL <= gpr[ADDRB];
	  
	  if (CLK == 0) i_DOAH <= DOA2[7:0];
     if (CLK == 0) i_DOBH <= gpr[ADDRB];

     if ((CLK == 0) && WE) gpr[ADDRA] <= DI;
     c <= DOA2[8];
`elsif TEST4
`elsif TEST5
     if (CLK == 1) i_DOAL <= DOA2[7:0];
     if (CLK == 1) i_DOBL <= gpr[ADDRB];

	  if (CLK == 0) i_DOAH <= DOA2[7:0];
     if (CLK == 0) i_DOBH <= gpr[ADDRB];
	  if (CLK == 0) i_wb_valid <= PREDEC & c;
	  
     if (WE2) gpr[ADDRA] <= DI2;     
     c <= DOA2[8];
`elsif TEST6
     if (CLK == 1) i_DOAL <= DOA2[7:0];
     if (CLK == 1) i_DOBL <= gpr[ADDRB];
	  
	  if (CLK == 0) i_DOAH <= DOA2[7:0];
     if (CLK == 0) i_DOBH <= gpr[ADDRB];
	  if (CLK == 0) i_wb_valid <= WB & c;	  
	  if (CLK == 0) i_wb_data <= WB_DATA[7:0];
  `ifdef OUTPUT_WB_ADDR
	  if (CLK == 0) i_wb_addr <= ADDRAH;
  `endif
     if (WE2) gpr[ADDRA] <= DI2;
     c <= WB_DATA[8];
`elsif TEST7
     if (CLK == 1) i0_DOAL <= DOA2[7:0];
     if (CLK == 1) i0_DOBL <= gpr[ADDRB];

     if (CLK == 0) i_DOAL <= i0_DOAL;
     if (CLK == 0) i_DOBL <= i0_DOBL;	  
	  if (CLK == 0) i_DOAH <= DOA2[7:0];
     if (CLK == 0) i_DOBH <= gpr[ADDRB];
	  if (CLK == 0) i_wb_valid <= WB & c;	  
	  if (CLK == 0) i_wb_data <= WB_DATA[7:0];
  `ifdef OUTPUT_WB_ADDR
	  if (CLK == 0) i_wb_addr <= ADDRAH;
  `endif

     if (WE2) gpr[ADDRA] <= DI2;
     c <= WB_DATA[8];
`else
`endif
  end
endmodule