Synthesis and Ngdbuild Report synthesis: version Diamond_1.4_Production (87) Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Sat Feb 25 13:39:15 2012 Command Line: synthesis -f MachXO2_Breakout_rtavr_xo2_lattice.synproj -- all messages logged in file synthesis.log Synthesis Options INFO: Synthesis Options: (LSE-1022) INFO: -a option is = MachXO2 INFO: -s option is = 1 INFO: -t option is = TQFP144 INFO: -d option is = LCMXO2-1200ZE INFO: Using package TQFP144 INFO: Using performance grade 1 INFO: INFO: ########################################################## INFO: ### Lattice Family : MachXO2A INFO: ### Device : LCMXO2-1200ZE INFO: ### Package : TQFP144 INFO: ### Speed : 1 INFO: ########################################################## INFO: INFO: Optimization Goal = Area INFO: -top option is not used WARNING: Ignoring Frequency option in Area Mode, Setting to default frequency of 1.0 MHz INFO: Target Frequency = 1.000000 MHz INFO: Max Fanout = 1000 INFO: Timing Path count = 3 INFO: bram Utilization = 100.000000 % INFO: dsp usage = TRUE (default) INFO: dsp utilization = 100 (default) INFO: fsm_encoding_style = auto INFO: Mux style = Auto INFO: Use Carry Chain = TRUE INFO: carry_chain_length = 0 INFO: Use IO Insertion = TRUE INFO: Use IO Reg = TRUE INFO: Resource Sharing = TRUE INFO: Propagate Constants = TRUE INFO: Remove Duplicate Registers = TRUE INFO: force_gsr = auto INFO: ROM style = auto INFO: RAM style = auto INFO: -comp option is FALSE INFO: -syn option is FALSE INFO: -p C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr_xo2/source (searchpath added) INFO: -p C:/Documents and Settings/suz/My Documents/rtavr_diamond (searchpath added) INFO: -p C:/lscc/diamond/1.4/ispfpga/xo2c00/data (searchpath added) INFO: -p C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr_xo2 (searchpath added) INFO: -p C:/Documents and Settings/suz/My Documents/rtavr_diamond (searchpath added) INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr_xo2/source/rtavr_defs.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr_xo2/source/rtavr_common.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_alu.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_gpr_16.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_cpi.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_ms.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_port.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_ps.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_spi.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_timer0.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_usart.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_rom_4p.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_s0_fetch.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_s1_decode.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_smp.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_sram.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/isp_sample/isp.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr-0.9.5/xo2_sample/xo2_isp.v INFO: Ngd file = MachXO2_Breakout_rtavr_xo2.ngd INFO: -sdc option: sdc file input not used INFO: -lpf option: output file option is OFF INFO: hardtimer checking is enabled (default); -dt option not used INFO: -r option is OFF [ Remove LOC Properties is OFF ] -- Technology check ok...MachXO, MachXO2... INFO: The default vhdl library search path is now "c:/lscc/diamond/1.4/cae_library/vhdl_packages/vdbs" (VHDL-1504) INFO: ** Recompile design ** -- Technology check ok...MachXO, MachXO2... Compile Design INFO: Compile Design Begin c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/xo2_sample/xo2_isp.v(23): INFO: compiling module xo2_isp (VERI-1018) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/isp_sample/isp.v(83): INFO: compiling module isp (VERI-1018) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr.v(76): INFO: compiling module rtavr (VERI-1018) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_gpr_16.v(67): INFO: compiling module rtavr_gpr_16 (VERI-1018) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_ms.v(47): INFO: compiling module rtavr_ior(CPUID=0) (VERI-1018) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_ps.v(37): INFO: compiling module rtavr_ior_ps(CPUID=0) (VERI-1018) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_timer0.v(43): INFO: compiling module rtavr_ior_timer0(BASE_ADDR=6'b010101) (VERI-1018) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_spi.v(80): INFO: compiling module rtavr_ior_spi(BASE_ADDR=6'b101110) (VERI-1018) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_usart.v(66): INFO: compiling module rtavr_ior_usart(BASE_ADDR=6'b01110) (VERI-1018) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_port.v(51): INFO: compiling module rtavr_ior_port(BASE_ADDR=6'b011011) (VERI-1018) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_sram.v(43): INFO: compiling module rtavr_sram(SIZE=2048) (VERI-1018) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_rom_4p.v(60): INFO: compiling module rtavr_rom(SIZE=2048) (VERI-1018) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_s0_fetch.v(30): INFO: compiling module rtavr_s0_fetch (VERI-1018) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_s1_decode.v(42): INFO: compiling module rtavr_s1_decode (VERI-1018) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_alu.v(40): INFO: compiling module rtavr_alu (VERI-1018) INFO: ######## Converting i/o port : RXD to OUTPUT ... (LSE-1067) INFO: ######## Converting i/o port : CTS to INPUT ... (LSE-1068) INFO: ######## Converting i/o port : EXTOSC_EN to OUTPUT ... (LSE-1067) INFO: ######## Missing driver on net : PIN[18], patching with GND... (LSE-1017) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_ps.v(519): WARNING: Register \RTAVR/IOR/IOR_PS0/gi_int0_prev_214 is stuck at Zero (VDB-5013) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_usart.v(613): WARNING: Register \RTAVR/IOR/i_usart/RXB8_417 is stuck at Zero (VDB-5013) INFO: ######## Duplicated RAM Net :\RTAVR/GPR/gpr_lo to \RTAVR/GPR/gpr_lo_d0 to map to Lattice RAMs (LSE-1110) INFO: ######## Duplicated RAM Net :\RTAVR/GPR/gpr_lo to \RTAVR/GPR/gpr_lo_d1 to map to Lattice RAMs (LSE-1110) INFO: ######## Duplicated RAM Net :\RTAVR/GPR/gpr_hi to \RTAVR/GPR/gpr_hi_d2 to map to Lattice RAMs (LSE-1110) INFO: ######## Found 7 RAM Nets in design (LSE-1115) INFO: ######## Mapping RAM Net \RTAVR/ROM/rom to 4 EBR blocks in SINGLE_PORT Mode INFO: ######## Mapping RAM Net \RTAVR/RAM/mem to 2 EBR blocks in SINGLE_PORT Mode INFO: ######## Mapping RAM Net \RTAVR/GPR/gpr_lo to 2 Distributed blocks in PSEUDO_DUAL_PORT Mode INFO: ######## Mapping RAM Net \RTAVR/GPR/gpr_hi to 2 Distributed blocks in PSEUDO_DUAL_PORT Mode INFO: ######## Mapping RAM Net \RTAVR/GPR/gpr_lo_d0 to 2 Distributed blocks in PSEUDO_DUAL_PORT Mode INFO: ######## Mapping RAM Net \RTAVR/GPR/gpr_lo_d1 to 1 EBR blocks in PSEUDO_DUAL_PORT Mode INFO: ######## Mapping RAM Net \RTAVR/GPR/gpr_hi_d2 to 2 Distributed blocks in PSEUDO_DUAL_PORT Mode c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_usart.v(613): WARNING: Bit 0 of Register \RTAVR/IOR/i_usart/r_count_max_x is stuck at Zero (VDB-5010) INFO: Duplicate Register/Latch removal : \RTAVR/GPR/s2_DOBH is one to one match with \RTAVR/S1/n_reset_436 c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_ps.v(433): WARNING: Register \RTAVR/IOR/IOR_PS0/r_sph_i3 is stuck at Zero (VDB-5013) c:/documents and settings/suz/my documents/rtavr_diamond/rtavr-0.9.5/soc/rtavr_ior_port.v(136): WARNING: Register \RTAVR/IOR/i_port_c/r_pin_i2 is stuck at Zero (VDB-5013) INFO: Duplicate Register/Latch removal : \RTAVR/GPR/s2_addrbh_i0 is one to one match with \RTAVR/GPR/gpr_lo_d1_836 INFO: Duplicate Register/Latch removal : \RTAVR/GPR/s2_addrbh_i2 is one to one match with \RTAVR/GPR/gpr_lo_d1_841 INFO: Duplicate Register/Latch removal : \RTAVR/GPR/s2_addrbh_i1 is one to one match with \RTAVR/GPR/gpr_lo_d1_838 INFO: GSR Instance connected to net: \ISP/n1 (LSE-1148) INFO: GSR will not be inferred since no asynchronous signal was found in netlist (LSE-1147) WARNING: No lpf file will be written because -lpf option is not used or set to 0 INFO: Applying 1.000000 MHz constraint to all clocks (LSE-5000) INFO: Results of ngd drc checks are available in xo2_isp_drc.log INFO: All blocks are expanded and NGD expansion is successful INFO: Writing ngd file MachXO2_Breakout_rtavr_xo2.ngd ################### Begin Area Report (xo2_isp)###################### Number of register bits => 457 of 5444 (8 % ) CCU2D => 72 DCMA => 1 DP8KC => 1 DPR16X4C => 10 EHXPLLJ => 1 FD1P3AX => 39 FD1P3IX => 123 FD1P3JX => 10 FD1S1A => 16 FD1S3AX => 37 FD1S3IX => 227 FD1S3JX => 5 GSR => 1 IB => 5 INV => 9 JTAGF => 1 L6MUX21 => 32 LUT4 => 822 MUX41 => 29 MUX81 => 3 OB => 11 OSCH => 1 PFUMX => 92 SP8KC => 6 ################### End Area Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 7 Net : CLK180_OUT, loads : 178 Net : CLK0_OUT, loads : 173 Net : CLK270_OUT, loads : 50 Net : CLK_L, loads : 16 Net : CLK90_OUT, loads : 15 Net : CLK_B, loads : 13 Net : CLK_90_270, loads : 2 Clock Enable Nets Number of Clock Enables: 47 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : BSCAN_RESET_N, loads : 332 Net : GPR_PREDEC, loads : 58 Net : IOR_ADDRB_1, loads : 45 Net : IOR_ADDRB_0, loads : 44 Net : IOR_ADDRB_2, loads : 43 Net : n16, loads : 37 Net : CMD_ALU_ES1, loads : 33 Net : IOR_ADDRB_3, loads : 33 Net : IOR_ADDRB_5, loads : 29 Net : IOR_ADDRB_4, loads : 29 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 1000.000000 -name | | | clk5 [get_nets CLK90_OUT] | -| -| 0 | | | create_clock -period 1000.000000 -name | | | clk4 [get_nets CLK270_OUT] | -| -| 0 | | | create_clock -period 1000.000000 -name | | | clk3 [get_nets \RTAVR/CLK_B] | 1.000 MHz| 326.691 MHz| 1 | | | create_clock -period 1000.000000 -name | | | clk2 [get_nets CLK0_OUT] | -| -| 0 | | | create_clock -period 1000.000000 -name | | | clk1 [get_nets \RTAVR/CLK_L] | -| -| 0 | | | create_clock -period 1000.000000 -name | | | clk0 [get_nets CLK180_OUT] | 1.000 MHz| 9.985 MHz| 12 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 52.168 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 37.516 secs --------------------------------------------------------------