Synthesis and Ngdbuild  Report
#Build: Synplify Pro F-2011.09L, Build 022R, Oct 19 2011
#install: Y:\Program_Files\lscc\diamond\1.4\synpbase
#OS: Windows XP 5.1
#Hostname: K-SUZUKI-FQ1

$ Start of Compile
#Thu Feb 23 17:28:10 2012

Synopsys Verilog Compiler, version comp560rcp1, Build 045R, built Oct 18 2011
@N|Running in 32-bit mode
Copyright (C) 1994-2011 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@I::"Y:\Program_Files\lscc\diamond\1.4\synpbase\lib\lucent\machxo.v"
@I::"Y:\Program_Files\lscc\diamond\1.4\synpbase\lib\vlog\scemi_objects.v"
@I::"Y:\Program_Files\lscc\diamond\1.4\synpbase\lib\vlog\hypermods.v"
@I::"Y:\Program_Files\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo.v"
@I::"Z:\AVR_CORE\rtavr_diamond\test_hdl_xo\source\tool_test.v"
@W: CG921 :"Z:\AVR_CORE\rtavr_diamond\test_hdl_xo\source\tool_test.v":227:7:227:9|CLK is already declared in this scope.
@I::"Z:\AVR_CORE\rtavr_diamond\rtavr_tools-0.6\test_hdl\isp.v"
@I::"Z:\AVR_CORE\rtavr_diamond\rtavr_tools-0.6\test_hdl\spi_echo.v"
Verilog syntax check successful!
Selecting top level module tool_test
@N: CG364 :"Y:\Program_Files\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo.v":591:7:591:11|Synthesizing module JTAGD

@N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr_tools-0.6\test_hdl\spi_echo.v":17:7:17:14|Synthesizing module spi_echo

@W: CG133 :"Z:\AVR_CORE\rtavr_diamond\rtavr_tools-0.6\test_hdl\spi_echo.v":29:8:29:15|No assignment to r_spi_in
@N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr_tools-0.6\test_hdl\isp.v":70:7:70:9|Synthesizing module isp

@N: CL134 :"Z:\AVR_CORE\rtavr_diamond\rtavr_tools-0.6\test_hdl\isp.v":241:4:241:9|Found RAM mem, depth=1024, width=8
@N: CG364 :"Y:\Program_Files\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo.v":1372:7:1372:10|Synthesizing module OSCC

@N: CG364 :"Z:\AVR_CORE\rtavr_diamond\test_hdl_xo\source\tool_test.v":25:7:25:15|Synthesizing module tool_test

@W: CL271 :"Z:\AVR_CORE\rtavr_diamond\test_hdl_xo\source\tool_test.v":233:2:233:7|Pruning bits 26 to 25 of clk_count[26:0] -- not in use ...

@END
Premap Report (contents appended below)
@N:"Z:\AVR_CORE\rtavr_diamond\test_hdl_xo\synlog\MachXO_Breakout_test_hdl_xo_premap.srr"
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 239R, Built Oct 19 2011 10:56:21
Copyright (C) 1994-2011, Synopsys Inc.  All Rights Reserved
Product Version F-2011.09L

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled 
@N: MF546 |Generated clock conversion enabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@W: FX474 |User specified initial value found in some of the sequential elements in the design. Applying an initial value to a register may not deliver the best synthesis results. For example, registers with initial values may be preserved and retiming/pipelining may not be performed. To improve synthesis results you may want to remove the register initialization from the RTL code 
syn_allowed_resources : blockrams=3  set on top level netlist tool_test

Finished Pre Mapping Phase. (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 77MB)

Pre Mapping successful!

At Mapper Exit (Time elapsed 0h:00m:01s; Memory used current: 42MB peak: 77MB)

Process took 0h:00m:07s realtime, 0h:00m:01s cputime
# Thu Feb 23 17:28:22 2012

###########################################################]
Map & Optimize Report (contents appended below)
@N:"Z:\AVR_CORE\rtavr_diamond\test_hdl_xo\synlog\MachXO_Breakout_test_hdl_xo_fpga_mapper.srr"
Synopsys Lattice Technology Mapper, Version maplat, Build 239R, Built Oct 19 2011 10:56:21
Copyright (C) 1994-2011, Synopsys Inc.  All Rights Reserved
Product Version F-2011.09L

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled 
@N: MF546 |Generated clock conversion enabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF203 |Set autoconstraint_io 


Starting Optimization and Mapping (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 77MB)


Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 77MB)

@N: BN362 :"z:\avr_core\rtavr_diamond\rtavr_tools-0.6\test_hdl\spi_echo.v":40:4:40:9|Removing sequential instance SPI_ECHO.r_data[7] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.tool_test(verilog) because there are no references to its outputs 
@N: BN362 :"z:\avr_core\rtavr_diamond\rtavr_tools-0.6\test_hdl\spi_echo.v":40:4:40:9|Removing sequential instance SPI_ECHO.r_data[6] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.tool_test(verilog) because there are no references to its outputs 
@N: BN362 :"z:\avr_core\rtavr_diamond\rtavr_tools-0.6\test_hdl\spi_echo.v":40:4:40:9|Removing sequential instance SPI_ECHO.r_data[5] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.tool_test(verilog) because there are no references to its outputs 
@N:"z:\avr_core\rtavr_diamond\test_hdl_xo\source\tool_test.v":233:2:233:7|Found counter in view:work.tool_test(verilog) inst clk_count[24:0]
@N:"z:\avr_core\rtavr_diamond\rtavr_tools-0.6\test_hdl\isp.v":163:4:163:9|Found counter in view:work.isp(verilog) inst r_pr[15:0]
@N:"z:\avr_core\rtavr_diamond\rtavr_tools-0.6\test_hdl\isp.v":163:4:163:9|Found counter in view:work.isp(verilog) inst r_count[3:0]

Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 77MB)



#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[

======================================================================================
                                Instance:Pin        Generated Clock Optimization Status
======================================================================================
                          SPI_ECHO.r_sck:C              Not Done
                              r_cs2_prev:C              Not Done


##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]


Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 77MB)



Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 77MB)


Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 77MB)


Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 77MB)


Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 77MB)


Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 77MB)


Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 77MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 77MB)

@N: FX164 |The option to pack flops in the IOB has not been specified 

Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 77MB)

Writing Analyst data base Z:\AVR_CORE\rtavr_diamond\test_hdl_xo\MachXO_Breakout_test_hdl_xo.srm

Finished Writing Netlist Databases (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 77MB)

Writing EDIF Netlist and constraint files
F-2011.09L

Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:03s; Memory used current: 79MB peak: 80MB)


Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 80MB)

@N: MF276 |Gated clock conversion enabled, but no gated clocks found in design 

Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 80MB)


Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 80MB)

@N: MF333 |Generated clock conversion enabled, but no generated clocks found in design 

Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 80MB)

@W: MT246 :"z:\avr_core\rtavr_diamond\test_hdl_xo\source\tool_test.v":166:7:166:18|Blackbox OSCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"z:\avr_core\rtavr_diamond\test_hdl_xo\source\tool_test.v":50:14:50:18|Blackbox JTAGD is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock tool_test|CLK_INT_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:CLK_INT"



##### START OF TIMING REPORT #####[
# Timing Report written on Thu Feb 23 17:28:40 2012
#


Top view:               tool_test
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.


Performance Summary 
*******************


Worst slack in design: 494.085

                                     Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock                       Frequency     Frequency     Period        Period        Slack       Type         Group              
-----------------------------------------------------------------------------------------------------------------------------------------
tool_test|CLK_INT_inferred_clock     1.0 MHz       84.5 MHz      1000.000      11.830        494.085     inferred     Inferred_clkgroup_0
System                               1.0 MHz       222.1 MHz     1000.000      4.503         995.497     system       system_clkgroup    
=========================================================================================================================================





Clock Relationships
*******************

Clocks                                                              |    rise  to  rise     |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                          Ending                            |  constraint  slack    |  constraint  slack    |  constraint  slack    |  constraint  slack  
------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                            System                            |  1000.000    995.497  |  No paths    -        |  No paths    -        |  No paths    -      
System                            tool_test|CLK_INT_inferred_clock  |  1000.000    996.826  |  No paths    -        |  1000.000    998.240  |  No paths    -      
tool_test|CLK_INT_inferred_clock  System                            |  1000.000    993.189  |  No paths    -        |  No paths    -        |  1000.000    994.149
tool_test|CLK_INT_inferred_clock  tool_test|CLK_INT_inferred_clock  |  1000.000    992.265  |  1000.000    989.621  |  500.000     494.927  |  500.000     494.085
==================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port        Starting            User           Arrival     Required          
Name        Reference           Constraint     Time        Time         Slack
            Clock                                                            
-----------------------------------------------------------------------------
TOP_TCK     System (rising)     NA             0.000       997.770           
TOP_TDI     System (rising)     NA             0.000       997.770           
TOP_TMS     System (rising)     NA             0.000       997.770           
=============================================================================


Output Ports: 

Port        Starting                                       User           Arrival     Required          
Name        Reference                                      Constraint     Time        Time         Slack
            Clock                                                                                       
--------------------------------------------------------------------------------------------------------
LED[0]      tool_test|CLK_INT_inferred_clock (falling)     NA             5.851       1000.000          
LED[1]      tool_test|CLK_INT_inferred_clock (falling)     NA             5.851       1000.000          
LED[2]      tool_test|CLK_INT_inferred_clock (falling)     NA             5.851       1000.000          
LED[3]      tool_test|CLK_INT_inferred_clock (falling)     NA             5.851       1000.000          
LED[4]      tool_test|CLK_INT_inferred_clock (falling)     NA             5.851       1000.000          
LED[5]      tool_test|CLK_INT_inferred_clock (rising)      NA             5.851       1000.000          
LED[6]      tool_test|CLK_INT_inferred_clock (rising)      NA             5.851       1000.000          
LED[7]      tool_test|CLK_INT_inferred_clock (rising)      NA             6.811       1000.000          
TOP_TDO     System (rising)                                NA             4.503       1000.000          
========================================================================================================


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report
Part: lcmxo2280c-3

Register bits: 96 of 2280 (4%)
PIC Latch:       0
I/O cells:       12
Block Rams : 1 of 3 (33%)


Details:
CCU2:           22
FD1P3AX:        61
FD1S3AX:        28
FD1S3IX:        7
GSR:            1
IB:             3
INV:            11
OB:             9
ORCALUT4:       61
PUR:            1
SP8KB:          1
VHI:            1
VLO:            1
false:          3
true:           3
Mapper successful!

At Mapper Exit (Time elapsed 0h:00m:04s; Memory used current: 24MB peak: 80MB)

Process took 0h:00m:16s realtime, 0h:00m:04s cputime
# Thu Feb 23 17:28:42 2012

###########################################################]