Place & Route TRACE Report

Loading design for application trce from file machxo_breakout_rtavr_xo.ncd.
Design name: xo2_isp
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2280C
Package:     FTBGA256
Performance: 3
Loading device for application trce from file 'mj5g21x17.nph' in environment Y:/Program_Files/lscc/diamond/1.4/ispfpga.
Package Status:                     Final          Version 1.26
Performance Hardware Data Status: Version 1.69
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond_1.4_Production (87)
Thu Feb 23 17:41:11 2012

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o MachXO_Breakout_rtavr_xo.twr MachXO_Breakout_rtavr_xo.ncd MachXO_Breakout_rtavr_xo.prf 
Design file:     machxo_breakout_rtavr_xo.ncd
Preference file: machxo_breakout_rtavr_xo.prf
Device,speed:    LCMXO2280C,3
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "CLK_OUT" 499.750000 MHz (160 errors)
  • 160 items scored, 160 timing errors detected. Warning: 3.689MHz is the maximum frequency for this preference.
  • FREQUENCY NET "CLK_INT_inferred_clock" 100.929000 MHz (4096 errors)
  • 4096 items scored, 4096 timing errors detected. Warning: 7.402MHz is the maximum frequency for this preference. Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "CLK_OUT" 499.750000 MHz ; 160 items scored, 160 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 6.589ns (weighted slack = -269.073ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_cmd_load (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_2 (to CLK_OUT -) Delay: 9.880ns (17.5% logic, 82.5% route), 4 logic levels. Constraint Details: 9.880ns physical path delay RTAVR/S1/SLICE_125 to RTAVR/ROM/SLICE_277 exceeds (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) 0.049ns delay constraint less -3.416ns skew and 0.174ns DIN_SET requirement (totaling 3.291ns) by 6.589ns Physical Path Details: Data path RTAVR/S1/SLICE_125 to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.613 R10C11D.CLK to R10C11D.Q0 RTAVR/S1/SLICE_125 (from CLK_INT_inferred_clock) ROUTE 28 2.085 R10C11D.Q0 to R15C5C.C1 RTAVR/CMD_LOAD CTOF_DEL --- 0.371 R15C5C.C1 to R15C5C.F1 SLICE_104 ROUTE 2 2.969 R15C5C.F1 to R14C2A.B1 RTAVR/un1_CMD_LOAD_2dup CTOF_DEL --- 0.371 R14C2A.B1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 3.100 R14C2A.F1 to R9C4C.B0 RTAVR/rd_romdup CTOF_DEL --- 0.371 R9C4C.B0 to R9C4C.F0 RTAVR/ROM/SLICE_277 ROUTE 1 0.000 R9C4C.F0 to R9C4C.DI0 RTAVR/ROM/fb_6 (to CLK_OUT) -------- 9.880 (17.5% logic, 82.5% route), 4 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/S1/SLICE_125: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R10C11D.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R9C4C.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Error: The following path exceeds requirements by 6.589ns (weighted slack = -269.073ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_cmd_load (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_3 (to CLK_OUT -) Delay: 9.880ns (17.5% logic, 82.5% route), 4 logic levels. Constraint Details: 9.880ns physical path delay RTAVR/S1/SLICE_125 to RTAVR/ROM/SLICE_277 exceeds (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) 0.049ns delay constraint less -3.416ns skew and 0.174ns DIN_SET requirement (totaling 3.291ns) by 6.589ns Physical Path Details: Data path RTAVR/S1/SLICE_125 to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.613 R10C11D.CLK to R10C11D.Q0 RTAVR/S1/SLICE_125 (from CLK_INT_inferred_clock) ROUTE 28 2.085 R10C11D.Q0 to R15C5C.C1 RTAVR/CMD_LOAD CTOF_DEL --- 0.371 R15C5C.C1 to R15C5C.F1 SLICE_104 ROUTE 2 2.969 R15C5C.F1 to R14C2A.B1 RTAVR/un1_CMD_LOAD_2dup CTOF_DEL --- 0.371 R14C2A.B1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 3.100 R14C2A.F1 to R9C4C.B1 RTAVR/rd_romdup CTOF_DEL --- 0.371 R9C4C.B1 to R9C4C.F1 RTAVR/ROM/SLICE_277 ROUTE 1 0.000 R9C4C.F1 to R9C4C.DI1 RTAVR/ROM/fb_5 (to CLK_OUT) -------- 9.880 (17.5% logic, 82.5% route), 4 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/S1/SLICE_125: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R10C11D.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R9C4C.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Error: The following path exceeds requirements by 6.530ns (weighted slack = -266.663ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_ea_13 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_2 (to CLK_OUT -) Delay: 9.821ns (21.4% logic, 78.6% route), 5 logic levels. Constraint Details: 9.821ns physical path delay RTAVR/SLICE_315 to RTAVR/ROM/SLICE_277 exceeds (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) 0.049ns delay constraint less -3.416ns skew and 0.174ns DIN_SET requirement (totaling 3.291ns) by 6.530ns Physical Path Details: Data path RTAVR/SLICE_315 to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.613 R12C13D.CLK to R12C13D.Q1 RTAVR/SLICE_315 (from CLK_INT_inferred_clock) ROUTE 1 2.607 R12C13D.Q1 to R15C3B.A1 RTAVR/S1_EA_13 CTOF_DEL --- 0.371 R15C3B.A1 to R15C3B.F1 RTAVR/SLICE_424 ROUTE 2 0.513 R15C3B.F1 to R15C3B.C0 RTAVR/EA_13 CTOF_DEL --- 0.371 R15C3B.C0 to R15C3B.F0 RTAVR/SLICE_424 ROUTE 3 1.504 R15C3B.F0 to R14C2A.A1 RTAVR/oe_rom_0 CTOF_DEL --- 0.371 R14C2A.A1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 3.100 R14C2A.F1 to R9C4C.B0 RTAVR/rd_romdup CTOF_DEL --- 0.371 R9C4C.B0 to R9C4C.F0 RTAVR/ROM/SLICE_277 ROUTE 1 0.000 R9C4C.F0 to R9C4C.DI0 RTAVR/ROM/fb_6 (to CLK_OUT) -------- 9.821 (21.4% logic, 78.6% route), 5 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/SLICE_315: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R12C13D.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R9C4C.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Error: The following path exceeds requirements by 6.530ns (weighted slack = -266.663ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_ea_13 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_3 (to CLK_OUT -) Delay: 9.821ns (21.4% logic, 78.6% route), 5 logic levels. Constraint Details: 9.821ns physical path delay RTAVR/SLICE_315 to RTAVR/ROM/SLICE_277 exceeds (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) 0.049ns delay constraint less -3.416ns skew and 0.174ns DIN_SET requirement (totaling 3.291ns) by 6.530ns Physical Path Details: Data path RTAVR/SLICE_315 to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.613 R12C13D.CLK to R12C13D.Q1 RTAVR/SLICE_315 (from CLK_INT_inferred_clock) ROUTE 1 2.607 R12C13D.Q1 to R15C3B.A1 RTAVR/S1_EA_13 CTOF_DEL --- 0.371 R15C3B.A1 to R15C3B.F1 RTAVR/SLICE_424 ROUTE 2 0.513 R15C3B.F1 to R15C3B.C0 RTAVR/EA_13 CTOF_DEL --- 0.371 R15C3B.C0 to R15C3B.F0 RTAVR/SLICE_424 ROUTE 3 1.504 R15C3B.F0 to R14C2A.A1 RTAVR/oe_rom_0 CTOF_DEL --- 0.371 R14C2A.A1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 3.100 R14C2A.F1 to R9C4C.B1 RTAVR/rd_romdup CTOF_DEL --- 0.371 R9C4C.B1 to R9C4C.F1 RTAVR/ROM/SLICE_277 ROUTE 1 0.000 R9C4C.F1 to R9C4C.DI1 RTAVR/ROM/fb_5 (to CLK_OUT) -------- 9.821 (21.4% logic, 78.6% route), 5 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/SLICE_315: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R12C13D.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R9C4C.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Error: The following path exceeds requirements by 6.498ns (weighted slack = -265.357ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_pr_13 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_2 (to CLK_OUT -) Delay: 9.789ns (21.4% logic, 78.6% route), 5 logic levels. Constraint Details: 9.789ns physical path delay ISP/SLICE_70 to RTAVR/ROM/SLICE_277 exceeds (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) 0.049ns delay constraint less -3.416ns skew and 0.174ns DIN_SET requirement (totaling 3.291ns) by 6.498ns Physical Path Details: Data path ISP/SLICE_70 to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.613 R16C3D.CLK to R16C3D.Q0 ISP/SLICE_70 (from CLK_INT_inferred_clock) ROUTE 3 2.575 R16C3D.Q0 to R15C3B.C1 ISP_ADDR_13 CTOF_DEL --- 0.371 R15C3B.C1 to R15C3B.F1 RTAVR/SLICE_424 ROUTE 2 0.513 R15C3B.F1 to R15C3B.C0 RTAVR/EA_13 CTOF_DEL --- 0.371 R15C3B.C0 to R15C3B.F0 RTAVR/SLICE_424 ROUTE 3 1.504 R15C3B.F0 to R14C2A.A1 RTAVR/oe_rom_0 CTOF_DEL --- 0.371 R14C2A.A1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 3.100 R14C2A.F1 to R9C4C.B0 RTAVR/rd_romdup CTOF_DEL --- 0.371 R9C4C.B0 to R9C4C.F0 RTAVR/ROM/SLICE_277 ROUTE 1 0.000 R9C4C.F0 to R9C4C.DI0 RTAVR/ROM/fb_6 (to CLK_OUT) -------- 9.789 (21.4% logic, 78.6% route), 5 logic levels. Clock Skew Details: Source Clock Path osc_internal to ISP/SLICE_70: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R16C3D.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R9C4C.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Error: The following path exceeds requirements by 6.498ns (weighted slack = -265.357ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_pr_13 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_3 (to CLK_OUT -) Delay: 9.789ns (21.4% logic, 78.6% route), 5 logic levels. Constraint Details: 9.789ns physical path delay ISP/SLICE_70 to RTAVR/ROM/SLICE_277 exceeds (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) 0.049ns delay constraint less -3.416ns skew and 0.174ns DIN_SET requirement (totaling 3.291ns) by 6.498ns Physical Path Details: Data path ISP/SLICE_70 to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.613 R16C3D.CLK to R16C3D.Q0 ISP/SLICE_70 (from CLK_INT_inferred_clock) ROUTE 3 2.575 R16C3D.Q0 to R15C3B.C1 ISP_ADDR_13 CTOF_DEL --- 0.371 R15C3B.C1 to R15C3B.F1 RTAVR/SLICE_424 ROUTE 2 0.513 R15C3B.F1 to R15C3B.C0 RTAVR/EA_13 CTOF_DEL --- 0.371 R15C3B.C0 to R15C3B.F0 RTAVR/SLICE_424 ROUTE 3 1.504 R15C3B.F0 to R14C2A.A1 RTAVR/oe_rom_0 CTOF_DEL --- 0.371 R14C2A.A1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 3.100 R14C2A.F1 to R9C4C.B1 RTAVR/rd_romdup CTOF_DEL --- 0.371 R9C4C.B1 to R9C4C.F1 RTAVR/ROM/SLICE_277 ROUTE 1 0.000 R9C4C.F1 to R9C4C.DI1 RTAVR/ROM/fb_5 (to CLK_OUT) -------- 9.789 (21.4% logic, 78.6% route), 5 logic levels. Clock Skew Details: Source Clock Path osc_internal to ISP/SLICE_70: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R16C3D.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R9C4C.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Error: The following path exceeds requirements by 6.105ns (weighted slack = -249.308ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_cmd_load (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_14 (to CLK_OUT -) Delay: 9.396ns (18.4% logic, 81.6% route), 4 logic levels. Constraint Details: 9.396ns physical path delay RTAVR/S1/SLICE_125 to RTAVR/ROM/SLICE_283 exceeds (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) 0.049ns delay constraint less -3.416ns skew and 0.174ns DIN_SET requirement (totaling 3.291ns) by 6.105ns Physical Path Details: Data path RTAVR/S1/SLICE_125 to RTAVR/ROM/SLICE_283: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.613 R10C11D.CLK to R10C11D.Q0 RTAVR/S1/SLICE_125 (from CLK_INT_inferred_clock) ROUTE 28 2.085 R10C11D.Q0 to R15C5C.C1 RTAVR/CMD_LOAD CTOF_DEL --- 0.371 R15C5C.C1 to R15C5C.F1 SLICE_104 ROUTE 2 2.969 R15C5C.F1 to R14C2A.B1 RTAVR/un1_CMD_LOAD_2dup CTOF_DEL --- 0.371 R14C2A.B1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 2.616 R14C2A.F1 to R8C8D.A0 RTAVR/rd_romdup CTOF_DEL --- 0.371 R8C8D.A0 to R8C8D.F0 RTAVR/ROM/SLICE_283 ROUTE 1 0.000 R8C8D.F0 to R8C8D.DI0 RTAVR/ROM/fb_10 (to CLK_OUT) -------- 9.396 (18.4% logic, 81.6% route), 4 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/S1/SLICE_125: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R10C11D.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_283: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R8C8D.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Error: The following path exceeds requirements by 6.105ns (weighted slack = -249.308ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_cmd_load (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_15 (to CLK_OUT -) Delay: 9.396ns (18.4% logic, 81.6% route), 4 logic levels. Constraint Details: 9.396ns physical path delay RTAVR/S1/SLICE_125 to RTAVR/ROM/SLICE_283 exceeds (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) 0.049ns delay constraint less -3.416ns skew and 0.174ns DIN_SET requirement (totaling 3.291ns) by 6.105ns Physical Path Details: Data path RTAVR/S1/SLICE_125 to RTAVR/ROM/SLICE_283: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.613 R10C11D.CLK to R10C11D.Q0 RTAVR/S1/SLICE_125 (from CLK_INT_inferred_clock) ROUTE 28 2.085 R10C11D.Q0 to R15C5C.C1 RTAVR/CMD_LOAD CTOF_DEL --- 0.371 R15C5C.C1 to R15C5C.F1 SLICE_104 ROUTE 2 2.969 R15C5C.F1 to R14C2A.B1 RTAVR/un1_CMD_LOAD_2dup CTOF_DEL --- 0.371 R14C2A.B1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 2.616 R14C2A.F1 to R8C8D.A1 RTAVR/rd_romdup CTOF_DEL --- 0.371 R8C8D.A1 to R8C8D.F1 RTAVR/ROM/SLICE_283 ROUTE 1 0.000 R8C8D.F1 to R8C8D.DI1 RTAVR/ROM/fb_9 (to CLK_OUT) -------- 9.396 (18.4% logic, 81.6% route), 4 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/S1/SLICE_125: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R10C11D.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_283: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R8C8D.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Error: The following path exceeds requirements by 6.046ns (weighted slack = -246.898ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_ea_13 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_14 (to CLK_OUT -) Delay: 9.337ns (22.5% logic, 77.5% route), 5 logic levels. Constraint Details: 9.337ns physical path delay RTAVR/SLICE_315 to RTAVR/ROM/SLICE_283 exceeds (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) 0.049ns delay constraint less -3.416ns skew and 0.174ns DIN_SET requirement (totaling 3.291ns) by 6.046ns Physical Path Details: Data path RTAVR/SLICE_315 to RTAVR/ROM/SLICE_283: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.613 R12C13D.CLK to R12C13D.Q1 RTAVR/SLICE_315 (from CLK_INT_inferred_clock) ROUTE 1 2.607 R12C13D.Q1 to R15C3B.A1 RTAVR/S1_EA_13 CTOF_DEL --- 0.371 R15C3B.A1 to R15C3B.F1 RTAVR/SLICE_424 ROUTE 2 0.513 R15C3B.F1 to R15C3B.C0 RTAVR/EA_13 CTOF_DEL --- 0.371 R15C3B.C0 to R15C3B.F0 RTAVR/SLICE_424 ROUTE 3 1.504 R15C3B.F0 to R14C2A.A1 RTAVR/oe_rom_0 CTOF_DEL --- 0.371 R14C2A.A1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 2.616 R14C2A.F1 to R8C8D.A0 RTAVR/rd_romdup CTOF_DEL --- 0.371 R8C8D.A0 to R8C8D.F0 RTAVR/ROM/SLICE_283 ROUTE 1 0.000 R8C8D.F0 to R8C8D.DI0 RTAVR/ROM/fb_10 (to CLK_OUT) -------- 9.337 (22.5% logic, 77.5% route), 5 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/SLICE_315: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R12C13D.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_283: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R8C8D.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Error: The following path exceeds requirements by 6.046ns (weighted slack = -246.898ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_ea_13 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_15 (to CLK_OUT -) Delay: 9.337ns (22.5% logic, 77.5% route), 5 logic levels. Constraint Details: 9.337ns physical path delay RTAVR/SLICE_315 to RTAVR/ROM/SLICE_283 exceeds (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) 0.049ns delay constraint less -3.416ns skew and 0.174ns DIN_SET requirement (totaling 3.291ns) by 6.046ns Physical Path Details: Data path RTAVR/SLICE_315 to RTAVR/ROM/SLICE_283: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.613 R12C13D.CLK to R12C13D.Q1 RTAVR/SLICE_315 (from CLK_INT_inferred_clock) ROUTE 1 2.607 R12C13D.Q1 to R15C3B.A1 RTAVR/S1_EA_13 CTOF_DEL --- 0.371 R15C3B.A1 to R15C3B.F1 RTAVR/SLICE_424 ROUTE 2 0.513 R15C3B.F1 to R15C3B.C0 RTAVR/EA_13 CTOF_DEL --- 0.371 R15C3B.C0 to R15C3B.F0 RTAVR/SLICE_424 ROUTE 3 1.504 R15C3B.F0 to R14C2A.A1 RTAVR/oe_rom_0 CTOF_DEL --- 0.371 R14C2A.A1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 2.616 R14C2A.F1 to R8C8D.A1 RTAVR/rd_romdup CTOF_DEL --- 0.371 R8C8D.A1 to R8C8D.F1 RTAVR/ROM/SLICE_283 ROUTE 1 0.000 R8C8D.F1 to R8C8D.DI1 RTAVR/ROM/fb_9 (to CLK_OUT) -------- 9.337 (22.5% logic, 77.5% route), 5 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/SLICE_315: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R12C13D.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_283: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R8C8D.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Warning: 3.689MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "CLK_INT_inferred_clock" 100.929000 MHz ; 4096 items scored, 4096 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 24.670ns (weighted slack = -125.207ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/ROM/DOA_2 (from CLK_OUT -) Destination: FF Data in RTAVR/S0/s1_postinc (to CLK_INT_inferred_clock -) Delay: 23.032ns (16.5% logic, 83.5% route), 9 logic levels. Constraint Details: 23.032ns physical path delay RTAVR/ROM/SLICE_277 to RTAVR/S0/SLICE_174 exceeds (delay constraint based on source clock period of 2.000ns and destination clock period of 9.907ns) 1.952ns delay constraint less 3.416ns skew and 0.174ns DIN_SET requirement (totaling -1.638ns) by 24.670ns Physical Path Details: Data path RTAVR/ROM/SLICE_277 to RTAVR/S0/SLICE_174: Name Fanout Delay (ns) Site Resource LTCH_DEL --- 0.840 R9C4C.CLK to R9C4C.Q0 RTAVR/ROM/SLICE_277 (from CLK_OUT) ROUTE 9 3.504 R9C4C.Q0 to R11C12D.B0 RTAVR/ROM_DOA_2 CTOF_DEL --- 0.371 R11C12D.B0 to R11C12D.F0 RTAVR/SLICE_335 ROUTE 1 2.500 R11C12D.F0 to R8C11C.B1 RTAVR/S0/v_xreg_0 CTOF_DEL --- 0.371 R8C11C.B1 to R8C11C.F1 RTAVR/S0/SLICE_408 ROUTE 5 1.991 R8C11C.F1 to R7C11D.A1 RTAVR/v_xreg CTOF_DEL --- 0.371 R7C11D.A1 to R7C11D.F1 RTAVR/SLICE_442 ROUTE 1 0.626 R7C11D.F1 to R7C11D.D0 RTAVR/un5_IDX_INST CTOF_DEL --- 0.371 R7C11D.D0 to R7C11D.F0 RTAVR/SLICE_442 ROUTE 1 2.871 R7C11D.F0 to R7C11B.A1 RTAVR/S1/un1_S0_WB_INST_1 CTOF_DEL --- 0.371 R7C11B.A1 to R7C11B.F1 RTAVR/S1/SLICE_406 ROUTE 3 1.513 R7C11B.F1 to R10C11C.A0 RTAVR/S1/un1_S0_WB_INST_0 CTOF_DEL --- 0.371 R10C11C.A0 to R10C11C.F0 RTAVR/S1/SLICE_437 ROUTE 2 2.418 R10C11C.F0 to R8C11D.A1 RTAVR/S1/un1_S0_VALID_0 CTOF_DEL --- 0.371 R8C11D.A1 to R8C11D.F1 RTAVR/SLICE_175 ROUTE 2 3.801 R8C11D.F1 to R8C11B.A0 RTAVR/S0_VALID CTOF_DEL --- 0.371 R8C11B.A0 to R8C11B.F0 RTAVR/S0/SLICE_174 ROUTE 1 0.000 R8C11B.F0 to R8C11B.DI0 RTAVR/S0/s1_postinc_2 (to CLK_INT_inferred_clock) -------- 23.032 (16.5% logic, 83.5% route), 9 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R9C4C.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Destination Clock Path osc_internal to RTAVR/S0/SLICE_174: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R8C11B.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 24.544ns (weighted slack = -124.568ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/ROM/DOA_15 (from CLK_OUT -) Destination: FF Data in RTAVR/S0/s1_postinc (to CLK_INT_inferred_clock -) Delay: 22.906ns (18.2% logic, 81.8% route), 10 logic levels. Constraint Details: 22.906ns physical path delay RTAVR/ROM/SLICE_283 to RTAVR/S0/SLICE_174 exceeds (delay constraint based on source clock period of 2.000ns and destination clock period of 9.907ns) 1.952ns delay constraint less 3.416ns skew and 0.174ns DIN_SET requirement (totaling -1.638ns) by 24.544ns Physical Path Details: Data path RTAVR/ROM/SLICE_283 to RTAVR/S0/SLICE_174: Name Fanout Delay (ns) Site Resource LTCH_DEL --- 0.840 R8C8D.CLK to R8C8D.Q1 RTAVR/ROM/SLICE_283 (from CLK_OUT) ROUTE 13 2.390 R8C8D.Q1 to R7C11C.C1 RTAVR/ROM_DOA_15 CTOF_DEL --- 0.371 R7C11C.C1 to R7C11C.F1 RTAVR/S0/SLICE_604 ROUTE 1 2.767 R7C11C.F1 to R8C11B.A1 RTAVR/S0/f_sbix_2 CTOF_DEL --- 0.371 R8C11B.A1 to R8C11B.F1 RTAVR/S0/SLICE_174 ROUTE 8 0.350 R8C11B.F1 to R8C11C.D1 RTAVR/un1_PM_OUT_3 CTOF_DEL --- 0.371 R8C11C.D1 to R8C11C.F1 RTAVR/S0/SLICE_408 ROUTE 5 1.991 R8C11C.F1 to R7C11D.A1 RTAVR/v_xreg CTOF_DEL --- 0.371 R7C11D.A1 to R7C11D.F1 RTAVR/SLICE_442 ROUTE 1 0.626 R7C11D.F1 to R7C11D.D0 RTAVR/un5_IDX_INST CTOF_DEL --- 0.371 R7C11D.D0 to R7C11D.F0 RTAVR/SLICE_442 ROUTE 1 2.871 R7C11D.F0 to R7C11B.A1 RTAVR/S1/un1_S0_WB_INST_1 CTOF_DEL --- 0.371 R7C11B.A1 to R7C11B.F1 RTAVR/S1/SLICE_406 ROUTE 3 1.513 R7C11B.F1 to R10C11C.A0 RTAVR/S1/un1_S0_WB_INST_0 CTOF_DEL --- 0.371 R10C11C.A0 to R10C11C.F0 RTAVR/S1/SLICE_437 ROUTE 2 2.418 R10C11C.F0 to R8C11D.A1 RTAVR/S1/un1_S0_VALID_0 CTOF_DEL --- 0.371 R8C11D.A1 to R8C11D.F1 RTAVR/SLICE_175 ROUTE 2 3.801 R8C11D.F1 to R8C11B.A0 RTAVR/S0_VALID CTOF_DEL --- 0.371 R8C11B.A0 to R8C11B.F0 RTAVR/S0/SLICE_174 ROUTE 1 0.000 R8C11B.F0 to R8C11B.DI0 RTAVR/S0/s1_postinc_2 (to CLK_INT_inferred_clock) -------- 22.906 (18.2% logic, 81.8% route), 10 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/ROM/SLICE_283: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R8C8D.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Destination Clock Path osc_internal to RTAVR/S0/SLICE_174: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R8C11B.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 24.416ns (weighted slack = -123.918ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/ROM/DOA_3 (from CLK_OUT -) Destination: FF Data in RTAVR/S0/s1_postinc (to CLK_INT_inferred_clock -) Delay: 22.778ns (16.7% logic, 83.3% route), 9 logic levels. Constraint Details: 22.778ns physical path delay RTAVR/ROM/SLICE_277 to RTAVR/S0/SLICE_174 exceeds (delay constraint based on source clock period of 2.000ns and destination clock period of 9.907ns) 1.952ns delay constraint less 3.416ns skew and 0.174ns DIN_SET requirement (totaling -1.638ns) by 24.416ns Physical Path Details: Data path RTAVR/ROM/SLICE_277 to RTAVR/S0/SLICE_174: Name Fanout Delay (ns) Site Resource LTCH_DEL --- 0.840 R9C4C.CLK to R9C4C.Q1 RTAVR/ROM/SLICE_277 (from CLK_OUT) ROUTE 9 3.250 R9C4C.Q1 to R11C12D.C0 RTAVR/ROM_DOA_3 CTOF_DEL --- 0.371 R11C12D.C0 to R11C12D.F0 RTAVR/SLICE_335 ROUTE 1 2.500 R11C12D.F0 to R8C11C.B1 RTAVR/S0/v_xreg_0 CTOF_DEL --- 0.371 R8C11C.B1 to R8C11C.F1 RTAVR/S0/SLICE_408 ROUTE 5 1.991 R8C11C.F1 to R7C11D.A1 RTAVR/v_xreg CTOF_DEL --- 0.371 R7C11D.A1 to R7C11D.F1 RTAVR/SLICE_442 ROUTE 1 0.626 R7C11D.F1 to R7C11D.D0 RTAVR/un5_IDX_INST CTOF_DEL --- 0.371 R7C11D.D0 to R7C11D.F0 RTAVR/SLICE_442 ROUTE 1 2.871 R7C11D.F0 to R7C11B.A1 RTAVR/S1/un1_S0_WB_INST_1 CTOF_DEL --- 0.371 R7C11B.A1 to R7C11B.F1 RTAVR/S1/SLICE_406 ROUTE 3 1.513 R7C11B.F1 to R10C11C.A0 RTAVR/S1/un1_S0_WB_INST_0 CTOF_DEL --- 0.371 R10C11C.A0 to R10C11C.F0 RTAVR/S1/SLICE_437 ROUTE 2 2.418 R10C11C.F0 to R8C11D.A1 RTAVR/S1/un1_S0_VALID_0 CTOF_DEL --- 0.371 R8C11D.A1 to R8C11D.F1 RTAVR/SLICE_175 ROUTE 2 3.801 R8C11D.F1 to R8C11B.A0 RTAVR/S0_VALID CTOF_DEL --- 0.371 R8C11B.A0 to R8C11B.F0 RTAVR/S0/SLICE_174 ROUTE 1 0.000 R8C11B.F0 to R8C11B.DI0 RTAVR/S0/s1_postinc_2 (to CLK_INT_inferred_clock) -------- 22.778 (16.7% logic, 83.3% route), 9 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R9C4C.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Destination Clock Path osc_internal to RTAVR/S0/SLICE_174: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R8C11B.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 24.282ns (weighted slack = -123.238ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/ROM/DOA_12 (from CLK_OUT -) Destination: FF Data in RTAVR/S0/s1_postinc (to CLK_INT_inferred_clock -) Delay: 22.644ns (18.5% logic, 81.5% route), 10 logic levels. Constraint Details: 22.644ns physical path delay RTAVR/ROM/SLICE_282 to RTAVR/S0/SLICE_174 exceeds (delay constraint based on source clock period of 2.000ns and destination clock period of 9.907ns) 1.952ns delay constraint less 3.416ns skew and 0.174ns DIN_SET requirement (totaling -1.638ns) by 24.282ns Physical Path Details: Data path RTAVR/ROM/SLICE_282 to RTAVR/S0/SLICE_174: Name Fanout Delay (ns) Site Resource LTCH_DEL --- 0.840 R8C4D.CLK to R8C4D.Q0 RTAVR/ROM/SLICE_282 (from CLK_OUT) ROUTE 7 2.128 R8C4D.Q0 to R7C11C.D1 RTAVR/ROM_DOA_12 CTOF_DEL --- 0.371 R7C11C.D1 to R7C11C.F1 RTAVR/S0/SLICE_604 ROUTE 1 2.767 R7C11C.F1 to R8C11B.A1 RTAVR/S0/f_sbix_2 CTOF_DEL --- 0.371 R8C11B.A1 to R8C11B.F1 RTAVR/S0/SLICE_174 ROUTE 8 0.350 R8C11B.F1 to R8C11C.D1 RTAVR/un1_PM_OUT_3 CTOF_DEL --- 0.371 R8C11C.D1 to R8C11C.F1 RTAVR/S0/SLICE_408 ROUTE 5 1.991 R8C11C.F1 to R7C11D.A1 RTAVR/v_xreg CTOF_DEL --- 0.371 R7C11D.A1 to R7C11D.F1 RTAVR/SLICE_442 ROUTE 1 0.626 R7C11D.F1 to R7C11D.D0 RTAVR/un5_IDX_INST CTOF_DEL --- 0.371 R7C11D.D0 to R7C11D.F0 RTAVR/SLICE_442 ROUTE 1 2.871 R7C11D.F0 to R7C11B.A1 RTAVR/S1/un1_S0_WB_INST_1 CTOF_DEL --- 0.371 R7C11B.A1 to R7C11B.F1 RTAVR/S1/SLICE_406 ROUTE 3 1.513 R7C11B.F1 to R10C11C.A0 RTAVR/S1/un1_S0_WB_INST_0 CTOF_DEL --- 0.371 R10C11C.A0 to R10C11C.F0 RTAVR/S1/SLICE_437 ROUTE 2 2.418 R10C11C.F0 to R8C11D.A1 RTAVR/S1/un1_S0_VALID_0 CTOF_DEL --- 0.371 R8C11D.A1 to R8C11D.F1 RTAVR/SLICE_175 ROUTE 2 3.801 R8C11D.F1 to R8C11B.A0 RTAVR/S0_VALID CTOF_DEL --- 0.371 R8C11B.A0 to R8C11B.F0 RTAVR/S0/SLICE_174 ROUTE 1 0.000 R8C11B.F0 to R8C11B.DI0 RTAVR/S0/s1_postinc_2 (to CLK_INT_inferred_clock) -------- 22.644 (18.5% logic, 81.5% route), 10 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/ROM/SLICE_282: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R8C4D.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Destination Clock Path osc_internal to RTAVR/S0/SLICE_174: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R8C11B.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 23.735ns (weighted slack = -120.462ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/ROM/DOA_15 (from CLK_OUT -) Destination: FF Data in RTAVR/S0/s1_postinc (to CLK_INT_inferred_clock -) Delay: 22.097ns (15.6% logic, 84.4% route), 8 logic levels. Constraint Details: 22.097ns physical path delay RTAVR/ROM/SLICE_283 to RTAVR/S0/SLICE_174 exceeds (delay constraint based on source clock period of 2.000ns and destination clock period of 9.907ns) 1.952ns delay constraint less 3.416ns skew and 0.174ns DIN_SET requirement (totaling -1.638ns) by 23.735ns Physical Path Details: Data path RTAVR/ROM/SLICE_283 to RTAVR/S0/SLICE_174: Name Fanout Delay (ns) Site Resource LTCH_DEL --- 0.840 R8C8D.CLK to R8C8D.Q1 RTAVR/ROM/SLICE_283 (from CLK_OUT) ROUTE 13 2.390 R8C8D.Q1 to R7C11C.C1 RTAVR/ROM_DOA_15 CTOF_DEL --- 0.371 R7C11C.C1 to R7C11C.F1 RTAVR/S0/SLICE_604 ROUTE 1 2.767 R7C11C.F1 to R8C11B.A1 RTAVR/S0/f_sbix_2 CTOF_DEL --- 0.371 R8C11B.A1 to R8C11B.F1 RTAVR/S0/SLICE_174 ROUTE 8 2.900 R8C11B.F1 to R7C11D.B0 RTAVR/un1_PM_OUT_3 CTOF_DEL --- 0.371 R7C11D.B0 to R7C11D.F0 RTAVR/SLICE_442 ROUTE 1 2.871 R7C11D.F0 to R7C11B.A1 RTAVR/S1/un1_S0_WB_INST_1 CTOF_DEL --- 0.371 R7C11B.A1 to R7C11B.F1 RTAVR/S1/SLICE_406 ROUTE 3 1.513 R7C11B.F1 to R10C11C.A0 RTAVR/S1/un1_S0_WB_INST_0 CTOF_DEL --- 0.371 R10C11C.A0 to R10C11C.F0 RTAVR/S1/SLICE_437 ROUTE 2 2.418 R10C11C.F0 to R8C11D.A1 RTAVR/S1/un1_S0_VALID_0 CTOF_DEL --- 0.371 R8C11D.A1 to R8C11D.F1 RTAVR/SLICE_175 ROUTE 2 3.801 R8C11D.F1 to R8C11B.A0 RTAVR/S0_VALID CTOF_DEL --- 0.371 R8C11B.A0 to R8C11B.F0 RTAVR/S0/SLICE_174 ROUTE 1 0.000 R8C11B.F0 to R8C11B.DI0 RTAVR/S0/s1_postinc_2 (to CLK_INT_inferred_clock) -------- 22.097 (15.6% logic, 84.4% route), 8 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/ROM/SLICE_283: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R8C8D.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Destination Clock Path osc_internal to RTAVR/S0/SLICE_174: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R8C11B.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 23.473ns (weighted slack = -119.132ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/ROM/DOA_12 (from CLK_OUT -) Destination: FF Data in RTAVR/S0/s1_postinc (to CLK_INT_inferred_clock -) Delay: 21.835ns (15.7% logic, 84.3% route), 8 logic levels. Constraint Details: 21.835ns physical path delay RTAVR/ROM/SLICE_282 to RTAVR/S0/SLICE_174 exceeds (delay constraint based on source clock period of 2.000ns and destination clock period of 9.907ns) 1.952ns delay constraint less 3.416ns skew and 0.174ns DIN_SET requirement (totaling -1.638ns) by 23.473ns Physical Path Details: Data path RTAVR/ROM/SLICE_282 to RTAVR/S0/SLICE_174: Name Fanout Delay (ns) Site Resource LTCH_DEL --- 0.840 R8C4D.CLK to R8C4D.Q0 RTAVR/ROM/SLICE_282 (from CLK_OUT) ROUTE 7 2.128 R8C4D.Q0 to R7C11C.D1 RTAVR/ROM_DOA_12 CTOF_DEL --- 0.371 R7C11C.D1 to R7C11C.F1 RTAVR/S0/SLICE_604 ROUTE 1 2.767 R7C11C.F1 to R8C11B.A1 RTAVR/S0/f_sbix_2 CTOF_DEL --- 0.371 R8C11B.A1 to R8C11B.F1 RTAVR/S0/SLICE_174 ROUTE 8 2.900 R8C11B.F1 to R7C11D.B0 RTAVR/un1_PM_OUT_3 CTOF_DEL --- 0.371 R7C11D.B0 to R7C11D.F0 RTAVR/SLICE_442 ROUTE 1 2.871 R7C11D.F0 to R7C11B.A1 RTAVR/S1/un1_S0_WB_INST_1 CTOF_DEL --- 0.371 R7C11B.A1 to R7C11B.F1 RTAVR/S1/SLICE_406 ROUTE 3 1.513 R7C11B.F1 to R10C11C.A0 RTAVR/S1/un1_S0_WB_INST_0 CTOF_DEL --- 0.371 R10C11C.A0 to R10C11C.F0 RTAVR/S1/SLICE_437 ROUTE 2 2.418 R10C11C.F0 to R8C11D.A1 RTAVR/S1/un1_S0_VALID_0 CTOF_DEL --- 0.371 R8C11D.A1 to R8C11D.F1 RTAVR/SLICE_175 ROUTE 2 3.801 R8C11D.F1 to R8C11B.A0 RTAVR/S0_VALID CTOF_DEL --- 0.371 R8C11B.A0 to R8C11B.F0 RTAVR/S0/SLICE_174 ROUTE 1 0.000 R8C11B.F0 to R8C11B.DI0 RTAVR/S0/s1_postinc_2 (to CLK_INT_inferred_clock) -------- 21.835 (15.7% logic, 84.3% route), 8 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/ROM/SLICE_282: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R8C4D.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Destination Clock Path osc_internal to RTAVR/S0/SLICE_174: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R8C11B.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 22.982ns (weighted slack = -116.640ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/ROM/DOA_2 (from CLK_OUT -) Destination: FF Data in RTAVR/S1/r_pc_4 (to CLK_INT_inferred_clock -) Delay: 21.253ns (16.2% logic, 83.8% route), 8 logic levels. Constraint Details: 21.253ns physical path delay RTAVR/ROM/SLICE_277 to RTAVR/S1/SLICE_260 exceeds (delay constraint based on source clock period of 2.000ns and destination clock period of 9.907ns) 1.952ns delay constraint less 3.416ns skew and 0.265ns CE_SET requirement (totaling -1.729ns) by 22.982ns Physical Path Details: Data path RTAVR/ROM/SLICE_277 to RTAVR/S1/SLICE_260: Name Fanout Delay (ns) Site Resource LTCH_DEL --- 0.840 R9C4C.CLK to R9C4C.Q0 RTAVR/ROM/SLICE_277 (from CLK_OUT) ROUTE 9 3.504 R9C4C.Q0 to R11C12D.B0 RTAVR/ROM_DOA_2 CTOF_DEL --- 0.371 R11C12D.B0 to R11C12D.F0 RTAVR/SLICE_335 ROUTE 1 2.500 R11C12D.F0 to R8C11C.B1 RTAVR/S0/v_xreg_0 CTOF_DEL --- 0.371 R8C11C.B1 to R8C11C.F1 RTAVR/S0/SLICE_408 ROUTE 5 1.991 R8C11C.F1 to R7C11D.A1 RTAVR/v_xreg CTOF_DEL --- 0.371 R7C11D.A1 to R7C11D.F1 RTAVR/SLICE_442 ROUTE 1 0.626 R7C11D.F1 to R7C11D.D0 RTAVR/un5_IDX_INST CTOF_DEL --- 0.371 R7C11D.D0 to R7C11D.F0 RTAVR/SLICE_442 ROUTE 1 2.871 R7C11D.F0 to R7C11B.A1 RTAVR/S1/un1_S0_WB_INST_1 CTOF_DEL --- 0.371 R7C11B.A1 to R7C11B.F1 RTAVR/S1/SLICE_406 ROUTE 3 1.374 R7C11B.F1 to R10C11A.C1 RTAVR/S1/un1_S0_WB_INST_0 CTOF_DEL --- 0.371 R10C11A.C1 to R10C11A.F1 RTAVR/S1/SLICE_292 ROUTE 1 2.897 R10C11A.F1 to R12C10D.D1 RTAVR/S1/un1_s0_inv_conflict_0 CTOF_DEL --- 0.371 R12C10D.D1 to R12C10D.F1 RTAVR/S1/SLICE_567 ROUTE 12 2.053 R12C10D.F1 to R13C10A.CE RTAVR/S1/un1_n_reset7_0 (to CLK_INT_inferred_clock) -------- 21.253 (16.2% logic, 83.8% route), 8 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R9C4C.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Destination Clock Path osc_internal to RTAVR/S1/SLICE_260: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R13C10A.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 22.976ns (weighted slack = -116.610ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/ROM/DOA_2 (from CLK_OUT -) Destination: FF Data in RTAVR/S1/r_pc_0 (to CLK_INT_inferred_clock -) Delay: 21.247ns (16.2% logic, 83.8% route), 8 logic levels. Constraint Details: 21.247ns physical path delay RTAVR/ROM/SLICE_277 to RTAVR/S1/SLICE_256 exceeds (delay constraint based on source clock period of 2.000ns and destination clock period of 9.907ns) 1.952ns delay constraint less 3.416ns skew and 0.265ns CE_SET requirement (totaling -1.729ns) by 22.976ns Physical Path Details: Data path RTAVR/ROM/SLICE_277 to RTAVR/S1/SLICE_256: Name Fanout Delay (ns) Site Resource LTCH_DEL --- 0.840 R9C4C.CLK to R9C4C.Q0 RTAVR/ROM/SLICE_277 (from CLK_OUT) ROUTE 9 3.504 R9C4C.Q0 to R11C12D.B0 RTAVR/ROM_DOA_2 CTOF_DEL --- 0.371 R11C12D.B0 to R11C12D.F0 RTAVR/SLICE_335 ROUTE 1 2.500 R11C12D.F0 to R8C11C.B1 RTAVR/S0/v_xreg_0 CTOF_DEL --- 0.371 R8C11C.B1 to R8C11C.F1 RTAVR/S0/SLICE_408 ROUTE 5 1.991 R8C11C.F1 to R7C11D.A1 RTAVR/v_xreg CTOF_DEL --- 0.371 R7C11D.A1 to R7C11D.F1 RTAVR/SLICE_442 ROUTE 1 0.626 R7C11D.F1 to R7C11D.D0 RTAVR/un5_IDX_INST CTOF_DEL --- 0.371 R7C11D.D0 to R7C11D.F0 RTAVR/SLICE_442 ROUTE 1 2.871 R7C11D.F0 to R7C11B.A1 RTAVR/S1/un1_S0_WB_INST_1 CTOF_DEL --- 0.371 R7C11B.A1 to R7C11B.F1 RTAVR/S1/SLICE_406 ROUTE 3 1.374 R7C11B.F1 to R10C11A.C1 RTAVR/S1/un1_S0_WB_INST_0 CTOF_DEL --- 0.371 R10C11A.C1 to R10C11A.F1 RTAVR/S1/SLICE_292 ROUTE 1 2.897 R10C11A.F1 to R12C10D.D1 RTAVR/S1/un1_s0_inv_conflict_0 CTOF_DEL --- 0.371 R12C10D.D1 to R12C10D.F1 RTAVR/S1/SLICE_567 ROUTE 12 2.047 R12C10D.F1 to R10C9D.CE RTAVR/S1/un1_n_reset7_0 (to CLK_INT_inferred_clock) -------- 21.247 (16.2% logic, 83.8% route), 8 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/ROM/SLICE_277: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R9C4C.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Destination Clock Path osc_internal to RTAVR/S1/SLICE_256: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R10C9D.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 22.856ns (weighted slack = -116.001ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/ROM/DOA_15 (from CLK_OUT -) Destination: FF Data in RTAVR/S1/r_pc_4 (to CLK_INT_inferred_clock -) Delay: 21.127ns (18.0% logic, 82.0% route), 9 logic levels. Constraint Details: 21.127ns physical path delay RTAVR/ROM/SLICE_283 to RTAVR/S1/SLICE_260 exceeds (delay constraint based on source clock period of 2.000ns and destination clock period of 9.907ns) 1.952ns delay constraint less 3.416ns skew and 0.265ns CE_SET requirement (totaling -1.729ns) by 22.856ns Physical Path Details: Data path RTAVR/ROM/SLICE_283 to RTAVR/S1/SLICE_260: Name Fanout Delay (ns) Site Resource LTCH_DEL --- 0.840 R8C8D.CLK to R8C8D.Q1 RTAVR/ROM/SLICE_283 (from CLK_OUT) ROUTE 13 2.390 R8C8D.Q1 to R7C11C.C1 RTAVR/ROM_DOA_15 CTOF_DEL --- 0.371 R7C11C.C1 to R7C11C.F1 RTAVR/S0/SLICE_604 ROUTE 1 2.767 R7C11C.F1 to R8C11B.A1 RTAVR/S0/f_sbix_2 CTOF_DEL --- 0.371 R8C11B.A1 to R8C11B.F1 RTAVR/S0/SLICE_174 ROUTE 8 0.350 R8C11B.F1 to R8C11C.D1 RTAVR/un1_PM_OUT_3 CTOF_DEL --- 0.371 R8C11C.D1 to R8C11C.F1 RTAVR/S0/SLICE_408 ROUTE 5 1.991 R8C11C.F1 to R7C11D.A1 RTAVR/v_xreg CTOF_DEL --- 0.371 R7C11D.A1 to R7C11D.F1 RTAVR/SLICE_442 ROUTE 1 0.626 R7C11D.F1 to R7C11D.D0 RTAVR/un5_IDX_INST CTOF_DEL --- 0.371 R7C11D.D0 to R7C11D.F0 RTAVR/SLICE_442 ROUTE 1 2.871 R7C11D.F0 to R7C11B.A1 RTAVR/S1/un1_S0_WB_INST_1 CTOF_DEL --- 0.371 R7C11B.A1 to R7C11B.F1 RTAVR/S1/SLICE_406 ROUTE 3 1.374 R7C11B.F1 to R10C11A.C1 RTAVR/S1/un1_S0_WB_INST_0 CTOF_DEL --- 0.371 R10C11A.C1 to R10C11A.F1 RTAVR/S1/SLICE_292 ROUTE 1 2.897 R10C11A.F1 to R12C10D.D1 RTAVR/S1/un1_s0_inv_conflict_0 CTOF_DEL --- 0.371 R12C10D.D1 to R12C10D.F1 RTAVR/S1/SLICE_567 ROUTE 12 2.053 R12C10D.F1 to R13C10A.CE RTAVR/S1/un1_n_reset7_0 (to CLK_INT_inferred_clock) -------- 21.127 (18.0% logic, 82.0% route), 9 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/ROM/SLICE_283: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R8C8D.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Destination Clock Path osc_internal to RTAVR/S1/SLICE_260: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R13C10A.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 22.850ns (weighted slack = -115.970ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/ROM/DOA_15 (from CLK_OUT -) Destination: FF Data in RTAVR/S1/r_pc_0 (to CLK_INT_inferred_clock -) Delay: 21.121ns (18.0% logic, 82.0% route), 9 logic levels. Constraint Details: 21.121ns physical path delay RTAVR/ROM/SLICE_283 to RTAVR/S1/SLICE_256 exceeds (delay constraint based on source clock period of 2.000ns and destination clock period of 9.907ns) 1.952ns delay constraint less 3.416ns skew and 0.265ns CE_SET requirement (totaling -1.729ns) by 22.850ns Physical Path Details: Data path RTAVR/ROM/SLICE_283 to RTAVR/S1/SLICE_256: Name Fanout Delay (ns) Site Resource LTCH_DEL --- 0.840 R8C8D.CLK to R8C8D.Q1 RTAVR/ROM/SLICE_283 (from CLK_OUT) ROUTE 13 2.390 R8C8D.Q1 to R7C11C.C1 RTAVR/ROM_DOA_15 CTOF_DEL --- 0.371 R7C11C.C1 to R7C11C.F1 RTAVR/S0/SLICE_604 ROUTE 1 2.767 R7C11C.F1 to R8C11B.A1 RTAVR/S0/f_sbix_2 CTOF_DEL --- 0.371 R8C11B.A1 to R8C11B.F1 RTAVR/S0/SLICE_174 ROUTE 8 0.350 R8C11B.F1 to R8C11C.D1 RTAVR/un1_PM_OUT_3 CTOF_DEL --- 0.371 R8C11C.D1 to R8C11C.F1 RTAVR/S0/SLICE_408 ROUTE 5 1.991 R8C11C.F1 to R7C11D.A1 RTAVR/v_xreg CTOF_DEL --- 0.371 R7C11D.A1 to R7C11D.F1 RTAVR/SLICE_442 ROUTE 1 0.626 R7C11D.F1 to R7C11D.D0 RTAVR/un5_IDX_INST CTOF_DEL --- 0.371 R7C11D.D0 to R7C11D.F0 RTAVR/SLICE_442 ROUTE 1 2.871 R7C11D.F0 to R7C11B.A1 RTAVR/S1/un1_S0_WB_INST_1 CTOF_DEL --- 0.371 R7C11B.A1 to R7C11B.F1 RTAVR/S1/SLICE_406 ROUTE 3 1.374 R7C11B.F1 to R10C11A.C1 RTAVR/S1/un1_S0_WB_INST_0 CTOF_DEL --- 0.371 R10C11A.C1 to R10C11A.F1 RTAVR/S1/SLICE_292 ROUTE 1 2.897 R10C11A.F1 to R12C10D.D1 RTAVR/S1/un1_s0_inv_conflict_0 CTOF_DEL --- 0.371 R12C10D.D1 to R12C10D.F1 RTAVR/S1/SLICE_567 ROUTE 12 2.047 R12C10D.F1 to R10C9D.CE RTAVR/S1/un1_n_reset7_0 (to CLK_INT_inferred_clock) -------- 21.121 (18.0% logic, 82.0% route), 9 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/ROM/SLICE_283: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.613 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 2.803 R14C2C.Q0 to R8C8D.CLK CLK_OUT -------- 6.425 (9.5% logic, 90.5% route), 1 logic levels. Destination Clock Path osc_internal to RTAVR/S1/SLICE_256: Name Fanout Delay (ns) Site Resource ROUTE 274 3.009 OSC.OSC to R10C9D.CLK CLK_INT_inferred_clock -------- 3.009 (0.0% logic, 100.0% route), 0 logic levels. Warning: 7.402MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "CLK_OUT" 499.750000 MHz | | | ; | 499.750 MHz| 3.689 MHz| 4 * | | | FREQUENCY NET "CLK_INT_inferred_clock" | | | 100.929000 MHz ; | 100.929 MHz| 7.402 MHz| 9 * | | | ---------------------------------------------------------------------------- 2 preferences(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- RTAVR/Z_out_0 | 2| 942| 22.13% | | | RTAVR/Z_out_a | 1| 941| 22.11% | | | RTAVR/ALU/N_402 | 3| 909| 21.36% | | | RTAVR/IOR/IOR_PS0/r_sreg_5_1 | 1| 816| 19.17% | | | RTAVR/IOR/IOR_PS0/un33_DO_async | 7| 728| 17.11% | | | RTAVR/S1/un1_S0_WB_INST_0 | 3| 672| 15.79% | | | RTAVR/ALU/un1_WC_cry_3 | 1| 653| 15.34% | | | RTAVR/S1/un1_n_reset7_0 | 12| 603| 14.17% | | | RTAVR/IOR/IOR_PS0/un52_DO_async | 6| 591| 13.89% | | | RTAVR/IOR/N_321 | 1| 573| 13.46% | | | RTAVR/IOR/DO_async_1_0 | 1| 573| 13.46% | | | RTAVR/IOR/DO_0_0 | 1| 573| 13.46% | | | RTAVR/un1_PM_OUT_3 | 8| 545| 12.81% | | | RTAVR/ALU/un1_WC_cry_1 | 1| 542| 12.73% | | | RTAVR/ALU_OUT_7 | 4| 528| 12.41% | | | RTAVR/rd_iordup | 17| 524| 12.31% | | | RTAVR/IOR/IOR_PS0/un80_DO_async | 4| 522| 12.27% | | | RTAVR/oe_ior | 20| 519| 12.19% | | | RTAVR/S1/un1_s0_inv_conflict_0 | 1| 504| 11.84% | | | RTAVR/ALU/un1_WC_1_cry_6_0_S1 | 1| 491| 11.54% | | | RTAVR/ALU/un23_Z_out_4 | 1| 490| 11.51% | | | RTAVR/IOR/IOR_PS0/DO_0_iv_6_0 | 1| 473| 11.11% | | | RTAVR/V_out_0 | 3| 468| 11.00% | | | RTAVR/ALU_RR_0 | 1| 465| 10.93% | | | RTAVR/ALU/un1_A_5_cry_6_0_S1 | 2| 443| 10.41% | | | RTAVR/ALU/un23_Z_out_5 | 1| 438| 10.29% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: CLK_OUT Source: RTAVR/SLICE_538.Q0 Loads: 168 Covered under: FREQUENCY NET "CLK_OUT" 499.750000 MHz ; Data transfers from: Clock Domain: CLK_INT_inferred_clock Source: osc_internal.CFGCLK Covered under: FREQUENCY NET "CLK_OUT" 499.750000 MHz ; Transfers: 24 Clock Domain: CLK_INT_inferred_clock Source: osc_internal.CFGCLK Loads: 274 Covered under: FREQUENCY NET "CLK_INT_inferred_clock" 100.929000 MHz ; Data transfers from: Clock Domain: CLK_OUT Source: RTAVR/SLICE_538.Q0 Covered under: FREQUENCY NET "CLK_INT_inferred_clock" 100.929000 MHz ; Transfers: 16 Timing summary (Setup): --------------- Timing errors: 4256 Score: 207425080 Cumulative negative slack: 157683988 Constraints cover 876305 paths, 97 nets, and 5087 connections (99.9% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond_1.4_Production (87) Thu Feb 23 17:41:21 2012 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o MachXO_Breakout_rtavr_xo.twr MachXO_Breakout_rtavr_xo.ncd MachXO_Breakout_rtavr_xo.prf Design file: machxo_breakout_rtavr_xo.ncd Preference file: machxo_breakout_rtavr_xo.prf Device,speed: LCMXO2280C,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "CLK_OUT" 499.750000 MHz (0 errors)
  • 160 items scored, 0 timing errors detected.
  • FREQUENCY NET "CLK_INT_inferred_clock" 100.929000 MHz (0 errors)
  • 4096 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "CLK_OUT" 499.750000 MHz ; 160 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.385ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_ea_15 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_5 (to CLK_OUT -) Delay: 1.207ns (29.7% logic, 70.3% route), 4 logic levels. Constraint Details: 1.207ns physical path delay RTAVR/SLICE_316 to RTAVR/ROM/SLICE_278 meets (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) -0.019ns DIN_HLD and 0.000ns delay constraint less -0.841ns skew requirement (totaling 0.822ns) by 0.385ns Physical Path Details: Data path RTAVR/SLICE_316 to RTAVR/ROM/SLICE_278: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R14C7C.CLK to R14C7C.Q1 RTAVR/SLICE_316 (from CLK_INT_inferred_clock) ROUTE 3 0.267 R14C7C.Q1 to R14C2C.D1 RTAVR/S1_EA_15 CTOF_DEL --- 0.074 R14C2C.D1 to R14C2C.F1 RTAVR/SLICE_538 ROUTE 3 0.172 R14C2C.F1 to R14C2A.C1 RTAVR/EA_15 CTOF_DEL --- 0.074 R14C2A.C1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 0.409 R14C2A.F1 to R8C4C.C1 RTAVR/rd_romdup CTOF_DEL --- 0.074 R8C4C.C1 to R8C4C.F1 RTAVR/ROM/SLICE_278 ROUTE 1 0.000 R8C4C.F1 to R8C4C.DI1 RTAVR/ROM/fb_3 (to CLK_OUT) -------- 1.207 (29.7% logic, 70.3% route), 4 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/SLICE_316: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C7C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_278: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.150 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 0.691 R14C2C.Q0 to R8C4C.CLK CLK_OUT -------- 1.582 (9.5% logic, 90.5% route), 1 logic levels. Passed: The following path meets requirements by 0.385ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_ea_15 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_11 (to CLK_OUT -) Delay: 1.207ns (29.7% logic, 70.3% route), 4 logic levels. Constraint Details: 1.207ns physical path delay RTAVR/SLICE_316 to RTAVR/ROM/SLICE_281 meets (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) -0.019ns DIN_HLD and 0.000ns delay constraint less -0.841ns skew requirement (totaling 0.822ns) by 0.385ns Physical Path Details: Data path RTAVR/SLICE_316 to RTAVR/ROM/SLICE_281: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R14C7C.CLK to R14C7C.Q1 RTAVR/SLICE_316 (from CLK_INT_inferred_clock) ROUTE 3 0.267 R14C7C.Q1 to R14C2C.D1 RTAVR/S1_EA_15 CTOF_DEL --- 0.074 R14C2C.D1 to R14C2C.F1 RTAVR/SLICE_538 ROUTE 3 0.172 R14C2C.F1 to R14C2A.C1 RTAVR/EA_15 CTOF_DEL --- 0.074 R14C2A.C1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 0.409 R14C2A.F1 to R8C4A.C1 RTAVR/rd_romdup CTOF_DEL --- 0.074 R8C4A.C1 to R8C4A.F1 RTAVR/ROM/SLICE_281 ROUTE 1 0.000 R8C4A.F1 to R8C4A.DI1 RTAVR/ROM/fb_13 (to CLK_OUT) -------- 1.207 (29.7% logic, 70.3% route), 4 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/SLICE_316: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C7C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_281: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.150 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 0.691 R14C2C.Q0 to R8C4A.CLK CLK_OUT -------- 1.582 (9.5% logic, 90.5% route), 1 logic levels. Passed: The following path meets requirements by 0.385ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_ea_15 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_13 (to CLK_OUT -) Delay: 1.207ns (29.7% logic, 70.3% route), 4 logic levels. Constraint Details: 1.207ns physical path delay RTAVR/SLICE_316 to RTAVR/ROM/SLICE_282 meets (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) -0.019ns DIN_HLD and 0.000ns delay constraint less -0.841ns skew requirement (totaling 0.822ns) by 0.385ns Physical Path Details: Data path RTAVR/SLICE_316 to RTAVR/ROM/SLICE_282: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R14C7C.CLK to R14C7C.Q1 RTAVR/SLICE_316 (from CLK_INT_inferred_clock) ROUTE 3 0.267 R14C7C.Q1 to R14C2C.D1 RTAVR/S1_EA_15 CTOF_DEL --- 0.074 R14C2C.D1 to R14C2C.F1 RTAVR/SLICE_538 ROUTE 3 0.172 R14C2C.F1 to R14C2A.C1 RTAVR/EA_15 CTOF_DEL --- 0.074 R14C2A.C1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 0.409 R14C2A.F1 to R8C4D.C1 RTAVR/rd_romdup CTOF_DEL --- 0.074 R8C4D.C1 to R8C4D.F1 RTAVR/ROM/SLICE_282 ROUTE 1 0.000 R8C4D.F1 to R8C4D.DI1 RTAVR/ROM/fb_11 (to CLK_OUT) -------- 1.207 (29.7% logic, 70.3% route), 4 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/SLICE_316: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C7C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_282: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.150 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 0.691 R14C2C.Q0 to R8C4D.CLK CLK_OUT -------- 1.582 (9.5% logic, 90.5% route), 1 logic levels. Passed: The following path meets requirements by 0.385ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_ea_15 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_0 (to CLK_OUT -) Delay: 1.207ns (29.7% logic, 70.3% route), 4 logic levels. Constraint Details: 1.207ns physical path delay RTAVR/SLICE_316 to RTAVR/ROM/SLICE_276 meets (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) -0.019ns DIN_HLD and 0.000ns delay constraint less -0.841ns skew requirement (totaling 0.822ns) by 0.385ns Physical Path Details: Data path RTAVR/SLICE_316 to RTAVR/ROM/SLICE_276: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R14C7C.CLK to R14C7C.Q1 RTAVR/SLICE_316 (from CLK_INT_inferred_clock) ROUTE 3 0.267 R14C7C.Q1 to R14C2C.D1 RTAVR/S1_EA_15 CTOF_DEL --- 0.074 R14C2C.D1 to R14C2C.F1 RTAVR/SLICE_538 ROUTE 3 0.172 R14C2C.F1 to R14C2A.C1 RTAVR/EA_15 CTOF_DEL --- 0.074 R14C2A.C1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 0.409 R14C2A.F1 to R8C4B.C0 RTAVR/rd_romdup CTOF_DEL --- 0.074 R8C4B.C0 to R8C4B.F0 RTAVR/ROM/SLICE_276 ROUTE 1 0.000 R8C4B.F0 to R8C4B.DI0 RTAVR/ROM/fb_8 (to CLK_OUT) -------- 1.207 (29.7% logic, 70.3% route), 4 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/SLICE_316: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C7C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_276: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.150 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 0.691 R14C2C.Q0 to R8C4B.CLK CLK_OUT -------- 1.582 (9.5% logic, 90.5% route), 1 logic levels. Passed: The following path meets requirements by 0.385ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_ea_15 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_12 (to CLK_OUT -) Delay: 1.207ns (29.7% logic, 70.3% route), 4 logic levels. Constraint Details: 1.207ns physical path delay RTAVR/SLICE_316 to RTAVR/ROM/SLICE_282 meets (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) -0.019ns DIN_HLD and 0.000ns delay constraint less -0.841ns skew requirement (totaling 0.822ns) by 0.385ns Physical Path Details: Data path RTAVR/SLICE_316 to RTAVR/ROM/SLICE_282: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R14C7C.CLK to R14C7C.Q1 RTAVR/SLICE_316 (from CLK_INT_inferred_clock) ROUTE 3 0.267 R14C7C.Q1 to R14C2C.D1 RTAVR/S1_EA_15 CTOF_DEL --- 0.074 R14C2C.D1 to R14C2C.F1 RTAVR/SLICE_538 ROUTE 3 0.172 R14C2C.F1 to R14C2A.C1 RTAVR/EA_15 CTOF_DEL --- 0.074 R14C2A.C1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 0.409 R14C2A.F1 to R8C4D.C0 RTAVR/rd_romdup CTOF_DEL --- 0.074 R8C4D.C0 to R8C4D.F0 RTAVR/ROM/SLICE_282 ROUTE 1 0.000 R8C4D.F0 to R8C4D.DI0 RTAVR/ROM/fb_12 (to CLK_OUT) -------- 1.207 (29.7% logic, 70.3% route), 4 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/SLICE_316: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C7C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_282: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.150 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 0.691 R14C2C.Q0 to R8C4D.CLK CLK_OUT -------- 1.582 (9.5% logic, 90.5% route), 1 logic levels. Passed: The following path meets requirements by 0.385ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_ea_15 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_10 (to CLK_OUT -) Delay: 1.207ns (29.7% logic, 70.3% route), 4 logic levels. Constraint Details: 1.207ns physical path delay RTAVR/SLICE_316 to RTAVR/ROM/SLICE_281 meets (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) -0.019ns DIN_HLD and 0.000ns delay constraint less -0.841ns skew requirement (totaling 0.822ns) by 0.385ns Physical Path Details: Data path RTAVR/SLICE_316 to RTAVR/ROM/SLICE_281: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R14C7C.CLK to R14C7C.Q1 RTAVR/SLICE_316 (from CLK_INT_inferred_clock) ROUTE 3 0.267 R14C7C.Q1 to R14C2C.D1 RTAVR/S1_EA_15 CTOF_DEL --- 0.074 R14C2C.D1 to R14C2C.F1 RTAVR/SLICE_538 ROUTE 3 0.172 R14C2C.F1 to R14C2A.C1 RTAVR/EA_15 CTOF_DEL --- 0.074 R14C2A.C1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 0.409 R14C2A.F1 to R8C4A.C0 RTAVR/rd_romdup CTOF_DEL --- 0.074 R8C4A.C0 to R8C4A.F0 RTAVR/ROM/SLICE_281 ROUTE 1 0.000 R8C4A.F0 to R8C4A.DI0 RTAVR/ROM/fb_14 (to CLK_OUT) -------- 1.207 (29.7% logic, 70.3% route), 4 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/SLICE_316: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C7C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_281: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.150 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 0.691 R14C2C.Q0 to R8C4A.CLK CLK_OUT -------- 1.582 (9.5% logic, 90.5% route), 1 logic levels. Passed: The following path meets requirements by 0.385ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_ea_15 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_1 (to CLK_OUT -) Delay: 1.207ns (29.7% logic, 70.3% route), 4 logic levels. Constraint Details: 1.207ns physical path delay RTAVR/SLICE_316 to RTAVR/ROM/SLICE_276 meets (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) -0.019ns DIN_HLD and 0.000ns delay constraint less -0.841ns skew requirement (totaling 0.822ns) by 0.385ns Physical Path Details: Data path RTAVR/SLICE_316 to RTAVR/ROM/SLICE_276: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R14C7C.CLK to R14C7C.Q1 RTAVR/SLICE_316 (from CLK_INT_inferred_clock) ROUTE 3 0.267 R14C7C.Q1 to R14C2C.D1 RTAVR/S1_EA_15 CTOF_DEL --- 0.074 R14C2C.D1 to R14C2C.F1 RTAVR/SLICE_538 ROUTE 3 0.172 R14C2C.F1 to R14C2A.C1 RTAVR/EA_15 CTOF_DEL --- 0.074 R14C2A.C1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 0.409 R14C2A.F1 to R8C4B.C1 RTAVR/rd_romdup CTOF_DEL --- 0.074 R8C4B.C1 to R8C4B.F1 RTAVR/ROM/SLICE_276 ROUTE 1 0.000 R8C4B.F1 to R8C4B.DI1 RTAVR/ROM/fb_7 (to CLK_OUT) -------- 1.207 (29.7% logic, 70.3% route), 4 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/SLICE_316: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C7C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_276: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.150 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 0.691 R14C2C.Q0 to R8C4B.CLK CLK_OUT -------- 1.582 (9.5% logic, 90.5% route), 1 logic levels. Passed: The following path meets requirements by 0.385ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S1/s2_ea_15 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/ROM/DOA_4 (to CLK_OUT -) Delay: 1.207ns (29.7% logic, 70.3% route), 4 logic levels. Constraint Details: 1.207ns physical path delay RTAVR/SLICE_316 to RTAVR/ROM/SLICE_278 meets (delay constraint based on source clock period of 9.907ns and destination clock period of 2.000ns) -0.019ns DIN_HLD and 0.000ns delay constraint less -0.841ns skew requirement (totaling 0.822ns) by 0.385ns Physical Path Details: Data path RTAVR/SLICE_316 to RTAVR/ROM/SLICE_278: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R14C7C.CLK to R14C7C.Q1 RTAVR/SLICE_316 (from CLK_INT_inferred_clock) ROUTE 3 0.267 R14C7C.Q1 to R14C2C.D1 RTAVR/S1_EA_15 CTOF_DEL --- 0.074 R14C2C.D1 to R14C2C.F1 RTAVR/SLICE_538 ROUTE 3 0.172 R14C2C.F1 to R14C2A.C1 RTAVR/EA_15 CTOF_DEL --- 0.074 R14C2A.C1 to R14C2A.F1 RTAVR/SLICE_457 ROUTE 34 0.409 R14C2A.F1 to R8C4C.C0 RTAVR/rd_romdup CTOF_DEL --- 0.074 R8C4C.C0 to R8C4C.F0 RTAVR/ROM/SLICE_278 ROUTE 1 0.000 R8C4C.F0 to R8C4C.DI0 RTAVR/ROM/fb_4 (to CLK_OUT) -------- 1.207 (29.7% logic, 70.3% route), 4 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/SLICE_316: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C7C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/ROM/SLICE_278: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C2C.CLK CLK_INT_inferred_clock REG_DEL --- 0.150 R14C2C.CLK to R14C2C.Q0 RTAVR/SLICE_538 ROUTE 168 0.691 R14C2C.Q0 to R8C4C.CLK CLK_OUT -------- 1.582 (9.5% logic, 90.5% route), 1 logic levels. Passed: The following path meets requirements by 0.389ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/ROM/DOA_6 (from CLK_OUT -) Destination: FF Data in RTAVR/ROM/DOA_6 (to CLK_OUT -) Delay: 0.370ns (64.9% logic, 35.1% route), 2 logic levels. Constraint Details: 0.370ns physical path delay RTAVR/ROM/SLICE_279 to RTAVR/ROM/SLICE_279 meets -0.019ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.389ns Physical Path Details: Data path RTAVR/ROM/SLICE_279 to RTAVR/ROM/SLICE_279: Name Fanout Delay (ns) Site Resource LTCH_DEL --- 0.166 R9C8B.CLK to R9C8B.Q0 RTAVR/ROM/SLICE_279 (from CLK_OUT) ROUTE 5 0.130 R9C8B.Q0 to R9C8B.D0 RTAVR/ROM_DOA_6 CTOF_DEL --- 0.074 R9C8B.D0 to R9C8B.F0 RTAVR/ROM/SLICE_279 ROUTE 1 0.000 R9C8B.F0 to R9C8B.DI0 RTAVR/ROM/fb_2 (to CLK_OUT) -------- 0.370 (64.9% logic, 35.1% route), 2 logic levels. Clock Skew Details: Source Clock Path RTAVR/SLICE_538 to RTAVR/ROM/SLICE_279: Name Fanout Delay (ns) Site Resource ROUTE 168 0.691 R14C2C.Q0 to R9C8B.CLK CLK_OUT -------- 0.691 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RTAVR/SLICE_538 to RTAVR/ROM/SLICE_279: Name Fanout Delay (ns) Site Resource ROUTE 168 0.691 R14C2C.Q0 to R9C8B.CLK CLK_OUT -------- 0.691 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.390ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/ROM/DOA_5 (from CLK_OUT -) Destination: FF Data in RTAVR/ROM/DOA_5 (to CLK_OUT -) Delay: 0.371ns (64.7% logic, 35.3% route), 2 logic levels. Constraint Details: 0.371ns physical path delay RTAVR/ROM/SLICE_278 to RTAVR/ROM/SLICE_278 meets -0.019ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.390ns Physical Path Details: Data path RTAVR/ROM/SLICE_278 to RTAVR/ROM/SLICE_278: Name Fanout Delay (ns) Site Resource LTCH_DEL --- 0.166 R8C4C.CLK to R8C4C.Q1 RTAVR/ROM/SLICE_278 (from CLK_OUT) ROUTE 5 0.131 R8C4C.Q1 to R8C4C.A1 RTAVR/ROM_DOA_5 CTOF_DEL --- 0.074 R8C4C.A1 to R8C4C.F1 RTAVR/ROM/SLICE_278 ROUTE 1 0.000 R8C4C.F1 to R8C4C.DI1 RTAVR/ROM/fb_3 (to CLK_OUT) -------- 0.371 (64.7% logic, 35.3% route), 2 logic levels. Clock Skew Details: Source Clock Path RTAVR/SLICE_538 to RTAVR/ROM/SLICE_278: Name Fanout Delay (ns) Site Resource ROUTE 168 0.691 R14C2C.Q0 to R8C4C.CLK CLK_OUT -------- 0.691 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path RTAVR/SLICE_538 to RTAVR/ROM/SLICE_278: Name Fanout Delay (ns) Site Resource ROUTE 168 0.691 R14C2C.Q0 to R8C4C.CLK CLK_OUT -------- 0.691 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: FREQUENCY NET "CLK_INT_inferred_clock" 100.929000 MHz ; 4096 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.277ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/S0/s1_sbix (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/S1/s2_sbix (to CLK_INT_inferred_clock -) Delay: 0.271ns (50.6% logic, 49.4% route), 1 logic levels. Constraint Details: 0.271ns physical path delay RTAVR/SLICE_267 to RTAVR/S1/SLICE_129 meets -0.006ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.006ns) by 0.277ns Physical Path Details: Data path RTAVR/SLICE_267 to RTAVR/S1/SLICE_129: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R8C9D.CLK to R8C9D.Q0 RTAVR/SLICE_267 (from CLK_INT_inferred_clock) ROUTE 3 0.134 R8C9D.Q0 to R8C9C.M1 RTAVR/PD_SBIX (to CLK_INT_inferred_clock) -------- 0.271 (50.6% logic, 49.4% route), 1 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/SLICE_267: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R8C9D.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/S1/SLICE_129: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R8C9C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.312ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_pr_8 (from CLK_INT_inferred_clock -) Destination: FF Data in ISP/r_pr_cry_0_7 (to CLK_INT_inferred_clock -) FF ISP/r_pr_8 FF ISP/r_pr_7 Delay: 0.268ns (51.1% logic, 48.9% route), 1 logic levels. Constraint Details: 0.268ns physical path delay ISP/SLICE_73 to ISP/SLICE_73 meets -0.044ns LUT_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.044ns) by 0.312ns Physical Path Details: Data path ISP/SLICE_73 to ISP/SLICE_73: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R16C3A.CLK to R16C3A.Q1 ISP/SLICE_73 (from CLK_INT_inferred_clock) ROUTE 3 0.131 R16C3A.Q1 to R16C3A.A1 ISP_ADDR_8 (to CLK_INT_inferred_clock) -------- 0.268 (51.1% logic, 48.9% route), 1 logic levels. Clock Skew Details: Source Clock Path osc_internal to ISP/SLICE_73: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R16C3A.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to ISP/SLICE_73: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R16C3A.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.314ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_pr_11 (from CLK_INT_inferred_clock -) Destination: FF Data in ISP/r_pr_cry_0_11 (to CLK_INT_inferred_clock -) FF ISP/r_pr_12 FF ISP/r_pr_11 Delay: 0.268ns (51.1% logic, 48.9% route), 1 logic levels. Constraint Details: 0.268ns physical path delay ISP/SLICE_71 to ISP/SLICE_71 meets -0.046ns LUT_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.046ns) by 0.314ns Physical Path Details: Data path ISP/SLICE_71 to ISP/SLICE_71: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R16C3C.CLK to R16C3C.Q0 ISP/SLICE_71 (from CLK_INT_inferred_clock) ROUTE 3 0.131 R16C3C.Q0 to R16C3C.A0 ISP_ADDR_11 (to CLK_INT_inferred_clock) -------- 0.268 (51.1% logic, 48.9% route), 1 logic levels. Clock Skew Details: Source Clock Path osc_internal to ISP/SLICE_71: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R16C3C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to ISP/SLICE_71: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R16C3C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.315ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_pr_12 (from CLK_INT_inferred_clock -) Destination: FF Data in ISP/r_pr_cry_0_11 (to CLK_INT_inferred_clock -) FF ISP/r_pr_12 FF ISP/r_pr_11 Delay: 0.271ns (50.6% logic, 49.4% route), 1 logic levels. Constraint Details: 0.271ns physical path delay ISP/SLICE_71 to ISP/SLICE_71 meets -0.044ns LUT_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.044ns) by 0.315ns Physical Path Details: Data path ISP/SLICE_71 to ISP/SLICE_71: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R16C3C.CLK to R16C3C.Q1 ISP/SLICE_71 (from CLK_INT_inferred_clock) ROUTE 3 0.134 R16C3C.Q1 to R16C3C.A1 ISP_ADDR_12 (to CLK_INT_inferred_clock) -------- 0.271 (50.6% logic, 49.4% route), 1 logic levels. Clock Skew Details: Source Clock Path osc_internal to ISP/SLICE_71: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R16C3C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to ISP/SLICE_71: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R16C3C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.331ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_pr_15 (from CLK_INT_inferred_clock -) Destination: FF Data in ISP/r_pr_15 (to CLK_INT_inferred_clock -) Delay: 0.271ns (50.6% logic, 49.4% route), 1 logic levels. Constraint Details: 0.271ns physical path delay ISP/SLICE_69 to ISP/SLICE_69 meets -0.060ns LUT_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.060ns) by 0.331ns Physical Path Details: Data path ISP/SLICE_69 to ISP/SLICE_69: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R16C4A.CLK to R16C4A.Q0 ISP/SLICE_69 (from CLK_INT_inferred_clock) ROUTE 5 0.134 R16C4A.Q0 to R16C4A.A0 ISP_ADDR_15 (to CLK_INT_inferred_clock) -------- 0.271 (50.6% logic, 49.4% route), 1 logic levels. Clock Skew Details: Source Clock Path osc_internal to ISP/SLICE_69: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R16C4A.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to ISP/SLICE_69: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R16C4A.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.342ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/IOR/IOR_PS0/r_spl_0 (from CLK_INT_inferred_clock +) Destination: FF Data in RTAVR/IOR/IOR_PS0/r_spl_0 (to CLK_INT_inferred_clock +) Delay: 0.334ns (59.9% logic, 40.1% route), 2 logic levels. Constraint Details: 0.334ns physical path delay RTAVR/IOR/IOR_PS0/SLICE_319 to RTAVR/IOR/IOR_PS0/SLICE_319 meets -0.008ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.008ns) by 0.342ns Physical Path Details: Data path RTAVR/IOR/IOR_PS0/SLICE_319 to RTAVR/IOR/IOR_PS0/SLICE_319: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.126 R14C10C.CLK to R14C10C.Q0 RTAVR/IOR/IOR_PS0/SLICE_319 (from CLK_INT_inferred_clock) ROUTE 5 0.134 R14C10C.Q0 to R14C10C.A0 RTAVR/SP_IN_0 CTOF_DEL --- 0.074 R14C10C.A0 to R14C10C.F0 RTAVR/IOR/IOR_PS0/SLICE_319 ROUTE 1 0.000 R14C10C.F0 to R14C10C.DI0 RTAVR/IOR/IOR_PS0/r_spl_5_0 (to CLK_INT_inferred_clock) -------- 0.334 (59.9% logic, 40.1% route), 2 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/IOR/IOR_PS0/SLICE_319: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C10C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/IOR/IOR_PS0/SLICE_319: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R14C10C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.352ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_2 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_cry_0_2 (to CLK_INT_inferred_clock -) FF RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_3 FF RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_2 Delay: 0.302ns (45.4% logic, 54.6% route), 1 logic levels. Constraint Details: 0.302ns physical path delay RTAVR/IOR/IOR_PS0/i_timer0/SLICE_47 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_47 meets -0.050ns LUT_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.050ns) by 0.352ns Physical Path Details: Data path RTAVR/IOR/IOR_PS0/i_timer0/SLICE_47 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_47: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R19C10B.CLK to R19C10B.Q0 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_47 (from CLK_INT_inferred_clock) ROUTE 1 0.165 R19C10B.Q0 to R19C10B.C0 RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_2 (to CLK_INT_inferred_clock) -------- 0.302 (45.4% logic, 54.6% route), 1 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_47: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R19C10B.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_47: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R19C10B.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.352ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_0 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_cry_0_0 (to CLK_INT_inferred_clock -) FF RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_1 FF RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_0 Delay: 0.302ns (45.4% logic, 54.6% route), 1 logic levels. Constraint Details: 0.302ns physical path delay RTAVR/IOR/IOR_PS0/i_timer0/SLICE_48 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_48 meets -0.050ns LUT_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.050ns) by 0.352ns Physical Path Details: Data path RTAVR/IOR/IOR_PS0/i_timer0/SLICE_48 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_48: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R19C10A.CLK to R19C10A.Q0 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_48 (from CLK_INT_inferred_clock) ROUTE 1 0.165 R19C10A.Q0 to R19C10A.C0 RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_0 (to CLK_INT_inferred_clock) -------- 0.302 (45.4% logic, 54.6% route), 1 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_48: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R19C10A.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_48: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R19C10A.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.354ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/IOR/i_usart/r_ps_8 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/IOR/i_usart/r_ps_cry_0_8 (to CLK_INT_inferred_clock -) FF RTAVR/IOR/i_usart/r_ps_9 FF RTAVR/IOR/i_usart/r_ps_8 Delay: 0.304ns (45.1% logic, 54.9% route), 1 logic levels. Constraint Details: 0.304ns physical path delay RTAVR/IOR/i_usart/SLICE_34 to RTAVR/IOR/i_usart/SLICE_34 meets -0.050ns LUT_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.050ns) by 0.354ns Physical Path Details: Data path RTAVR/IOR/i_usart/SLICE_34 to RTAVR/IOR/i_usart/SLICE_34: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R15C15A.CLK to R15C15A.Q0 RTAVR/IOR/i_usart/SLICE_34 (from CLK_INT_inferred_clock) ROUTE 2 0.167 R15C15A.Q0 to R15C15A.C0 RTAVR/IOR/i_usart/r_ps_8 (to CLK_INT_inferred_clock) -------- 0.304 (45.1% logic, 54.9% route), 1 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/IOR/i_usart/SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R15C15A.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/IOR/i_usart/SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R15C15A.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.355ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_5 (from CLK_INT_inferred_clock -) Destination: FF Data in RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_5 (to CLK_INT_inferred_clock -) FF RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_4 Delay: 0.306ns (44.8% logic, 55.2% route), 1 logic levels. Constraint Details: 0.306ns physical path delay RTAVR/IOR/IOR_PS0/i_timer0/SLICE_46 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_46 meets -0.049ns LUT_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.049ns) by 0.355ns Physical Path Details: Data path RTAVR/IOR/IOR_PS0/i_timer0/SLICE_46 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_46: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.137 R19C10C.CLK to R19C10C.Q1 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_46 (from CLK_INT_inferred_clock) ROUTE 3 0.169 R19C10C.Q1 to R19C10C.C1 RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_5 (to CLK_INT_inferred_clock) -------- 0.306 (44.8% logic, 55.2% route), 1 logic levels. Clock Skew Details: Source Clock Path osc_internal to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_46: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R19C10C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_46: Name Fanout Delay (ns) Site Resource ROUTE 274 0.741 OSC.OSC to R19C10C.CLK CLK_INT_inferred_clock -------- 0.741 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "CLK_OUT" 499.750000 MHz | | | ; | -| -| 4 | | | FREQUENCY NET "CLK_INT_inferred_clock" | | | 100.929000 MHz ; | -| -| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: CLK_OUT Source: RTAVR/SLICE_538.Q0 Loads: 168 Covered under: FREQUENCY NET "CLK_OUT" 499.750000 MHz ; Data transfers from: Clock Domain: CLK_INT_inferred_clock Source: osc_internal.CFGCLK Covered under: FREQUENCY NET "CLK_OUT" 499.750000 MHz ; Transfers: 24 Clock Domain: CLK_INT_inferred_clock Source: osc_internal.CFGCLK Loads: 274 Covered under: FREQUENCY NET "CLK_INT_inferred_clock" 100.929000 MHz ; Data transfers from: Clock Domain: CLK_OUT Source: RTAVR/SLICE_538.Q0 Covered under: FREQUENCY NET "CLK_INT_inferred_clock" 100.929000 MHz ; Transfers: 16 Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 876038 paths, 97 nets, and 5087 connections (99.9% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 4256 (setup), 0 (hold) Score: 207425080 (setup), 0 (hold) Cumulative negative slack: 157683988 (157683988+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------