PAR: Place And Route Diamond_1.4_Production (87). Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Sat Feb 25 15:45:46 2012 C:/lscc/diamond/1.4/ispfpga\bin\nt\par -f MachXO2_Breakout_test_hdl_xo2.p2t MachXO2_Breakout_test_hdl_xo2_map.ncd MachXO2_Breakout_test_hdl_xo2.dir MachXO2_Breakout_test_hdl_xo2.prf Preference file: MachXO2_Breakout_test_hdl_xo2.prf. Cost Table Summary Level/ Number Timing Run NCD Cost [ncd] Unrouted Score Time Status ---------- -------- -------- ----- ------------ 5_1 * 0 0 02:05 Complete * : Design saved. par done! Lattice Place and Route Report for Design "MachXO2_Breakout_test_hdl_xo2_map.ncd" Sat Feb 25 15:45:46 2012 Best Par Run PAR: Place And Route Diamond_1.4_Production (87). Command Line: C:/lscc/diamond/1.4/ispfpga\bin\nt\par -f MachXO2_Breakout_test_hdl_xo2.p2t MachXO2_Breakout_test_hdl_xo2_map.ncd MachXO2_Breakout_test_hdl_xo2.dir MachXO2_Breakout_test_hdl_xo2.prf Preference file: MachXO2_Breakout_test_hdl_xo2.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file MachXO2_Breakout_test_hdl_xo2_map.ncd. Design name: tool_test NCD version: 3.2 Vendor: LATTICE Device: LCMXO2-1200ZE Package: TQFP144 Performance: 1 Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/1.4/ispfpga. Package Status: Final Version 1.33 Performance Hardware Data Status: Final Version 22.4 License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 14/108 12% used 14/108 12% bonded SLICE 126/640 19% used OSC 1/1 100% used JTAG 1/1 100% used EBR 1/7 14% used PLL 1/1 100% used WARNING - par: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - par: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - par: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - par: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. Number of Signals: 550 Number of Connections: 870 Pin Constraint Summary: 10 out of 14 pins locked (71% locked). The following 6 signals are selected to use the primary clock routing resources: CLK_IN0 (driver: clk_selector, clk load #: 14) CLK0_OUT (driver: pll, clk load #: 13) CLK90_OUT (driver: pll, clk load #: 13) CLK (driver: osc_internal, clk load #: 53) CLK180_OUT (driver: pll, clk load #: 13) CLK270_OUT (driver: pll, clk load #: 13) The following 1 signal is selected to use the DCM clock routing resources: CLK_IN0 (driver: clk_selector, clk load #: 14) No signal is selected as secondary clock. No signal is selected as Global Set/Reset. Starting Placer Phase 0. ......... Finished Placer Phase 0. REAL time: 5 secs Starting Placer Phase 1. ................... Placer score = 24619. Finished Placer Phase 1. REAL time: 1 mins 56 secs Starting Placer Phase 2. . Placer score = 24619 Finished Placer Phase 2. REAL time: 1 mins 56 secs Clock Report Global Clock Resources: CLK_PIN : 1 out of 8 (12%) PLL : 1 out of 1 (100%) DCM : 1 out of 2 (50%) DCC : 0 out of 8 (0%) Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY "CLK0_OUT" from CLKOP on comp "pll" on PLL site "LPLL", clk load = 13 PRIMARY "CLK90_OUT" from CLKOS on comp "pll" on PLL site "LPLL", clk load = 13 PRIMARY "CLK" from OSC on comp "osc_internal" on site "OSC", clk load = 53 PRIMARY "CLK180_OUT" from CLKOS2 on comp "pll" on PLL site "LPLL", clk load = 13 PRIMARY "CLK270_OUT" from CLKOS3 on comp "pll" on PLL site "LPLL", clk load = 13 PRIMARY DCM "CLK_IN0", total # of clk loads = 14 "CLK_IN0" from comp "clk_selector" on DCM site "DCM6" - DCM input "CLK" from OSC on comp "osc_internal" on site "OSC" - DCM input "EXTOSC_c" from comp "EXTOSC" on CLK_PIN site "27 (PL9A)" PRIMARY : 6 out of 8 (75%) SECONDARY: 0 out of 8 (0%) Edge Clocks: No edge clock selected. I/O Usage Summary (final): 14 out of 108 (13.0%) PIO sites used. 14 out of 108 (13.0%) bonded PIO sites used. Number of PIO comps: 14; differential: 0 Number of Vref pins used: 0 I/O Bank Usage Summary: +----------+---------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+---------------+------------+-----------+ | 0 | 4 / 28 ( 14%) | 2.5V | - | | 1 | 8 / 26 ( 30%) | 3.3V | - | | 2 | 0 / 28 ( 0%) | - | - | | 3 | 2 / 26 ( 7%) | 3.3V | - | +----------+---------------+------------+-----------+ Total placer CPU time: 1 mins 43 secs Dumping design to file MachXO2_Breakout_test_hdl_xo2.dir/5_1.ncd. WARNING - par: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - par: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - par: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - par: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. 0 connections routed; 870 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 2 mins 1 secs Starting iterative routing. For each routing iteration the number inside the parenthesis is the total time (in picoseconds) the design is failing the timing constraints. For each routing iteration the router will attempt to reduce this number until the number of routing iterations is completed or the value is 0 meaning the design has fully met the timing constraints. End of iteration 1 870 successful; 0 unrouted; (0) real time: 2 mins 3 secs Dumping design to file MachXO2_Breakout_test_hdl_xo2.dir/5_1.ncd. Total CPU time 1 mins 49 secs Total REAL time: 2 mins 3 secs Completely routed. End of route. 870 routed (100.00%); 0 unrouted. Checking DRC ... No errors found. WARNING - par: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - par: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - par: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - par: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. Timing score: 0 Total REAL time to completion: 2 mins 5 secs Dumping design to file MachXO2_Breakout_test_hdl_xo2.dir/5_1.ncd. All signals are completely routed. par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.