Place & Route TRACE Report
Loading design for application trce from file machxo2_breakout_rtavr_xo2.ncd.
Design name: xo2_isp
NCD version: 3.2
Vendor: LATTICE
Device: LCMXO2-1200ZE
Package: TQFP144
Performance: 1
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/1.4/ispfpga.
Package Status: Final Version 1.33
Performance Hardware Data Status: Final Version 22.4
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond_1.4_Production (87)
Sat Feb 25 14:02:41 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce -v 10 -gt -sethld -sp 1 -sphld m -o MachXO2_Breakout_rtavr_xo2.twr MachXO2_Breakout_rtavr_xo2.ncd MachXO2_Breakout_rtavr_xo2.prf
Design file: machxo2_breakout_rtavr_xo2.ncd
Preference file: machxo2_breakout_rtavr_xo2.prf
Device,speed: LCMXO2-1200ZE,1
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY NET "CLK180_OUT" 12.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 14.127MHz is the maximum frequency for this preference.
FREQUENCY NET "CLK_INT" 2.080000 MHz (0 errors) 0 items scored, 0 timing errors detected.
FREQUENCY NET "CLK_IN0" 12.000000 MHz (0 errors) 0 items scored, 0 timing errors detected.
FREQUENCY NET "CLK0_OUT" 12.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 15.267MHz is the maximum frequency for this preference.
FREQUENCY NET "CLK90_OUT" 12.000000 MHz (0 errors) 2103 items scored, 0 timing errors detected.
Report: 14.504MHz is the maximum frequency for this preference.
FREQUENCY NET "CLK270_OUT" 12.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 14.187MHz is the maximum frequency for this preference.
FREQUENCY PORT "EXTOSC" 24.000000 MHz (0 errors) 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
PERIOD PORT "TOP_TCK" 0.100000 nS (1 errors)
0 items scored, 1 timing error detected.
WARNING - trce: Input and feedback clock frequencies do not match their divider settings for pll
WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz.
WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz.
WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz.
WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ;
4096 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 6.272ns (weighted slack = 12.544ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i8 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/i_usart/rx_data_rdy_403 (to CLK180_OUT +)
Delay: 34.689ns (29.4% logic, 70.6% route), 11 logic levels.
Constraint Details:
34.689ns physical path delay ISP/SLICE_126 to RTAVR/IOR/i_usart/SLICE_298 meets
41.666ns delay constraint less
0.000ns skew and
0.705ns LSR_SET requirement (totaling 40.961ns) by 6.272ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/IOR/i_usart/SLICE_298:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q0 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.816 R10C4A.Q0 to R7C9D.C1 ISP_ADDR_8
CTOF_DEL --- 0.923 R7C9D.C1 to R7C9D.F1 RTAVR/SLICE_566
ROUTE 4 1.680 R7C9D.F1 to R7C7A.D0 RTAVR/RAM_ADDRB_8
CTOF_DEL --- 0.923 R7C7A.D0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 3.382 R8C7B.F0 to R7C14B.D1 RTAVR/IOR/i_usart/n494
CTOF_DEL --- 0.923 R7C14B.D1 to R7C14B.F1 RTAVR/SLICE_176
ROUTE 1 3.226 R7C14B.F1 to R9C7C.LSR RTAVR/IOR/i_usart/n3120 (to CLK180_OUT)
--------
34.689 (29.4% logic, 70.6% route), 11 logic levels.
Clock Skew Details:
Source Clock Path pll to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/i_usart/SLICE_298:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R9C7C.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.848ns (weighted slack = 13.696ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i9 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/i_usart/rx_data_rdy_403 (to CLK180_OUT +)
Delay: 34.113ns (29.9% logic, 70.1% route), 11 logic levels.
Constraint Details:
34.113ns physical path delay ISP/SLICE_126 to RTAVR/IOR/i_usart/SLICE_298 meets
41.666ns delay constraint less
0.000ns skew and
0.705ns LSR_SET requirement (totaling 40.961ns) by 6.848ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/IOR/i_usart/SLICE_298:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q1 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.221 R10C4A.Q1 to R7C7A.D1 ISP_ADDR_9
CTOF_DEL --- 0.923 R7C7A.D1 to R7C7A.F1 RTAVR/SLICE_533
ROUTE 4 1.699 R7C7A.F1 to R7C7A.B0 RTAVR/RAM_ADDRB_9
CTOF_DEL --- 0.923 R7C7A.B0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 3.382 R8C7B.F0 to R7C14B.D1 RTAVR/IOR/i_usart/n494
CTOF_DEL --- 0.923 R7C14B.D1 to R7C14B.F1 RTAVR/SLICE_176
ROUTE 1 3.226 R7C14B.F1 to R9C7C.LSR RTAVR/IOR/i_usart/n3120 (to CLK180_OUT)
--------
34.113 (29.9% logic, 70.1% route), 11 logic levels.
Clock Skew Details:
Source Clock Path pll to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/i_usart/SLICE_298:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R9C7C.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.224ns (weighted slack = 14.448ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i10 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/i_usart/rx_data_rdy_403 (to CLK180_OUT +)
Delay: 33.737ns (30.2% logic, 69.8% route), 11 logic levels.
Constraint Details:
33.737ns physical path delay ISP/SLICE_127 to RTAVR/IOR/i_usart/SLICE_298 meets
41.666ns delay constraint less
0.000ns skew and
0.705ns LSR_SET requirement (totaling 40.961ns) by 7.224ns
Physical Path Details:
Data path ISP/SLICE_127 to RTAVR/IOR/i_usart/SLICE_298:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R9C6C.CLK to R9C6C.Q0 ISP/SLICE_127 (from CLK180_OUT)
ROUTE 2 2.248 R9C6C.Q0 to R7C7C.D1 ISP_ADDR_10
CTOF_DEL --- 0.923 R7C7C.D1 to R7C7C.F1 RTAVR/SLICE_565
ROUTE 4 2.296 R7C7C.F1 to R7C7A.A0 RTAVR/RAM_ADDRB_10
CTOF_DEL --- 0.923 R7C7A.A0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 3.382 R8C7B.F0 to R7C14B.D1 RTAVR/IOR/i_usart/n494
CTOF_DEL --- 0.923 R7C14B.D1 to R7C14B.F1 RTAVR/SLICE_176
ROUTE 1 3.226 R7C14B.F1 to R9C7C.LSR RTAVR/IOR/i_usart/n3120 (to CLK180_OUT)
--------
33.737 (30.2% logic, 69.8% route), 11 logic levels.
Clock Skew Details:
Source Clock Path pll to ISP/SLICE_127:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R9C6C.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/i_usart/SLICE_298:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R9C7C.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.502ns (weighted slack = 15.004ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i8 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/i_usart/FE_409 (to CLK180_OUT +)
Delay: 33.594ns (30.3% logic, 69.7% route), 11 logic levels.
Constraint Details:
33.594ns physical path delay ISP/SLICE_126 to RTAVR/IOR/i_usart/SLICE_603 meets
41.666ns delay constraint less
0.000ns skew and
0.570ns CE_SET requirement (totaling 41.096ns) by 7.502ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/IOR/i_usart/SLICE_603:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q0 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.816 R10C4A.Q0 to R7C9D.C1 ISP_ADDR_8
CTOF_DEL --- 0.923 R7C9D.C1 to R7C9D.F1 RTAVR/SLICE_566
ROUTE 4 1.680 R7C9D.F1 to R7C7A.D0 RTAVR/RAM_ADDRB_8
CTOF_DEL --- 0.923 R7C7A.D0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 2.930 R8C7B.F0 to R8C14B.C1 RTAVR/IOR/i_usart/n494
CTOF_DEL --- 0.923 R8C14B.C1 to R8C14B.F1 RTAVR/SLICE_406
ROUTE 1 2.583 R8C14B.F1 to R8C6D.CE RTAVR/IOR/i_usart/n2287 (to CLK180_OUT)
--------
33.594 (30.3% logic, 69.7% route), 11 logic levels.
Clock Skew Details:
Source Clock Path pll to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/i_usart/SLICE_603:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R8C6D.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.591ns (weighted slack = 15.182ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i8 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/i_usart/rx_count_en_401 (to CLK180_OUT +)
Delay: 33.370ns (30.5% logic, 69.5% route), 11 logic levels.
Constraint Details:
33.370ns physical path delay ISP/SLICE_126 to RTAVR/IOR/SLICE_594 meets
41.666ns delay constraint less
0.000ns skew and
0.705ns LSR_SET requirement (totaling 40.961ns) by 7.591ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/IOR/SLICE_594:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q0 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.816 R10C4A.Q0 to R7C9D.C1 ISP_ADDR_8
CTOF_DEL --- 0.923 R7C9D.C1 to R7C9D.F1 RTAVR/SLICE_566
ROUTE 4 1.680 R7C9D.F1 to R7C7A.D0 RTAVR/RAM_ADDRB_8
CTOF_DEL --- 0.923 R7C7A.D0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.569 R8C7A.F0 to R8C6D.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C6D.D1 to R8C6D.F1 RTAVR/IOR/i_usart/SLICE_603
ROUTE 6 2.325 R8C6D.F1 to R9C7C.D0 RTAVR/IOR/do_rxcount
CTOF_DEL --- 0.923 R9C7C.D0 to R9C7C.F0 RTAVR/IOR/i_usart/SLICE_298
ROUTE 3 1.575 R9C7C.F0 to R8C7C.D0 RTAVR/IOR/i_usart/n2277
CTOF_DEL --- 0.923 R8C7C.D0 to R8C7C.F0 RTAVR/IOR/SLICE_673
ROUTE 1 2.466 R8C7C.F0 to R8C6A.LSR RTAVR/IOR/i_usart/n2297 (to CLK180_OUT)
--------
33.370 (30.5% logic, 69.5% route), 11 logic levels.
Clock Skew Details:
Source Clock Path pll to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/SLICE_594:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R8C6A.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.714ns (weighted slack = 15.428ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i6 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/i_usart/rx_data_rdy_403 (to CLK180_OUT +)
Delay: 33.247ns (30.6% logic, 69.4% route), 11 logic levels.
Constraint Details:
33.247ns physical path delay ISP/SLICE_125 to RTAVR/IOR/i_usart/SLICE_298 meets
41.666ns delay constraint less
0.000ns skew and
0.705ns LSR_SET requirement (totaling 40.961ns) by 7.714ns
Physical Path Details:
Data path ISP/SLICE_125 to RTAVR/IOR/i_usart/SLICE_298:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R9C5C.CLK to R9C5C.Q0 ISP/SLICE_125 (from CLK180_OUT)
ROUTE 2 2.248 R9C5C.Q0 to R7C6C.D1 ISP_ADDR_6
CTOF_DEL --- 0.923 R7C6C.D1 to R7C6C.F1 RTAVR/SLICE_568
ROUTE 4 1.806 R7C6C.F1 to R7C7A.C0 RTAVR/RAM_ADDRB_6
CTOF_DEL --- 0.923 R7C7A.C0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 3.382 R8C7B.F0 to R7C14B.D1 RTAVR/IOR/i_usart/n494
CTOF_DEL --- 0.923 R7C14B.D1 to R7C14B.F1 RTAVR/SLICE_176
ROUTE 1 3.226 R7C14B.F1 to R9C7C.LSR RTAVR/IOR/i_usart/n3120 (to CLK180_OUT)
--------
33.247 (30.6% logic, 69.4% route), 11 logic levels.
Clock Skew Details:
Source Clock Path pll to ISP/SLICE_125:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R9C5C.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/i_usart/SLICE_298:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R9C7C.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.078ns (weighted slack = 16.156ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i9 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/i_usart/FE_409 (to CLK180_OUT +)
Delay: 33.018ns (30.8% logic, 69.2% route), 11 logic levels.
Constraint Details:
33.018ns physical path delay ISP/SLICE_126 to RTAVR/IOR/i_usart/SLICE_603 meets
41.666ns delay constraint less
0.000ns skew and
0.570ns CE_SET requirement (totaling 41.096ns) by 8.078ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/IOR/i_usart/SLICE_603:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q1 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.221 R10C4A.Q1 to R7C7A.D1 ISP_ADDR_9
CTOF_DEL --- 0.923 R7C7A.D1 to R7C7A.F1 RTAVR/SLICE_533
ROUTE 4 1.699 R7C7A.F1 to R7C7A.B0 RTAVR/RAM_ADDRB_9
CTOF_DEL --- 0.923 R7C7A.B0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 2.930 R8C7B.F0 to R8C14B.C1 RTAVR/IOR/i_usart/n494
CTOF_DEL --- 0.923 R8C14B.C1 to R8C14B.F1 RTAVR/SLICE_406
ROUTE 1 2.583 R8C14B.F1 to R8C6D.CE RTAVR/IOR/i_usart/n2287 (to CLK180_OUT)
--------
33.018 (30.8% logic, 69.2% route), 11 logic levels.
Clock Skew Details:
Source Clock Path pll to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/i_usart/SLICE_603:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R8C6D.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.142ns (weighted slack = 16.284ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i8 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/i_usart/rx_count_671__i4 (to CLK180_OUT +)
Delay: 33.092ns (33.6% logic, 66.4% route), 12 logic levels.
Constraint Details:
33.092ns physical path delay ISP/SLICE_126 to RTAVR/IOR/i_usart/SLICE_291 meets
41.666ns delay constraint less
0.000ns skew and
0.432ns DIN_SET requirement (totaling 41.234ns) by 8.142ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/IOR/i_usart/SLICE_291:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q0 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.816 R10C4A.Q0 to R7C9D.C1 ISP_ADDR_8
CTOF_DEL --- 0.923 R7C9D.C1 to R7C9D.F1 RTAVR/SLICE_566
ROUTE 4 1.680 R7C9D.F1 to R7C7A.D0 RTAVR/RAM_ADDRB_8
CTOF_DEL --- 0.923 R7C7A.D0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.569 R8C7A.F0 to R8C6D.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C6D.D1 to R8C6D.F1 RTAVR/IOR/i_usart/SLICE_603
ROUTE 6 2.356 R8C6D.F1 to R10C7B.D0 RTAVR/IOR/do_rxcount
CTOF_DEL --- 0.923 R10C7B.D0 to R10C7B.F0 RTAVR/IOR/i_usart/SLICE_495
ROUTE 2 1.043 R10C7B.F0 to R10C7B.C1 RTAVR/IOR/i_usart/n9696
CTOF_DEL --- 0.923 R10C7B.C1 to R10C7B.F1 RTAVR/IOR/i_usart/SLICE_495
ROUTE 2 1.766 R10C7B.F1 to R9C7B.C0 RTAVR/IOR/i_usart/n9712
CTOF_DEL --- 0.923 R9C7B.C0 to R9C7B.F0 RTAVR/IOR/i_usart/SLICE_291
ROUTE 1 0.000 R9C7B.F0 to R9C7B.DI0 RTAVR/IOR/i_usart/n27 (to CLK180_OUT)
--------
33.092 (33.6% logic, 66.4% route), 12 logic levels.
Clock Skew Details:
Source Clock Path pll to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/i_usart/SLICE_291:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R9C7B.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.167ns (weighted slack = 16.334ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i9 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/i_usart/rx_count_en_401 (to CLK180_OUT +)
Delay: 32.794ns (31.1% logic, 68.9% route), 11 logic levels.
Constraint Details:
32.794ns physical path delay ISP/SLICE_126 to RTAVR/IOR/SLICE_594 meets
41.666ns delay constraint less
0.000ns skew and
0.705ns LSR_SET requirement (totaling 40.961ns) by 8.167ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/IOR/SLICE_594:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q1 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.221 R10C4A.Q1 to R7C7A.D1 ISP_ADDR_9
CTOF_DEL --- 0.923 R7C7A.D1 to R7C7A.F1 RTAVR/SLICE_533
ROUTE 4 1.699 R7C7A.F1 to R7C7A.B0 RTAVR/RAM_ADDRB_9
CTOF_DEL --- 0.923 R7C7A.B0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.569 R8C7A.F0 to R8C6D.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C6D.D1 to R8C6D.F1 RTAVR/IOR/i_usart/SLICE_603
ROUTE 6 2.325 R8C6D.F1 to R9C7C.D0 RTAVR/IOR/do_rxcount
CTOF_DEL --- 0.923 R9C7C.D0 to R9C7C.F0 RTAVR/IOR/i_usart/SLICE_298
ROUTE 3 1.575 R9C7C.F0 to R8C7C.D0 RTAVR/IOR/i_usart/n2277
CTOF_DEL --- 0.923 R8C7C.D0 to R8C7C.F0 RTAVR/IOR/SLICE_673
ROUTE 1 2.466 R8C7C.F0 to R8C6A.LSR RTAVR/IOR/i_usart/n2297 (to CLK180_OUT)
--------
32.794 (31.1% logic, 68.9% route), 11 logic levels.
Clock Skew Details:
Source Clock Path pll to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/SLICE_594:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R8C6A.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 8.329ns (weighted slack = 16.658ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i7 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/i_usart/rx_data_rdy_403 (to CLK180_OUT +)
Delay: 32.632ns (28.4% logic, 71.6% route), 10 logic levels.
Constraint Details:
32.632ns physical path delay ISP/SLICE_125 to RTAVR/IOR/i_usart/SLICE_298 meets
41.666ns delay constraint less
0.000ns skew and
0.705ns LSR_SET requirement (totaling 40.961ns) by 8.329ns
Physical Path Details:
Data path ISP/SLICE_125 to RTAVR/IOR/i_usart/SLICE_298:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R9C5C.CLK to R9C5C.Q1 ISP/SLICE_125 (from CLK180_OUT)
ROUTE 2 2.819 R9C5C.Q1 to R7C8D.C1 ISP_ADDR_7
CTOF_DEL --- 0.923 R7C8D.C1 to R7C8D.F1 RTAVR/SLICE_567
ROUTE 4 2.308 R7C8D.F1 to R7C7B.A0 RTAVR/RAM_ADDRB_7
CTOF_DEL --- 0.923 R7C7B.A0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 3.382 R8C7B.F0 to R7C14B.D1 RTAVR/IOR/i_usart/n494
CTOF_DEL --- 0.923 R7C14B.D1 to R7C14B.F1 RTAVR/SLICE_176
ROUTE 1 3.226 R7C14B.F1 to R9C7C.LSR RTAVR/IOR/i_usart/n3120 (to CLK180_OUT)
--------
32.632 (28.4% logic, 71.6% route), 10 logic levels.
Clock Skew Details:
Source Clock Path pll to ISP/SLICE_125:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R9C5C.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/i_usart/SLICE_298:
Name Fanout Delay (ns) Site Resource
ROUTE 149 3.680 LPLL.CLKOS2 to R9C7C.CLK CLK180_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Report: 14.127MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "CLK_INT" 2.080000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "CLK_IN0" 12.000000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 17.834ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s2_DOBH_rep_6 (from CLK0_OUT +)
Destination: FF Data in RTAVR/S1/r_pc_i0_i10 (to CLK0_OUT +)
Delay: 64.929ns (33.9% logic, 66.1% route), 21 logic levels.
Constraint Details:
64.929ns physical path delay RTAVR/SLICE_683 to RTAVR/S1/SLICE_338 meets
83.333ns delay constraint less
0.000ns skew and
0.570ns CE_SET requirement (totaling 82.763ns) by 17.834ns
Physical Path Details:
Data path RTAVR/SLICE_683 to RTAVR/S1/SLICE_338:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R4C7C.CLK to R4C7C.Q1 RTAVR/SLICE_683 (from CLK0_OUT)
ROUTE 8 5.665 R4C7C.Q1 to R8C17A.C1 RTAVR/GPR/n1441
CTOF_DEL --- 0.923 R8C17A.C1 to R8C17A.F1 RTAVR/SLICE_516
ROUTE 3 1.569 R8C17A.F1 to R7C17A.D1 RTAVR/GPR_DOBH_0
CTOF_DEL --- 0.923 R7C17A.D1 to R7C17A.F1 RTAVR/SLICE_357
ROUTE 1 2.931 R7C17A.F1 to R7C20A.A1 RTAVR/ALU_RR_0
C1TOFCO_DE --- 1.795 R7C20A.A1 to R7C20A.FCO RTAVR/ALU/SLICE_61
ROUTE 1 0.000 R7C20A.FCO to R7C20B.FCI RTAVR/ALU/n9841
FCITOF0_DE --- 1.181 R7C20B.FCI to R7C20B.F0 RTAVR/ALU/SLICE_60
ROUTE 2 1.835 R7C20B.F0 to R9C20B.C0 RTAVR/ALU/n108
C0TOFCO_DE --- 2.064 R9C20B.C0 to R9C20B.FCO RTAVR/ALU/SLICE_70
ROUTE 1 0.000 R9C20B.FCO to R9C20C.FCI RTAVR/ALU/n9870
FCITOF1_DE --- 1.298 R9C20C.FCI to R9C20C.F1 RTAVR/ALU/SLICE_69
ROUTE 1 3.175 R9C20C.F1 to R7C18A.D1 RTAVR/ALU/n115
CTOOFX_DEL --- 1.359 R7C18A.D1 to R7C18A.OFX0 RTAVR/ALU/i10583/SLICE_460
ROUTE 1 0.000 R7C18A.OFX0 to R7C18A.FXB RTAVR/ALU/n11026
FXTOOFX_DE --- 0.478 R7C18A.FXB to R7C18A.OFX1 RTAVR/ALU/i10583/SLICE_460
ROUTE 2 3.375 R7C18A.OFX1 to R9C12D.A1 RTAVR/ALU_OUT_4
CTOF_DEL --- 0.923 R9C12D.A1 to R9C12D.F1 SLICE_621
ROUTE 1 1.482 R9C12D.F1 to R9C12B.D0 RTAVR/ALU/n12000
CTOF_DEL --- 0.923 R9C12B.D0 to R9C12B.F0 SLICE_622
ROUTE 1 1.002 R9C12B.F0 to R9C12B.C1 RTAVR/ALU/n12001
CTOF_DEL --- 0.923 R9C12B.C1 to R9C12B.F1 SLICE_622
ROUTE 1 1.488 R9C12B.F1 to R8C12C.D0 RTAVR/n10825
CTOF_DEL --- 0.923 R8C12C.D0 to R8C12C.F0 RTAVR/SLICE_488
ROUTE 1 1.002 R8C12C.F0 to R8C12C.C1 RTAVR/n4_adj_76
CTOF_DEL --- 0.923 R8C12C.C1 to R8C12C.F1 RTAVR/SLICE_488
ROUTE 2 2.649 R8C12C.F1 to R4C12D.D0 RTAVR/FLAGS_OUT_1
CTOOFX_DEL --- 1.359 R4C12D.D0 to R4C12D.OFX0 RTAVR/i1716/MUX41A/MUX21/SLICE_426
ROUTE 1 0.000 R4C12D.OFX0 to R4C12C.FXA RTAVR/i1716/FXA
FXTOOFX_DE --- 0.478 R4C12C.FXA to R4C12C.OFX1 RTAVR/i1716/MUX41B/MUX21/SLICE_427
ROUTE 2 2.642 R4C12C.OFX1 to R2C18C.D0 RTAVR/v_flags_bit
CTOF_DEL --- 0.923 R2C18C.D0 to R2C18C.F0 RTAVR/S1/SLICE_550
ROUTE 1 1.002 R2C18C.F0 to R2C18C.C1 RTAVR/S1/n15
CTOF_DEL --- 0.923 R2C18C.C1 to R2C18C.F1 RTAVR/S1/SLICE_550
ROUTE 2 4.269 R2C18C.F1 to R7C14C.D0 RTAVR/S1/n79
CTOF_DEL --- 0.923 R7C14C.D0 to R7C14C.F0 RTAVR/S1/SLICE_560
ROUTE 2 2.333 R7C14C.F0 to R7C12C.A0 RTAVR/S1/s0_inv_jump
CTOF_DEL --- 0.923 R7C12C.A0 to R7C12C.F0 RTAVR/S1/SLICE_150
ROUTE 3 1.083 R7C12C.F0 to R7C12C.C1 RTAVR/S1/v_int
CTOF_DEL --- 0.923 R7C12C.C1 to R7C12C.F1 RTAVR/S1/SLICE_150
ROUTE 12 5.384 R7C12C.F1 to R2C15A.CE RTAVR/S1/n1113 (to CLK0_OUT)
--------
64.929 (33.9% logic, 66.1% route), 21 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/SLICE_683:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R4C7C.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/S1/SLICE_338:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R2C15A.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 17.834ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s2_DOBH_rep_6 (from CLK0_OUT +)
Destination: FF Data in RTAVR/S1/r_pc_i0_i2 (to CLK0_OUT +)
Delay: 64.929ns (33.9% logic, 66.1% route), 21 logic levels.
Constraint Details:
64.929ns physical path delay RTAVR/SLICE_683 to RTAVR/S1/SLICE_330 meets
83.333ns delay constraint less
0.000ns skew and
0.570ns CE_SET requirement (totaling 82.763ns) by 17.834ns
Physical Path Details:
Data path RTAVR/SLICE_683 to RTAVR/S1/SLICE_330:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R4C7C.CLK to R4C7C.Q1 RTAVR/SLICE_683 (from CLK0_OUT)
ROUTE 8 5.665 R4C7C.Q1 to R8C17A.C1 RTAVR/GPR/n1441
CTOF_DEL --- 0.923 R8C17A.C1 to R8C17A.F1 RTAVR/SLICE_516
ROUTE 3 1.569 R8C17A.F1 to R7C17A.D1 RTAVR/GPR_DOBH_0
CTOF_DEL --- 0.923 R7C17A.D1 to R7C17A.F1 RTAVR/SLICE_357
ROUTE 1 2.931 R7C17A.F1 to R7C20A.A1 RTAVR/ALU_RR_0
C1TOFCO_DE --- 1.795 R7C20A.A1 to R7C20A.FCO RTAVR/ALU/SLICE_61
ROUTE 1 0.000 R7C20A.FCO to R7C20B.FCI RTAVR/ALU/n9841
FCITOF0_DE --- 1.181 R7C20B.FCI to R7C20B.F0 RTAVR/ALU/SLICE_60
ROUTE 2 1.835 R7C20B.F0 to R9C20B.C0 RTAVR/ALU/n108
C0TOFCO_DE --- 2.064 R9C20B.C0 to R9C20B.FCO RTAVR/ALU/SLICE_70
ROUTE 1 0.000 R9C20B.FCO to R9C20C.FCI RTAVR/ALU/n9870
FCITOF1_DE --- 1.298 R9C20C.FCI to R9C20C.F1 RTAVR/ALU/SLICE_69
ROUTE 1 3.175 R9C20C.F1 to R7C18A.D1 RTAVR/ALU/n115
CTOOFX_DEL --- 1.359 R7C18A.D1 to R7C18A.OFX0 RTAVR/ALU/i10583/SLICE_460
ROUTE 1 0.000 R7C18A.OFX0 to R7C18A.FXB RTAVR/ALU/n11026
FXTOOFX_DE --- 0.478 R7C18A.FXB to R7C18A.OFX1 RTAVR/ALU/i10583/SLICE_460
ROUTE 2 3.375 R7C18A.OFX1 to R9C12D.A1 RTAVR/ALU_OUT_4
CTOF_DEL --- 0.923 R9C12D.A1 to R9C12D.F1 SLICE_621
ROUTE 1 1.482 R9C12D.F1 to R9C12B.D0 RTAVR/ALU/n12000
CTOF_DEL --- 0.923 R9C12B.D0 to R9C12B.F0 SLICE_622
ROUTE 1 1.002 R9C12B.F0 to R9C12B.C1 RTAVR/ALU/n12001
CTOF_DEL --- 0.923 R9C12B.C1 to R9C12B.F1 SLICE_622
ROUTE 1 1.488 R9C12B.F1 to R8C12C.D0 RTAVR/n10825
CTOF_DEL --- 0.923 R8C12C.D0 to R8C12C.F0 RTAVR/SLICE_488
ROUTE 1 1.002 R8C12C.F0 to R8C12C.C1 RTAVR/n4_adj_76
CTOF_DEL --- 0.923 R8C12C.C1 to R8C12C.F1 RTAVR/SLICE_488
ROUTE 2 2.649 R8C12C.F1 to R4C12D.D0 RTAVR/FLAGS_OUT_1
CTOOFX_DEL --- 1.359 R4C12D.D0 to R4C12D.OFX0 RTAVR/i1716/MUX41A/MUX21/SLICE_426
ROUTE 1 0.000 R4C12D.OFX0 to R4C12C.FXA RTAVR/i1716/FXA
FXTOOFX_DE --- 0.478 R4C12C.FXA to R4C12C.OFX1 RTAVR/i1716/MUX41B/MUX21/SLICE_427
ROUTE 2 2.642 R4C12C.OFX1 to R2C18C.D0 RTAVR/v_flags_bit
CTOF_DEL --- 0.923 R2C18C.D0 to R2C18C.F0 RTAVR/S1/SLICE_550
ROUTE 1 1.002 R2C18C.F0 to R2C18C.C1 RTAVR/S1/n15
CTOF_DEL --- 0.923 R2C18C.C1 to R2C18C.F1 RTAVR/S1/SLICE_550
ROUTE 2 4.269 R2C18C.F1 to R7C14C.D0 RTAVR/S1/n79
CTOF_DEL --- 0.923 R7C14C.D0 to R7C14C.F0 RTAVR/S1/SLICE_560
ROUTE 2 2.333 R7C14C.F0 to R7C12C.A0 RTAVR/S1/s0_inv_jump
CTOF_DEL --- 0.923 R7C12C.A0 to R7C12C.F0 RTAVR/S1/SLICE_150
ROUTE 3 1.083 R7C12C.F0 to R7C12C.C1 RTAVR/S1/v_int
CTOF_DEL --- 0.923 R7C12C.C1 to R7C12C.F1 RTAVR/S1/SLICE_150
ROUTE 12 5.384 R7C12C.F1 to R2C12D.CE RTAVR/S1/n1113 (to CLK0_OUT)
--------
64.929 (33.9% logic, 66.1% route), 21 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/SLICE_683:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R4C7C.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/S1/SLICE_330:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R2C12D.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 17.834ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s2_DOBH_rep_6 (from CLK0_OUT +)
Destination: FF Data in RTAVR/S1/r_pc_i0_i0 (to CLK0_OUT +)
Delay: 64.929ns (33.9% logic, 66.1% route), 21 logic levels.
Constraint Details:
64.929ns physical path delay RTAVR/SLICE_683 to RTAVR/S1/SLICE_328 meets
83.333ns delay constraint less
0.000ns skew and
0.570ns CE_SET requirement (totaling 82.763ns) by 17.834ns
Physical Path Details:
Data path RTAVR/SLICE_683 to RTAVR/S1/SLICE_328:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R4C7C.CLK to R4C7C.Q1 RTAVR/SLICE_683 (from CLK0_OUT)
ROUTE 8 5.665 R4C7C.Q1 to R8C17A.C1 RTAVR/GPR/n1441
CTOF_DEL --- 0.923 R8C17A.C1 to R8C17A.F1 RTAVR/SLICE_516
ROUTE 3 1.569 R8C17A.F1 to R7C17A.D1 RTAVR/GPR_DOBH_0
CTOF_DEL --- 0.923 R7C17A.D1 to R7C17A.F1 RTAVR/SLICE_357
ROUTE 1 2.931 R7C17A.F1 to R7C20A.A1 RTAVR/ALU_RR_0
C1TOFCO_DE --- 1.795 R7C20A.A1 to R7C20A.FCO RTAVR/ALU/SLICE_61
ROUTE 1 0.000 R7C20A.FCO to R7C20B.FCI RTAVR/ALU/n9841
FCITOF0_DE --- 1.181 R7C20B.FCI to R7C20B.F0 RTAVR/ALU/SLICE_60
ROUTE 2 1.835 R7C20B.F0 to R9C20B.C0 RTAVR/ALU/n108
C0TOFCO_DE --- 2.064 R9C20B.C0 to R9C20B.FCO RTAVR/ALU/SLICE_70
ROUTE 1 0.000 R9C20B.FCO to R9C20C.FCI RTAVR/ALU/n9870
FCITOF1_DE --- 1.298 R9C20C.FCI to R9C20C.F1 RTAVR/ALU/SLICE_69
ROUTE 1 3.175 R9C20C.F1 to R7C18A.D1 RTAVR/ALU/n115
CTOOFX_DEL --- 1.359 R7C18A.D1 to R7C18A.OFX0 RTAVR/ALU/i10583/SLICE_460
ROUTE 1 0.000 R7C18A.OFX0 to R7C18A.FXB RTAVR/ALU/n11026
FXTOOFX_DE --- 0.478 R7C18A.FXB to R7C18A.OFX1 RTAVR/ALU/i10583/SLICE_460
ROUTE 2 3.375 R7C18A.OFX1 to R9C12D.A1 RTAVR/ALU_OUT_4
CTOF_DEL --- 0.923 R9C12D.A1 to R9C12D.F1 SLICE_621
ROUTE 1 1.482 R9C12D.F1 to R9C12B.D0 RTAVR/ALU/n12000
CTOF_DEL --- 0.923 R9C12B.D0 to R9C12B.F0 SLICE_622
ROUTE 1 1.002 R9C12B.F0 to R9C12B.C1 RTAVR/ALU/n12001
CTOF_DEL --- 0.923 R9C12B.C1 to R9C12B.F1 SLICE_622
ROUTE 1 1.488 R9C12B.F1 to R8C12C.D0 RTAVR/n10825
CTOF_DEL --- 0.923 R8C12C.D0 to R8C12C.F0 RTAVR/SLICE_488
ROUTE 1 1.002 R8C12C.F0 to R8C12C.C1 RTAVR/n4_adj_76
CTOF_DEL --- 0.923 R8C12C.C1 to R8C12C.F1 RTAVR/SLICE_488
ROUTE 2 2.649 R8C12C.F1 to R4C12D.D0 RTAVR/FLAGS_OUT_1
CTOOFX_DEL --- 1.359 R4C12D.D0 to R4C12D.OFX0 RTAVR/i1716/MUX41A/MUX21/SLICE_426
ROUTE 1 0.000 R4C12D.OFX0 to R4C12C.FXA RTAVR/i1716/FXA
FXTOOFX_DE --- 0.478 R4C12C.FXA to R4C12C.OFX1 RTAVR/i1716/MUX41B/MUX21/SLICE_427
ROUTE 2 2.642 R4C12C.OFX1 to R2C18C.D0 RTAVR/v_flags_bit
CTOF_DEL --- 0.923 R2C18C.D0 to R2C18C.F0 RTAVR/S1/SLICE_550
ROUTE 1 1.002 R2C18C.F0 to R2C18C.C1 RTAVR/S1/n15
CTOF_DEL --- 0.923 R2C18C.C1 to R2C18C.F1 RTAVR/S1/SLICE_550
ROUTE 2 4.269 R2C18C.F1 to R7C14C.D0 RTAVR/S1/n79
CTOF_DEL --- 0.923 R7C14C.D0 to R7C14C.F0 RTAVR/S1/SLICE_560
ROUTE 2 2.333 R7C14C.F0 to R7C12C.A0 RTAVR/S1/s0_inv_jump
CTOF_DEL --- 0.923 R7C12C.A0 to R7C12C.F0 RTAVR/S1/SLICE_150
ROUTE 3 1.083 R7C12C.F0 to R7C12C.C1 RTAVR/S1/v_int
CTOF_DEL --- 0.923 R7C12C.C1 to R7C12C.F1 RTAVR/S1/SLICE_150
ROUTE 12 5.384 R7C12C.F1 to R2C12C.CE RTAVR/S1/n1113 (to CLK0_OUT)
--------
64.929 (33.9% logic, 66.1% route), 21 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/SLICE_683:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R4C7C.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/S1/SLICE_328:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R2C12C.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 17.834ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s2_DOBH_rep_6 (from CLK0_OUT +)
Destination: FF Data in RTAVR/S1/r_pc_i0_i8 (to CLK0_OUT +)
Delay: 64.929ns (33.9% logic, 66.1% route), 21 logic levels.
Constraint Details:
64.929ns physical path delay RTAVR/SLICE_683 to RTAVR/S1/SLICE_336 meets
83.333ns delay constraint less
0.000ns skew and
0.570ns CE_SET requirement (totaling 82.763ns) by 17.834ns
Physical Path Details:
Data path RTAVR/SLICE_683 to RTAVR/S1/SLICE_336:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R4C7C.CLK to R4C7C.Q1 RTAVR/SLICE_683 (from CLK0_OUT)
ROUTE 8 5.665 R4C7C.Q1 to R8C17A.C1 RTAVR/GPR/n1441
CTOF_DEL --- 0.923 R8C17A.C1 to R8C17A.F1 RTAVR/SLICE_516
ROUTE 3 1.569 R8C17A.F1 to R7C17A.D1 RTAVR/GPR_DOBH_0
CTOF_DEL --- 0.923 R7C17A.D1 to R7C17A.F1 RTAVR/SLICE_357
ROUTE 1 2.931 R7C17A.F1 to R7C20A.A1 RTAVR/ALU_RR_0
C1TOFCO_DE --- 1.795 R7C20A.A1 to R7C20A.FCO RTAVR/ALU/SLICE_61
ROUTE 1 0.000 R7C20A.FCO to R7C20B.FCI RTAVR/ALU/n9841
FCITOF0_DE --- 1.181 R7C20B.FCI to R7C20B.F0 RTAVR/ALU/SLICE_60
ROUTE 2 1.835 R7C20B.F0 to R9C20B.C0 RTAVR/ALU/n108
C0TOFCO_DE --- 2.064 R9C20B.C0 to R9C20B.FCO RTAVR/ALU/SLICE_70
ROUTE 1 0.000 R9C20B.FCO to R9C20C.FCI RTAVR/ALU/n9870
FCITOF1_DE --- 1.298 R9C20C.FCI to R9C20C.F1 RTAVR/ALU/SLICE_69
ROUTE 1 3.175 R9C20C.F1 to R7C18A.D1 RTAVR/ALU/n115
CTOOFX_DEL --- 1.359 R7C18A.D1 to R7C18A.OFX0 RTAVR/ALU/i10583/SLICE_460
ROUTE 1 0.000 R7C18A.OFX0 to R7C18A.FXB RTAVR/ALU/n11026
FXTOOFX_DE --- 0.478 R7C18A.FXB to R7C18A.OFX1 RTAVR/ALU/i10583/SLICE_460
ROUTE 2 3.375 R7C18A.OFX1 to R9C12D.A1 RTAVR/ALU_OUT_4
CTOF_DEL --- 0.923 R9C12D.A1 to R9C12D.F1 SLICE_621
ROUTE 1 1.482 R9C12D.F1 to R9C12B.D0 RTAVR/ALU/n12000
CTOF_DEL --- 0.923 R9C12B.D0 to R9C12B.F0 SLICE_622
ROUTE 1 1.002 R9C12B.F0 to R9C12B.C1 RTAVR/ALU/n12001
CTOF_DEL --- 0.923 R9C12B.C1 to R9C12B.F1 SLICE_622
ROUTE 1 1.488 R9C12B.F1 to R8C12C.D0 RTAVR/n10825
CTOF_DEL --- 0.923 R8C12C.D0 to R8C12C.F0 RTAVR/SLICE_488
ROUTE 1 1.002 R8C12C.F0 to R8C12C.C1 RTAVR/n4_adj_76
CTOF_DEL --- 0.923 R8C12C.C1 to R8C12C.F1 RTAVR/SLICE_488
ROUTE 2 2.649 R8C12C.F1 to R4C12D.D0 RTAVR/FLAGS_OUT_1
CTOOFX_DEL --- 1.359 R4C12D.D0 to R4C12D.OFX0 RTAVR/i1716/MUX41A/MUX21/SLICE_426
ROUTE 1 0.000 R4C12D.OFX0 to R4C12C.FXA RTAVR/i1716/FXA
FXTOOFX_DE --- 0.478 R4C12C.FXA to R4C12C.OFX1 RTAVR/i1716/MUX41B/MUX21/SLICE_427
ROUTE 2 2.642 R4C12C.OFX1 to R2C18C.D0 RTAVR/v_flags_bit
CTOF_DEL --- 0.923 R2C18C.D0 to R2C18C.F0 RTAVR/S1/SLICE_550
ROUTE 1 1.002 R2C18C.F0 to R2C18C.C1 RTAVR/S1/n15
CTOF_DEL --- 0.923 R2C18C.C1 to R2C18C.F1 RTAVR/S1/SLICE_550
ROUTE 2 4.269 R2C18C.F1 to R7C14C.D0 RTAVR/S1/n79
CTOF_DEL --- 0.923 R7C14C.D0 to R7C14C.F0 RTAVR/S1/SLICE_560
ROUTE 2 2.333 R7C14C.F0 to R7C12C.A0 RTAVR/S1/s0_inv_jump
CTOF_DEL --- 0.923 R7C12C.A0 to R7C12C.F0 RTAVR/S1/SLICE_150
ROUTE 3 1.083 R7C12C.F0 to R7C12C.C1 RTAVR/S1/v_int
CTOF_DEL --- 0.923 R7C12C.C1 to R7C12C.F1 RTAVR/S1/SLICE_150
ROUTE 12 5.384 R7C12C.F1 to R3C14A.CE RTAVR/S1/n1113 (to CLK0_OUT)
--------
64.929 (33.9% logic, 66.1% route), 21 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/SLICE_683:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R4C7C.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/S1/SLICE_336:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R3C14A.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 17.834ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s2_DOBH_rep_6 (from CLK0_OUT +)
Destination: FF Data in RTAVR/S1/r_pc_i0_i11 (to CLK0_OUT +)
Delay: 64.929ns (33.9% logic, 66.1% route), 21 logic levels.
Constraint Details:
64.929ns physical path delay RTAVR/SLICE_683 to RTAVR/S1/SLICE_352 meets
83.333ns delay constraint less
0.000ns skew and
0.570ns CE_SET requirement (totaling 82.763ns) by 17.834ns
Physical Path Details:
Data path RTAVR/SLICE_683 to RTAVR/S1/SLICE_352:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R4C7C.CLK to R4C7C.Q1 RTAVR/SLICE_683 (from CLK0_OUT)
ROUTE 8 5.665 R4C7C.Q1 to R8C17A.C1 RTAVR/GPR/n1441
CTOF_DEL --- 0.923 R8C17A.C1 to R8C17A.F1 RTAVR/SLICE_516
ROUTE 3 1.569 R8C17A.F1 to R7C17A.D1 RTAVR/GPR_DOBH_0
CTOF_DEL --- 0.923 R7C17A.D1 to R7C17A.F1 RTAVR/SLICE_357
ROUTE 1 2.931 R7C17A.F1 to R7C20A.A1 RTAVR/ALU_RR_0
C1TOFCO_DE --- 1.795 R7C20A.A1 to R7C20A.FCO RTAVR/ALU/SLICE_61
ROUTE 1 0.000 R7C20A.FCO to R7C20B.FCI RTAVR/ALU/n9841
FCITOF0_DE --- 1.181 R7C20B.FCI to R7C20B.F0 RTAVR/ALU/SLICE_60
ROUTE 2 1.835 R7C20B.F0 to R9C20B.C0 RTAVR/ALU/n108
C0TOFCO_DE --- 2.064 R9C20B.C0 to R9C20B.FCO RTAVR/ALU/SLICE_70
ROUTE 1 0.000 R9C20B.FCO to R9C20C.FCI RTAVR/ALU/n9870
FCITOF1_DE --- 1.298 R9C20C.FCI to R9C20C.F1 RTAVR/ALU/SLICE_69
ROUTE 1 3.175 R9C20C.F1 to R7C18A.D1 RTAVR/ALU/n115
CTOOFX_DEL --- 1.359 R7C18A.D1 to R7C18A.OFX0 RTAVR/ALU/i10583/SLICE_460
ROUTE 1 0.000 R7C18A.OFX0 to R7C18A.FXB RTAVR/ALU/n11026
FXTOOFX_DE --- 0.478 R7C18A.FXB to R7C18A.OFX1 RTAVR/ALU/i10583/SLICE_460
ROUTE 2 3.375 R7C18A.OFX1 to R9C12D.A1 RTAVR/ALU_OUT_4
CTOF_DEL --- 0.923 R9C12D.A1 to R9C12D.F1 SLICE_621
ROUTE 1 1.482 R9C12D.F1 to R9C12B.D0 RTAVR/ALU/n12000
CTOF_DEL --- 0.923 R9C12B.D0 to R9C12B.F0 SLICE_622
ROUTE 1 1.002 R9C12B.F0 to R9C12B.C1 RTAVR/ALU/n12001
CTOF_DEL --- 0.923 R9C12B.C1 to R9C12B.F1 SLICE_622
ROUTE 1 1.488 R9C12B.F1 to R8C12C.D0 RTAVR/n10825
CTOF_DEL --- 0.923 R8C12C.D0 to R8C12C.F0 RTAVR/SLICE_488
ROUTE 1 1.002 R8C12C.F0 to R8C12C.C1 RTAVR/n4_adj_76
CTOF_DEL --- 0.923 R8C12C.C1 to R8C12C.F1 RTAVR/SLICE_488
ROUTE 2 2.649 R8C12C.F1 to R4C12D.D0 RTAVR/FLAGS_OUT_1
CTOOFX_DEL --- 1.359 R4C12D.D0 to R4C12D.OFX0 RTAVR/i1716/MUX41A/MUX21/SLICE_426
ROUTE 1 0.000 R4C12D.OFX0 to R4C12C.FXA RTAVR/i1716/FXA
FXTOOFX_DE --- 0.478 R4C12C.FXA to R4C12C.OFX1 RTAVR/i1716/MUX41B/MUX21/SLICE_427
ROUTE 2 2.642 R4C12C.OFX1 to R2C18C.D0 RTAVR/v_flags_bit
CTOF_DEL --- 0.923 R2C18C.D0 to R2C18C.F0 RTAVR/S1/SLICE_550
ROUTE 1 1.002 R2C18C.F0 to R2C18C.C1 RTAVR/S1/n15
CTOF_DEL --- 0.923 R2C18C.C1 to R2C18C.F1 RTAVR/S1/SLICE_550
ROUTE 2 4.269 R2C18C.F1 to R7C14C.D0 RTAVR/S1/n79
CTOF_DEL --- 0.923 R7C14C.D0 to R7C14C.F0 RTAVR/S1/SLICE_560
ROUTE 2 2.333 R7C14C.F0 to R7C12C.A0 RTAVR/S1/s0_inv_jump
CTOF_DEL --- 0.923 R7C12C.A0 to R7C12C.F0 RTAVR/S1/SLICE_150
ROUTE 3 1.083 R7C12C.F0 to R7C12C.C1 RTAVR/S1/v_int
CTOF_DEL --- 0.923 R7C12C.C1 to R7C12C.F1 RTAVR/S1/SLICE_150
ROUTE 12 5.384 R7C12C.F1 to R2C15B.CE RTAVR/S1/n1113 (to CLK0_OUT)
--------
64.929 (33.9% logic, 66.1% route), 21 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/SLICE_683:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R4C7C.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/S1/SLICE_352:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R2C15B.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 17.834ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s2_DOBH_rep_6 (from CLK0_OUT +)
Destination: FF Data in RTAVR/S1/r_pc_i0_i7 (to CLK0_OUT +)
Delay: 64.929ns (33.9% logic, 66.1% route), 21 logic levels.
Constraint Details:
64.929ns physical path delay RTAVR/SLICE_683 to RTAVR/S1/SLICE_335 meets
83.333ns delay constraint less
0.000ns skew and
0.570ns CE_SET requirement (totaling 82.763ns) by 17.834ns
Physical Path Details:
Data path RTAVR/SLICE_683 to RTAVR/S1/SLICE_335:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R4C7C.CLK to R4C7C.Q1 RTAVR/SLICE_683 (from CLK0_OUT)
ROUTE 8 5.665 R4C7C.Q1 to R8C17A.C1 RTAVR/GPR/n1441
CTOF_DEL --- 0.923 R8C17A.C1 to R8C17A.F1 RTAVR/SLICE_516
ROUTE 3 1.569 R8C17A.F1 to R7C17A.D1 RTAVR/GPR_DOBH_0
CTOF_DEL --- 0.923 R7C17A.D1 to R7C17A.F1 RTAVR/SLICE_357
ROUTE 1 2.931 R7C17A.F1 to R7C20A.A1 RTAVR/ALU_RR_0
C1TOFCO_DE --- 1.795 R7C20A.A1 to R7C20A.FCO RTAVR/ALU/SLICE_61
ROUTE 1 0.000 R7C20A.FCO to R7C20B.FCI RTAVR/ALU/n9841
FCITOF0_DE --- 1.181 R7C20B.FCI to R7C20B.F0 RTAVR/ALU/SLICE_60
ROUTE 2 1.835 R7C20B.F0 to R9C20B.C0 RTAVR/ALU/n108
C0TOFCO_DE --- 2.064 R9C20B.C0 to R9C20B.FCO RTAVR/ALU/SLICE_70
ROUTE 1 0.000 R9C20B.FCO to R9C20C.FCI RTAVR/ALU/n9870
FCITOF1_DE --- 1.298 R9C20C.FCI to R9C20C.F1 RTAVR/ALU/SLICE_69
ROUTE 1 3.175 R9C20C.F1 to R7C18A.D1 RTAVR/ALU/n115
CTOOFX_DEL --- 1.359 R7C18A.D1 to R7C18A.OFX0 RTAVR/ALU/i10583/SLICE_460
ROUTE 1 0.000 R7C18A.OFX0 to R7C18A.FXB RTAVR/ALU/n11026
FXTOOFX_DE --- 0.478 R7C18A.FXB to R7C18A.OFX1 RTAVR/ALU/i10583/SLICE_460
ROUTE 2 3.375 R7C18A.OFX1 to R9C12D.A1 RTAVR/ALU_OUT_4
CTOF_DEL --- 0.923 R9C12D.A1 to R9C12D.F1 SLICE_621
ROUTE 1 1.482 R9C12D.F1 to R9C12B.D0 RTAVR/ALU/n12000
CTOF_DEL --- 0.923 R9C12B.D0 to R9C12B.F0 SLICE_622
ROUTE 1 1.002 R9C12B.F0 to R9C12B.C1 RTAVR/ALU/n12001
CTOF_DEL --- 0.923 R9C12B.C1 to R9C12B.F1 SLICE_622
ROUTE 1 1.488 R9C12B.F1 to R8C12C.D0 RTAVR/n10825
CTOF_DEL --- 0.923 R8C12C.D0 to R8C12C.F0 RTAVR/SLICE_488
ROUTE 1 1.002 R8C12C.F0 to R8C12C.C1 RTAVR/n4_adj_76
CTOF_DEL --- 0.923 R8C12C.C1 to R8C12C.F1 RTAVR/SLICE_488
ROUTE 2 2.649 R8C12C.F1 to R4C12D.D0 RTAVR/FLAGS_OUT_1
CTOOFX_DEL --- 1.359 R4C12D.D0 to R4C12D.OFX0 RTAVR/i1716/MUX41A/MUX21/SLICE_426
ROUTE 1 0.000 R4C12D.OFX0 to R4C12C.FXA RTAVR/i1716/FXA
FXTOOFX_DE --- 0.478 R4C12C.FXA to R4C12C.OFX1 RTAVR/i1716/MUX41B/MUX21/SLICE_427
ROUTE 2 2.642 R4C12C.OFX1 to R2C18C.D0 RTAVR/v_flags_bit
CTOF_DEL --- 0.923 R2C18C.D0 to R2C18C.F0 RTAVR/S1/SLICE_550
ROUTE 1 1.002 R2C18C.F0 to R2C18C.C1 RTAVR/S1/n15
CTOF_DEL --- 0.923 R2C18C.C1 to R2C18C.F1 RTAVR/S1/SLICE_550
ROUTE 2 4.269 R2C18C.F1 to R7C14C.D0 RTAVR/S1/n79
CTOF_DEL --- 0.923 R7C14C.D0 to R7C14C.F0 RTAVR/S1/SLICE_560
ROUTE 2 2.333 R7C14C.F0 to R7C12C.A0 RTAVR/S1/s0_inv_jump
CTOF_DEL --- 0.923 R7C12C.A0 to R7C12C.F0 RTAVR/S1/SLICE_150
ROUTE 3 1.083 R7C12C.F0 to R7C12C.C1 RTAVR/S1/v_int
CTOF_DEL --- 0.923 R7C12C.C1 to R7C12C.F1 RTAVR/S1/SLICE_150
ROUTE 12 5.384 R7C12C.F1 to R3C14D.CE RTAVR/S1/n1113 (to CLK0_OUT)
--------
64.929 (33.9% logic, 66.1% route), 21 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/SLICE_683:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R4C7C.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/S1/SLICE_335:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R3C14D.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 17.834ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s2_DOBH_rep_6 (from CLK0_OUT +)
Destination: FF Data in RTAVR/S1/r_pc_i0_i1 (to CLK0_OUT +)
Delay: 64.929ns (33.9% logic, 66.1% route), 21 logic levels.
Constraint Details:
64.929ns physical path delay RTAVR/SLICE_683 to RTAVR/S1/SLICE_329 meets
83.333ns delay constraint less
0.000ns skew and
0.570ns CE_SET requirement (totaling 82.763ns) by 17.834ns
Physical Path Details:
Data path RTAVR/SLICE_683 to RTAVR/S1/SLICE_329:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R4C7C.CLK to R4C7C.Q1 RTAVR/SLICE_683 (from CLK0_OUT)
ROUTE 8 5.665 R4C7C.Q1 to R8C17A.C1 RTAVR/GPR/n1441
CTOF_DEL --- 0.923 R8C17A.C1 to R8C17A.F1 RTAVR/SLICE_516
ROUTE 3 1.569 R8C17A.F1 to R7C17A.D1 RTAVR/GPR_DOBH_0
CTOF_DEL --- 0.923 R7C17A.D1 to R7C17A.F1 RTAVR/SLICE_357
ROUTE 1 2.931 R7C17A.F1 to R7C20A.A1 RTAVR/ALU_RR_0
C1TOFCO_DE --- 1.795 R7C20A.A1 to R7C20A.FCO RTAVR/ALU/SLICE_61
ROUTE 1 0.000 R7C20A.FCO to R7C20B.FCI RTAVR/ALU/n9841
FCITOF0_DE --- 1.181 R7C20B.FCI to R7C20B.F0 RTAVR/ALU/SLICE_60
ROUTE 2 1.835 R7C20B.F0 to R9C20B.C0 RTAVR/ALU/n108
C0TOFCO_DE --- 2.064 R9C20B.C0 to R9C20B.FCO RTAVR/ALU/SLICE_70
ROUTE 1 0.000 R9C20B.FCO to R9C20C.FCI RTAVR/ALU/n9870
FCITOF1_DE --- 1.298 R9C20C.FCI to R9C20C.F1 RTAVR/ALU/SLICE_69
ROUTE 1 3.175 R9C20C.F1 to R7C18A.D1 RTAVR/ALU/n115
CTOOFX_DEL --- 1.359 R7C18A.D1 to R7C18A.OFX0 RTAVR/ALU/i10583/SLICE_460
ROUTE 1 0.000 R7C18A.OFX0 to R7C18A.FXB RTAVR/ALU/n11026
FXTOOFX_DE --- 0.478 R7C18A.FXB to R7C18A.OFX1 RTAVR/ALU/i10583/SLICE_460
ROUTE 2 3.375 R7C18A.OFX1 to R9C12D.A1 RTAVR/ALU_OUT_4
CTOF_DEL --- 0.923 R9C12D.A1 to R9C12D.F1 SLICE_621
ROUTE 1 1.482 R9C12D.F1 to R9C12B.D0 RTAVR/ALU/n12000
CTOF_DEL --- 0.923 R9C12B.D0 to R9C12B.F0 SLICE_622
ROUTE 1 1.002 R9C12B.F0 to R9C12B.C1 RTAVR/ALU/n12001
CTOF_DEL --- 0.923 R9C12B.C1 to R9C12B.F1 SLICE_622
ROUTE 1 1.488 R9C12B.F1 to R8C12C.D0 RTAVR/n10825
CTOF_DEL --- 0.923 R8C12C.D0 to R8C12C.F0 RTAVR/SLICE_488
ROUTE 1 1.002 R8C12C.F0 to R8C12C.C1 RTAVR/n4_adj_76
CTOF_DEL --- 0.923 R8C12C.C1 to R8C12C.F1 RTAVR/SLICE_488
ROUTE 2 2.649 R8C12C.F1 to R4C12D.D0 RTAVR/FLAGS_OUT_1
CTOOFX_DEL --- 1.359 R4C12D.D0 to R4C12D.OFX0 RTAVR/i1716/MUX41A/MUX21/SLICE_426
ROUTE 1 0.000 R4C12D.OFX0 to R4C12C.FXA RTAVR/i1716/FXA
FXTOOFX_DE --- 0.478 R4C12C.FXA to R4C12C.OFX1 RTAVR/i1716/MUX41B/MUX21/SLICE_427
ROUTE 2 2.642 R4C12C.OFX1 to R2C18C.D0 RTAVR/v_flags_bit
CTOF_DEL --- 0.923 R2C18C.D0 to R2C18C.F0 RTAVR/S1/SLICE_550
ROUTE 1 1.002 R2C18C.F0 to R2C18C.C1 RTAVR/S1/n15
CTOF_DEL --- 0.923 R2C18C.C1 to R2C18C.F1 RTAVR/S1/SLICE_550
ROUTE 2 4.269 R2C18C.F1 to R7C14C.D0 RTAVR/S1/n79
CTOF_DEL --- 0.923 R7C14C.D0 to R7C14C.F0 RTAVR/S1/SLICE_560
ROUTE 2 2.333 R7C14C.F0 to R7C12C.A0 RTAVR/S1/s0_inv_jump
CTOF_DEL --- 0.923 R7C12C.A0 to R7C12C.F0 RTAVR/S1/SLICE_150
ROUTE 3 1.083 R7C12C.F0 to R7C12C.C1 RTAVR/S1/v_int
CTOF_DEL --- 0.923 R7C12C.C1 to R7C12C.F1 RTAVR/S1/SLICE_150
ROUTE 12 5.384 R7C12C.F1 to R3C13D.CE RTAVR/S1/n1113 (to CLK0_OUT)
--------
64.929 (33.9% logic, 66.1% route), 21 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/SLICE_683:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R4C7C.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/S1/SLICE_329:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R3C13D.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 17.834ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s2_DOBH_rep_6 (from CLK0_OUT +)
Destination: FF Data in RTAVR/S1/r_pc_i0_i5 (to CLK0_OUT +)
Delay: 64.929ns (33.9% logic, 66.1% route), 21 logic levels.
Constraint Details:
64.929ns physical path delay RTAVR/SLICE_683 to RTAVR/S1/SLICE_333 meets
83.333ns delay constraint less
0.000ns skew and
0.570ns CE_SET requirement (totaling 82.763ns) by 17.834ns
Physical Path Details:
Data path RTAVR/SLICE_683 to RTAVR/S1/SLICE_333:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R4C7C.CLK to R4C7C.Q1 RTAVR/SLICE_683 (from CLK0_OUT)
ROUTE 8 5.665 R4C7C.Q1 to R8C17A.C1 RTAVR/GPR/n1441
CTOF_DEL --- 0.923 R8C17A.C1 to R8C17A.F1 RTAVR/SLICE_516
ROUTE 3 1.569 R8C17A.F1 to R7C17A.D1 RTAVR/GPR_DOBH_0
CTOF_DEL --- 0.923 R7C17A.D1 to R7C17A.F1 RTAVR/SLICE_357
ROUTE 1 2.931 R7C17A.F1 to R7C20A.A1 RTAVR/ALU_RR_0
C1TOFCO_DE --- 1.795 R7C20A.A1 to R7C20A.FCO RTAVR/ALU/SLICE_61
ROUTE 1 0.000 R7C20A.FCO to R7C20B.FCI RTAVR/ALU/n9841
FCITOF0_DE --- 1.181 R7C20B.FCI to R7C20B.F0 RTAVR/ALU/SLICE_60
ROUTE 2 1.835 R7C20B.F0 to R9C20B.C0 RTAVR/ALU/n108
C0TOFCO_DE --- 2.064 R9C20B.C0 to R9C20B.FCO RTAVR/ALU/SLICE_70
ROUTE 1 0.000 R9C20B.FCO to R9C20C.FCI RTAVR/ALU/n9870
FCITOF1_DE --- 1.298 R9C20C.FCI to R9C20C.F1 RTAVR/ALU/SLICE_69
ROUTE 1 3.175 R9C20C.F1 to R7C18A.D1 RTAVR/ALU/n115
CTOOFX_DEL --- 1.359 R7C18A.D1 to R7C18A.OFX0 RTAVR/ALU/i10583/SLICE_460
ROUTE 1 0.000 R7C18A.OFX0 to R7C18A.FXB RTAVR/ALU/n11026
FXTOOFX_DE --- 0.478 R7C18A.FXB to R7C18A.OFX1 RTAVR/ALU/i10583/SLICE_460
ROUTE 2 3.375 R7C18A.OFX1 to R9C12D.A1 RTAVR/ALU_OUT_4
CTOF_DEL --- 0.923 R9C12D.A1 to R9C12D.F1 SLICE_621
ROUTE 1 1.482 R9C12D.F1 to R9C12B.D0 RTAVR/ALU/n12000
CTOF_DEL --- 0.923 R9C12B.D0 to R9C12B.F0 SLICE_622
ROUTE 1 1.002 R9C12B.F0 to R9C12B.C1 RTAVR/ALU/n12001
CTOF_DEL --- 0.923 R9C12B.C1 to R9C12B.F1 SLICE_622
ROUTE 1 1.488 R9C12B.F1 to R8C12C.D0 RTAVR/n10825
CTOF_DEL --- 0.923 R8C12C.D0 to R8C12C.F0 RTAVR/SLICE_488
ROUTE 1 1.002 R8C12C.F0 to R8C12C.C1 RTAVR/n4_adj_76
CTOF_DEL --- 0.923 R8C12C.C1 to R8C12C.F1 RTAVR/SLICE_488
ROUTE 2 2.649 R8C12C.F1 to R4C12D.D0 RTAVR/FLAGS_OUT_1
CTOOFX_DEL --- 1.359 R4C12D.D0 to R4C12D.OFX0 RTAVR/i1716/MUX41A/MUX21/SLICE_426
ROUTE 1 0.000 R4C12D.OFX0 to R4C12C.FXA RTAVR/i1716/FXA
FXTOOFX_DE --- 0.478 R4C12C.FXA to R4C12C.OFX1 RTAVR/i1716/MUX41B/MUX21/SLICE_427
ROUTE 2 2.642 R4C12C.OFX1 to R2C18C.D0 RTAVR/v_flags_bit
CTOF_DEL --- 0.923 R2C18C.D0 to R2C18C.F0 RTAVR/S1/SLICE_550
ROUTE 1 1.002 R2C18C.F0 to R2C18C.C1 RTAVR/S1/n15
CTOF_DEL --- 0.923 R2C18C.C1 to R2C18C.F1 RTAVR/S1/SLICE_550
ROUTE 2 4.269 R2C18C.F1 to R7C14C.D0 RTAVR/S1/n79
CTOF_DEL --- 0.923 R7C14C.D0 to R7C14C.F0 RTAVR/S1/SLICE_560
ROUTE 2 2.333 R7C14C.F0 to R7C12C.A0 RTAVR/S1/s0_inv_jump
CTOF_DEL --- 0.923 R7C12C.A0 to R7C12C.F0 RTAVR/S1/SLICE_150
ROUTE 3 1.083 R7C12C.F0 to R7C12C.C1 RTAVR/S1/v_int
CTOF_DEL --- 0.923 R7C12C.C1 to R7C12C.F1 RTAVR/S1/SLICE_150
ROUTE 12 5.384 R7C12C.F1 to R2C12A.CE RTAVR/S1/n1113 (to CLK0_OUT)
--------
64.929 (33.9% logic, 66.1% route), 21 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/SLICE_683:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R4C7C.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/S1/SLICE_333:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R2C12A.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 17.834ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s2_DOBH_rep_6 (from CLK0_OUT +)
Destination: FF Data in RTAVR/S1/r_pc_i0_i9 (to CLK0_OUT +)
Delay: 64.929ns (33.9% logic, 66.1% route), 21 logic levels.
Constraint Details:
64.929ns physical path delay RTAVR/SLICE_683 to RTAVR/S1/SLICE_337 meets
83.333ns delay constraint less
0.000ns skew and
0.570ns CE_SET requirement (totaling 82.763ns) by 17.834ns
Physical Path Details:
Data path RTAVR/SLICE_683 to RTAVR/S1/SLICE_337:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R4C7C.CLK to R4C7C.Q1 RTAVR/SLICE_683 (from CLK0_OUT)
ROUTE 8 5.665 R4C7C.Q1 to R8C17A.C1 RTAVR/GPR/n1441
CTOF_DEL --- 0.923 R8C17A.C1 to R8C17A.F1 RTAVR/SLICE_516
ROUTE 3 1.569 R8C17A.F1 to R7C17A.D1 RTAVR/GPR_DOBH_0
CTOF_DEL --- 0.923 R7C17A.D1 to R7C17A.F1 RTAVR/SLICE_357
ROUTE 1 2.931 R7C17A.F1 to R7C20A.A1 RTAVR/ALU_RR_0
C1TOFCO_DE --- 1.795 R7C20A.A1 to R7C20A.FCO RTAVR/ALU/SLICE_61
ROUTE 1 0.000 R7C20A.FCO to R7C20B.FCI RTAVR/ALU/n9841
FCITOF0_DE --- 1.181 R7C20B.FCI to R7C20B.F0 RTAVR/ALU/SLICE_60
ROUTE 2 1.835 R7C20B.F0 to R9C20B.C0 RTAVR/ALU/n108
C0TOFCO_DE --- 2.064 R9C20B.C0 to R9C20B.FCO RTAVR/ALU/SLICE_70
ROUTE 1 0.000 R9C20B.FCO to R9C20C.FCI RTAVR/ALU/n9870
FCITOF1_DE --- 1.298 R9C20C.FCI to R9C20C.F1 RTAVR/ALU/SLICE_69
ROUTE 1 3.175 R9C20C.F1 to R7C18A.D1 RTAVR/ALU/n115
CTOOFX_DEL --- 1.359 R7C18A.D1 to R7C18A.OFX0 RTAVR/ALU/i10583/SLICE_460
ROUTE 1 0.000 R7C18A.OFX0 to R7C18A.FXB RTAVR/ALU/n11026
FXTOOFX_DE --- 0.478 R7C18A.FXB to R7C18A.OFX1 RTAVR/ALU/i10583/SLICE_460
ROUTE 2 3.375 R7C18A.OFX1 to R9C12D.A1 RTAVR/ALU_OUT_4
CTOF_DEL --- 0.923 R9C12D.A1 to R9C12D.F1 SLICE_621
ROUTE 1 1.482 R9C12D.F1 to R9C12B.D0 RTAVR/ALU/n12000
CTOF_DEL --- 0.923 R9C12B.D0 to R9C12B.F0 SLICE_622
ROUTE 1 1.002 R9C12B.F0 to R9C12B.C1 RTAVR/ALU/n12001
CTOF_DEL --- 0.923 R9C12B.C1 to R9C12B.F1 SLICE_622
ROUTE 1 1.488 R9C12B.F1 to R8C12C.D0 RTAVR/n10825
CTOF_DEL --- 0.923 R8C12C.D0 to R8C12C.F0 RTAVR/SLICE_488
ROUTE 1 1.002 R8C12C.F0 to R8C12C.C1 RTAVR/n4_adj_76
CTOF_DEL --- 0.923 R8C12C.C1 to R8C12C.F1 RTAVR/SLICE_488
ROUTE 2 2.649 R8C12C.F1 to R4C12D.D0 RTAVR/FLAGS_OUT_1
CTOOFX_DEL --- 1.359 R4C12D.D0 to R4C12D.OFX0 RTAVR/i1716/MUX41A/MUX21/SLICE_426
ROUTE 1 0.000 R4C12D.OFX0 to R4C12C.FXA RTAVR/i1716/FXA
FXTOOFX_DE --- 0.478 R4C12C.FXA to R4C12C.OFX1 RTAVR/i1716/MUX41B/MUX21/SLICE_427
ROUTE 2 2.642 R4C12C.OFX1 to R2C18C.D0 RTAVR/v_flags_bit
CTOF_DEL --- 0.923 R2C18C.D0 to R2C18C.F0 RTAVR/S1/SLICE_550
ROUTE 1 1.002 R2C18C.F0 to R2C18C.C1 RTAVR/S1/n15
CTOF_DEL --- 0.923 R2C18C.C1 to R2C18C.F1 RTAVR/S1/SLICE_550
ROUTE 2 4.269 R2C18C.F1 to R7C14C.D0 RTAVR/S1/n79
CTOF_DEL --- 0.923 R7C14C.D0 to R7C14C.F0 RTAVR/S1/SLICE_560
ROUTE 2 2.333 R7C14C.F0 to R7C12C.A0 RTAVR/S1/s0_inv_jump
CTOF_DEL --- 0.923 R7C12C.A0 to R7C12C.F0 RTAVR/S1/SLICE_150
ROUTE 3 1.083 R7C12C.F0 to R7C12C.C1 RTAVR/S1/v_int
CTOF_DEL --- 0.923 R7C12C.C1 to R7C12C.F1 RTAVR/S1/SLICE_150
ROUTE 12 5.384 R7C12C.F1 to R3C14B.CE RTAVR/S1/n1113 (to CLK0_OUT)
--------
64.929 (33.9% logic, 66.1% route), 21 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/SLICE_683:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R4C7C.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/S1/SLICE_337:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R3C14B.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 17.834ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s2_DOBH_rep_6 (from CLK0_OUT +)
Destination: FF Data in RTAVR/S1/r_pc_i0_i3 (to CLK0_OUT +)
Delay: 64.929ns (33.9% logic, 66.1% route), 21 logic levels.
Constraint Details:
64.929ns physical path delay RTAVR/SLICE_683 to RTAVR/S1/SLICE_331 meets
83.333ns delay constraint less
0.000ns skew and
0.570ns CE_SET requirement (totaling 82.763ns) by 17.834ns
Physical Path Details:
Data path RTAVR/SLICE_683 to RTAVR/S1/SLICE_331:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R4C7C.CLK to R4C7C.Q1 RTAVR/SLICE_683 (from CLK0_OUT)
ROUTE 8 5.665 R4C7C.Q1 to R8C17A.C1 RTAVR/GPR/n1441
CTOF_DEL --- 0.923 R8C17A.C1 to R8C17A.F1 RTAVR/SLICE_516
ROUTE 3 1.569 R8C17A.F1 to R7C17A.D1 RTAVR/GPR_DOBH_0
CTOF_DEL --- 0.923 R7C17A.D1 to R7C17A.F1 RTAVR/SLICE_357
ROUTE 1 2.931 R7C17A.F1 to R7C20A.A1 RTAVR/ALU_RR_0
C1TOFCO_DE --- 1.795 R7C20A.A1 to R7C20A.FCO RTAVR/ALU/SLICE_61
ROUTE 1 0.000 R7C20A.FCO to R7C20B.FCI RTAVR/ALU/n9841
FCITOF0_DE --- 1.181 R7C20B.FCI to R7C20B.F0 RTAVR/ALU/SLICE_60
ROUTE 2 1.835 R7C20B.F0 to R9C20B.C0 RTAVR/ALU/n108
C0TOFCO_DE --- 2.064 R9C20B.C0 to R9C20B.FCO RTAVR/ALU/SLICE_70
ROUTE 1 0.000 R9C20B.FCO to R9C20C.FCI RTAVR/ALU/n9870
FCITOF1_DE --- 1.298 R9C20C.FCI to R9C20C.F1 RTAVR/ALU/SLICE_69
ROUTE 1 3.175 R9C20C.F1 to R7C18A.D1 RTAVR/ALU/n115
CTOOFX_DEL --- 1.359 R7C18A.D1 to R7C18A.OFX0 RTAVR/ALU/i10583/SLICE_460
ROUTE 1 0.000 R7C18A.OFX0 to R7C18A.FXB RTAVR/ALU/n11026
FXTOOFX_DE --- 0.478 R7C18A.FXB to R7C18A.OFX1 RTAVR/ALU/i10583/SLICE_460
ROUTE 2 3.375 R7C18A.OFX1 to R9C12D.A1 RTAVR/ALU_OUT_4
CTOF_DEL --- 0.923 R9C12D.A1 to R9C12D.F1 SLICE_621
ROUTE 1 1.482 R9C12D.F1 to R9C12B.D0 RTAVR/ALU/n12000
CTOF_DEL --- 0.923 R9C12B.D0 to R9C12B.F0 SLICE_622
ROUTE 1 1.002 R9C12B.F0 to R9C12B.C1 RTAVR/ALU/n12001
CTOF_DEL --- 0.923 R9C12B.C1 to R9C12B.F1 SLICE_622
ROUTE 1 1.488 R9C12B.F1 to R8C12C.D0 RTAVR/n10825
CTOF_DEL --- 0.923 R8C12C.D0 to R8C12C.F0 RTAVR/SLICE_488
ROUTE 1 1.002 R8C12C.F0 to R8C12C.C1 RTAVR/n4_adj_76
CTOF_DEL --- 0.923 R8C12C.C1 to R8C12C.F1 RTAVR/SLICE_488
ROUTE 2 2.649 R8C12C.F1 to R4C12D.D0 RTAVR/FLAGS_OUT_1
CTOOFX_DEL --- 1.359 R4C12D.D0 to R4C12D.OFX0 RTAVR/i1716/MUX41A/MUX21/SLICE_426
ROUTE 1 0.000 R4C12D.OFX0 to R4C12C.FXA RTAVR/i1716/FXA
FXTOOFX_DE --- 0.478 R4C12C.FXA to R4C12C.OFX1 RTAVR/i1716/MUX41B/MUX21/SLICE_427
ROUTE 2 2.642 R4C12C.OFX1 to R2C18C.D0 RTAVR/v_flags_bit
CTOF_DEL --- 0.923 R2C18C.D0 to R2C18C.F0 RTAVR/S1/SLICE_550
ROUTE 1 1.002 R2C18C.F0 to R2C18C.C1 RTAVR/S1/n15
CTOF_DEL --- 0.923 R2C18C.C1 to R2C18C.F1 RTAVR/S1/SLICE_550
ROUTE 2 4.269 R2C18C.F1 to R7C14C.D0 RTAVR/S1/n79
CTOF_DEL --- 0.923 R7C14C.D0 to R7C14C.F0 RTAVR/S1/SLICE_560
ROUTE 2 2.333 R7C14C.F0 to R7C12C.A0 RTAVR/S1/s0_inv_jump
CTOF_DEL --- 0.923 R7C12C.A0 to R7C12C.F0 RTAVR/S1/SLICE_150
ROUTE 3 1.083 R7C12C.F0 to R7C12C.C1 RTAVR/S1/v_int
CTOF_DEL --- 0.923 R7C12C.C1 to R7C12C.F1 RTAVR/S1/SLICE_150
ROUTE 12 5.384 R7C12C.F1 to R2C12B.CE RTAVR/S1/n1113 (to CLK0_OUT)
--------
64.929 (33.9% logic, 66.1% route), 21 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/SLICE_683:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R4C7C.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/S1/SLICE_331:
Name Fanout Delay (ns) Site Resource
ROUTE 113 3.680 LPLL.CLKOP to R2C12B.CLK CLK0_OUT
--------
3.680 (0.0% logic, 100.0% route), 0 logic levels.
Report: 15.267MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "CLK90_OUT" 12.000000 MHz ;
2103 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 7.177ns (weighted slack = 14.354ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i1 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/r_do_i7 (to CLK90_OUT +)
Delay: 32.900ns (33.6% logic, 66.4% route), 11 logic levels.
Constraint Details:
32.900ns physical path delay ISP/SLICE_122 to RTAVR/IOR/SLICE_320 meets
41.667ns delay constraint less
1.158ns skew and
0.000ns feedback compensation and
0.432ns DIN_SET requirement (totaling 40.077ns) by 7.177ns
Physical Path Details:
Data path ISP/SLICE_122 to RTAVR/IOR/SLICE_320:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C3A.CLK to R10C3A.Q1 ISP/SLICE_122 (from CLK180_OUT)
ROUTE 5 3.932 R10C3A.Q1 to R7C8C.C1 ISP_ADDR_1
CTOF_DEL --- 0.923 R7C8C.C1 to R7C8C.F1 RTAVR/SLICE_389
ROUTE 49 3.502 R7C8C.F1 to R5C6C.D1 RTAVR/IOR_ADDRB_1
CTOF_DEL --- 0.923 R5C6C.D1 to R5C6C.F1 RTAVR/IOR/SLICE_585
ROUTE 11 2.642 R5C6C.F1 to R7C5B.C1 RTAVR/IOR/n8_adj_53
CTOF_DEL --- 0.923 R7C5B.C1 to R7C5B.F1 RTAVR/IOR/SLICE_593
ROUTE 7 2.548 R7C5B.F1 to R8C5B.B1 RTAVR/IOR/n11_adj_49
CTOF_DEL --- 0.923 R8C5B.B1 to R8C5B.F1 RTAVR/IOR/SLICE_648
ROUTE 1 1.488 R8C5B.F1 to R8C6B.D0 RTAVR/IOR/n115
CTOF_DEL --- 0.923 R8C6B.D0 to R8C6B.F0 RTAVR/IOR/SLICE_586
ROUTE 1 1.002 R8C6B.F0 to R8C6B.C1 RTAVR/IOR/n124
CTOF_DEL --- 0.923 R8C6B.C1 to R8C6B.F1 RTAVR/IOR/SLICE_586
ROUTE 1 0.765 R8C6B.F1 to R8C6A.D0 RTAVR/IOR/n133
CTOF_DEL --- 0.923 R8C6A.D0 to R8C6A.F0 RTAVR/IOR/SLICE_594
ROUTE 1 1.482 R8C6A.F0 to R8C6A.D1 RTAVR/IOR/n142
CTOF_DEL --- 0.923 R8C6A.D1 to R8C6A.F1 RTAVR/IOR/SLICE_594
ROUTE 1 2.284 R8C6A.F1 to R5C6B.D1 RTAVR/IOR/n151
CTOOFX_DEL --- 1.359 R5C6B.D1 to R5C6B.OFX0 RTAVR/IOR/mux_57_1452_1455_1458_1461_1464_1467_1470/MUX21/SLICE_441
ROUTE 1 2.198 R5C6B.OFX0 to R5C8C.D0 RTAVR/IOR/n178
CTOOFX_DEL --- 1.359 R5C8C.D0 to R5C8C.OFX0 RTAVR/IOR/SLICE_320
ROUTE 1 0.000 R5C8C.OFX0 to R5C8C.DI0 RTAVR/IOR/n214 (to CLK90_OUT)
--------
32.900 (33.6% logic, 66.4% route), 11 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_122:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C3A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/IOR/SLICE_320:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 3.680 LPLL.CLKOS to R5C8C.CLK CLK90_OUT
--------
-66.968 (112.3% logic, -12.3% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 7.418ns (weighted slack = 14.836ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i0 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/r_do_i7 (to CLK90_OUT +)
Delay: 32.659ns (33.9% logic, 66.1% route), 11 logic levels.
Constraint Details:
32.659ns physical path delay ISP/SLICE_122 to RTAVR/IOR/SLICE_320 meets
41.667ns delay constraint less
1.158ns skew and
0.000ns feedback compensation and
0.432ns DIN_SET requirement (totaling 40.077ns) by 7.418ns
Physical Path Details:
Data path ISP/SLICE_122 to RTAVR/IOR/SLICE_320:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C3A.CLK to R10C3A.Q0 ISP/SLICE_122 (from CLK180_OUT)
ROUTE 4 3.984 R10C3A.Q0 to R7C8C.C0 ISP_ADDR_0
CTOF_DEL --- 0.923 R7C8C.C0 to R7C8C.F0 RTAVR/SLICE_389
ROUTE 49 3.209 R7C8C.F0 to R5C6C.C1 RTAVR/IOR_ADDRB_0
CTOF_DEL --- 0.923 R5C6C.C1 to R5C6C.F1 RTAVR/IOR/SLICE_585
ROUTE 11 2.642 R5C6C.F1 to R7C5B.C1 RTAVR/IOR/n8_adj_53
CTOF_DEL --- 0.923 R7C5B.C1 to R7C5B.F1 RTAVR/IOR/SLICE_593
ROUTE 7 2.548 R7C5B.F1 to R8C5B.B1 RTAVR/IOR/n11_adj_49
CTOF_DEL --- 0.923 R8C5B.B1 to R8C5B.F1 RTAVR/IOR/SLICE_648
ROUTE 1 1.488 R8C5B.F1 to R8C6B.D0 RTAVR/IOR/n115
CTOF_DEL --- 0.923 R8C6B.D0 to R8C6B.F0 RTAVR/IOR/SLICE_586
ROUTE 1 1.002 R8C6B.F0 to R8C6B.C1 RTAVR/IOR/n124
CTOF_DEL --- 0.923 R8C6B.C1 to R8C6B.F1 RTAVR/IOR/SLICE_586
ROUTE 1 0.765 R8C6B.F1 to R8C6A.D0 RTAVR/IOR/n133
CTOF_DEL --- 0.923 R8C6A.D0 to R8C6A.F0 RTAVR/IOR/SLICE_594
ROUTE 1 1.482 R8C6A.F0 to R8C6A.D1 RTAVR/IOR/n142
CTOF_DEL --- 0.923 R8C6A.D1 to R8C6A.F1 RTAVR/IOR/SLICE_594
ROUTE 1 2.284 R8C6A.F1 to R5C6B.D1 RTAVR/IOR/n151
CTOOFX_DEL --- 1.359 R5C6B.D1 to R5C6B.OFX0 RTAVR/IOR/mux_57_1452_1455_1458_1461_1464_1467_1470/MUX21/SLICE_441
ROUTE 1 2.198 R5C6B.OFX0 to R5C8C.D0 RTAVR/IOR/n178
CTOOFX_DEL --- 1.359 R5C8C.D0 to R5C8C.OFX0 RTAVR/IOR/SLICE_320
ROUTE 1 0.000 R5C8C.OFX0 to R5C8C.DI0 RTAVR/IOR/n214 (to CLK90_OUT)
--------
32.659 (33.9% logic, 66.1% route), 11 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_122:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C3A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/IOR/SLICE_320:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 3.680 LPLL.CLKOS to R5C8C.CLK CLK90_OUT
--------
-66.968 (112.3% logic, -12.3% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 8.485ns (weighted slack = 16.970ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i2 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/r_do_i7 (to CLK90_OUT +)
Delay: 31.592ns (35.0% logic, 65.0% route), 11 logic levels.
Constraint Details:
31.592ns physical path delay ISP/SLICE_123 to RTAVR/IOR/SLICE_320 meets
41.667ns delay constraint less
1.158ns skew and
0.000ns feedback compensation and
0.432ns DIN_SET requirement (totaling 40.077ns) by 8.485ns
Physical Path Details:
Data path ISP/SLICE_123 to RTAVR/IOR/SLICE_320:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C3C.CLK to R10C3C.Q0 ISP/SLICE_123 (from CLK180_OUT)
ROUTE 10 3.544 R10C3C.Q0 to R4C6C.D1 ISP_ADDR_2
CTOF_DEL --- 0.923 R4C6C.D1 to R4C6C.F1 RTAVR/SLICE_569
ROUTE 41 2.582 R4C6C.F1 to R5C6C.A1 RTAVR/IOR_ADDRB_2
CTOF_DEL --- 0.923 R5C6C.A1 to R5C6C.F1 RTAVR/IOR/SLICE_585
ROUTE 11 2.642 R5C6C.F1 to R7C5B.C1 RTAVR/IOR/n8_adj_53
CTOF_DEL --- 0.923 R7C5B.C1 to R7C5B.F1 RTAVR/IOR/SLICE_593
ROUTE 7 2.548 R7C5B.F1 to R8C5B.B1 RTAVR/IOR/n11_adj_49
CTOF_DEL --- 0.923 R8C5B.B1 to R8C5B.F1 RTAVR/IOR/SLICE_648
ROUTE 1 1.488 R8C5B.F1 to R8C6B.D0 RTAVR/IOR/n115
CTOF_DEL --- 0.923 R8C6B.D0 to R8C6B.F0 RTAVR/IOR/SLICE_586
ROUTE 1 1.002 R8C6B.F0 to R8C6B.C1 RTAVR/IOR/n124
CTOF_DEL --- 0.923 R8C6B.C1 to R8C6B.F1 RTAVR/IOR/SLICE_586
ROUTE 1 0.765 R8C6B.F1 to R8C6A.D0 RTAVR/IOR/n133
CTOF_DEL --- 0.923 R8C6A.D0 to R8C6A.F0 RTAVR/IOR/SLICE_594
ROUTE 1 1.482 R8C6A.F0 to R8C6A.D1 RTAVR/IOR/n142
CTOF_DEL --- 0.923 R8C6A.D1 to R8C6A.F1 RTAVR/IOR/SLICE_594
ROUTE 1 2.284 R8C6A.F1 to R5C6B.D1 RTAVR/IOR/n151
CTOOFX_DEL --- 1.359 R5C6B.D1 to R5C6B.OFX0 RTAVR/IOR/mux_57_1452_1455_1458_1461_1464_1467_1470/MUX21/SLICE_441
ROUTE 1 2.198 R5C6B.OFX0 to R5C8C.D0 RTAVR/IOR/n178
CTOOFX_DEL --- 1.359 R5C8C.D0 to R5C8C.OFX0 RTAVR/IOR/SLICE_320
ROUTE 1 0.000 R5C8C.OFX0 to R5C8C.DI0 RTAVR/IOR/n214 (to CLK90_OUT)
--------
31.592 (35.0% logic, 65.0% route), 11 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_123:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C3C.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/IOR/SLICE_320:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 3.680 LPLL.CLKOS to R5C8C.CLK CLK90_OUT
--------
-66.968 (112.3% logic, -12.3% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 8.487ns (weighted slack = 16.974ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i1 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/r_do_i5 (to CLK90_OUT +)
Delay: 31.590ns (29.2% logic, 70.8% route), 9 logic levels.
Constraint Details:
31.590ns physical path delay ISP/SLICE_122 to RTAVR/IOR/SLICE_318 meets
41.667ns delay constraint less
1.158ns skew and
0.000ns feedback compensation and
0.432ns DIN_SET requirement (totaling 40.077ns) by 8.487ns
Physical Path Details:
Data path ISP/SLICE_122 to RTAVR/IOR/SLICE_318:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C3A.CLK to R10C3A.Q1 ISP/SLICE_122 (from CLK180_OUT)
ROUTE 5 3.932 R10C3A.Q1 to R7C8C.C1 ISP_ADDR_1
CTOF_DEL --- 0.923 R7C8C.C1 to R7C8C.F1 RTAVR/SLICE_389
ROUTE 49 3.502 R7C8C.F1 to R5C6C.D1 RTAVR/IOR_ADDRB_1
CTOF_DEL --- 0.923 R5C6C.D1 to R5C6C.F1 RTAVR/IOR/SLICE_585
ROUTE 11 2.642 R5C6C.F1 to R7C5B.C1 RTAVR/IOR/n8_adj_53
CTOF_DEL --- 0.923 R7C5B.C1 to R7C5B.F1 RTAVR/IOR/SLICE_593
ROUTE 7 3.466 R7C5B.F1 to R8C11D.A1 RTAVR/IOR/n11_adj_49
CTOF_DEL --- 0.923 R8C11D.A1 to R8C11D.F1 RTAVR/SLICE_407
ROUTE 1 2.532 R8C11D.F1 to R8C4A.D0 RTAVR/IOR/n117
CTOF_DEL --- 0.923 R8C4A.D0 to R8C4A.F0 RTAVR/IOR/SLICE_589
ROUTE 1 1.482 R8C4A.F0 to R8C4A.D1 RTAVR/IOR/n126
CTOF_DEL --- 0.923 R8C4A.D1 to R8C4A.F1 RTAVR/IOR/SLICE_589
ROUTE 1 3.264 R8C4A.F1 to R4C5D.D1 RTAVR/IOR/n153
CTOOFX_DEL --- 1.359 R4C5D.D1 to R4C5D.OFX0 RTAVR/IOR/mux_57_1452_1455_1458_1461_1464/MUX21/SLICE_443
ROUTE 1 1.559 R4C5D.OFX0 to R4C7A.D0 RTAVR/IOR/n180
CTOOFX_DEL --- 1.359 R4C7A.D0 to R4C7A.OFX0 RTAVR/IOR/SLICE_318
ROUTE 1 0.000 R4C7A.OFX0 to R4C7A.DI0 RTAVR/IOR/n216 (to CLK90_OUT)
--------
31.590 (29.2% logic, 70.8% route), 9 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_122:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C3A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/IOR/SLICE_318:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 3.680 LPLL.CLKOS to R4C7A.CLK CLK90_OUT
--------
-66.968 (112.3% logic, -12.3% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 8.728ns (weighted slack = 17.456ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i0 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/r_do_i5 (to CLK90_OUT +)
Delay: 31.349ns (29.4% logic, 70.6% route), 9 logic levels.
Constraint Details:
31.349ns physical path delay ISP/SLICE_122 to RTAVR/IOR/SLICE_318 meets
41.667ns delay constraint less
1.158ns skew and
0.000ns feedback compensation and
0.432ns DIN_SET requirement (totaling 40.077ns) by 8.728ns
Physical Path Details:
Data path ISP/SLICE_122 to RTAVR/IOR/SLICE_318:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C3A.CLK to R10C3A.Q0 ISP/SLICE_122 (from CLK180_OUT)
ROUTE 4 3.984 R10C3A.Q0 to R7C8C.C0 ISP_ADDR_0
CTOF_DEL --- 0.923 R7C8C.C0 to R7C8C.F0 RTAVR/SLICE_389
ROUTE 49 3.209 R7C8C.F0 to R5C6C.C1 RTAVR/IOR_ADDRB_0
CTOF_DEL --- 0.923 R5C6C.C1 to R5C6C.F1 RTAVR/IOR/SLICE_585
ROUTE 11 2.642 R5C6C.F1 to R7C5B.C1 RTAVR/IOR/n8_adj_53
CTOF_DEL --- 0.923 R7C5B.C1 to R7C5B.F1 RTAVR/IOR/SLICE_593
ROUTE 7 3.466 R7C5B.F1 to R8C11D.A1 RTAVR/IOR/n11_adj_49
CTOF_DEL --- 0.923 R8C11D.A1 to R8C11D.F1 RTAVR/SLICE_407
ROUTE 1 2.532 R8C11D.F1 to R8C4A.D0 RTAVR/IOR/n117
CTOF_DEL --- 0.923 R8C4A.D0 to R8C4A.F0 RTAVR/IOR/SLICE_589
ROUTE 1 1.482 R8C4A.F0 to R8C4A.D1 RTAVR/IOR/n126
CTOF_DEL --- 0.923 R8C4A.D1 to R8C4A.F1 RTAVR/IOR/SLICE_589
ROUTE 1 3.264 R8C4A.F1 to R4C5D.D1 RTAVR/IOR/n153
CTOOFX_DEL --- 1.359 R4C5D.D1 to R4C5D.OFX0 RTAVR/IOR/mux_57_1452_1455_1458_1461_1464/MUX21/SLICE_443
ROUTE 1 1.559 R4C5D.OFX0 to R4C7A.D0 RTAVR/IOR/n180
CTOOFX_DEL --- 1.359 R4C7A.D0 to R4C7A.OFX0 RTAVR/IOR/SLICE_318
ROUTE 1 0.000 R4C7A.OFX0 to R4C7A.DI0 RTAVR/IOR/n216 (to CLK90_OUT)
--------
31.349 (29.4% logic, 70.6% route), 9 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_122:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C3A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/IOR/SLICE_318:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 3.680 LPLL.CLKOS to R4C7A.CLK CLK90_OUT
--------
-66.968 (112.3% logic, -12.3% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 8.801ns (weighted slack = 17.602ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i2 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/r_do_i7 (to CLK90_OUT +)
Delay: 31.276ns (35.4% logic, 64.6% route), 11 logic levels.
Constraint Details:
31.276ns physical path delay ISP/SLICE_123 to RTAVR/IOR/SLICE_320 meets
41.667ns delay constraint less
1.158ns skew and
0.000ns feedback compensation and
0.432ns DIN_SET requirement (totaling 40.077ns) by 8.801ns
Physical Path Details:
Data path ISP/SLICE_123 to RTAVR/IOR/SLICE_320:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C3C.CLK to R10C3C.Q0 ISP/SLICE_123 (from CLK180_OUT)
ROUTE 10 3.544 R10C3C.Q0 to R4C6C.D1 ISP_ADDR_2
CTOF_DEL --- 0.923 R4C6C.D1 to R4C6C.F1 RTAVR/SLICE_569
ROUTE 41 2.984 R4C6C.F1 to R7C8A.D1 RTAVR/IOR_ADDRB_2
CTOF_DEL --- 0.923 R7C8A.D1 to R7C8A.F1 RTAVR/SLICE_611
ROUTE 3 1.877 R7C8A.F1 to R7C6D.C1 RTAVR/IOR/n8_adj_54
CTOF_DEL --- 0.923 R7C6D.C1 to R7C6D.F1 RTAVR/IOR/SLICE_577
ROUTE 7 2.595 R7C6D.F1 to R8C5B.C1 RTAVR/IOR/n11_adj_48
CTOF_DEL --- 0.923 R8C5B.C1 to R8C5B.F1 RTAVR/IOR/SLICE_648
ROUTE 1 1.488 R8C5B.F1 to R8C6B.D0 RTAVR/IOR/n115
CTOF_DEL --- 0.923 R8C6B.D0 to R8C6B.F0 RTAVR/IOR/SLICE_586
ROUTE 1 1.002 R8C6B.F0 to R8C6B.C1 RTAVR/IOR/n124
CTOF_DEL --- 0.923 R8C6B.C1 to R8C6B.F1 RTAVR/IOR/SLICE_586
ROUTE 1 0.765 R8C6B.F1 to R8C6A.D0 RTAVR/IOR/n133
CTOF_DEL --- 0.923 R8C6A.D0 to R8C6A.F0 RTAVR/IOR/SLICE_594
ROUTE 1 1.482 R8C6A.F0 to R8C6A.D1 RTAVR/IOR/n142
CTOF_DEL --- 0.923 R8C6A.D1 to R8C6A.F1 RTAVR/IOR/SLICE_594
ROUTE 1 2.284 R8C6A.F1 to R5C6B.D1 RTAVR/IOR/n151
CTOOFX_DEL --- 1.359 R5C6B.D1 to R5C6B.OFX0 RTAVR/IOR/mux_57_1452_1455_1458_1461_1464_1467_1470/MUX21/SLICE_441
ROUTE 1 2.198 R5C6B.OFX0 to R5C8C.D0 RTAVR/IOR/n178
CTOOFX_DEL --- 1.359 R5C8C.D0 to R5C8C.OFX0 RTAVR/IOR/SLICE_320
ROUTE 1 0.000 R5C8C.OFX0 to R5C8C.DI0 RTAVR/IOR/n214 (to CLK90_OUT)
--------
31.276 (35.4% logic, 64.6% route), 11 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_123:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C3C.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/IOR/SLICE_320:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 3.680 LPLL.CLKOS to R5C8C.CLK CLK90_OUT
--------
-66.968 (112.3% logic, -12.3% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 8.889ns (weighted slack = 17.778ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i0 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/r_do_i7 (to CLK90_OUT +)
Delay: 31.188ns (35.5% logic, 64.5% route), 11 logic levels.
Constraint Details:
31.188ns physical path delay ISP/SLICE_122 to RTAVR/IOR/SLICE_320 meets
41.667ns delay constraint less
1.158ns skew and
0.000ns feedback compensation and
0.432ns DIN_SET requirement (totaling 40.077ns) by 8.889ns
Physical Path Details:
Data path ISP/SLICE_122 to RTAVR/IOR/SLICE_320:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C3A.CLK to R10C3A.Q0 ISP/SLICE_122 (from CLK180_OUT)
ROUTE 4 3.984 R10C3A.Q0 to R7C8C.C0 ISP_ADDR_0
CTOF_DEL --- 0.923 R7C8C.C0 to R7C8C.F0 RTAVR/SLICE_389
ROUTE 49 2.456 R7C8C.F0 to R7C8A.A1 RTAVR/IOR_ADDRB_0
CTOF_DEL --- 0.923 R7C8A.A1 to R7C8A.F1 RTAVR/SLICE_611
ROUTE 3 1.877 R7C8A.F1 to R7C6D.C1 RTAVR/IOR/n8_adj_54
CTOF_DEL --- 0.923 R7C6D.C1 to R7C6D.F1 RTAVR/IOR/SLICE_577
ROUTE 7 2.595 R7C6D.F1 to R8C5B.C1 RTAVR/IOR/n11_adj_48
CTOF_DEL --- 0.923 R8C5B.C1 to R8C5B.F1 RTAVR/IOR/SLICE_648
ROUTE 1 1.488 R8C5B.F1 to R8C6B.D0 RTAVR/IOR/n115
CTOF_DEL --- 0.923 R8C6B.D0 to R8C6B.F0 RTAVR/IOR/SLICE_586
ROUTE 1 1.002 R8C6B.F0 to R8C6B.C1 RTAVR/IOR/n124
CTOF_DEL --- 0.923 R8C6B.C1 to R8C6B.F1 RTAVR/IOR/SLICE_586
ROUTE 1 0.765 R8C6B.F1 to R8C6A.D0 RTAVR/IOR/n133
CTOF_DEL --- 0.923 R8C6A.D0 to R8C6A.F0 RTAVR/IOR/SLICE_594
ROUTE 1 1.482 R8C6A.F0 to R8C6A.D1 RTAVR/IOR/n142
CTOF_DEL --- 0.923 R8C6A.D1 to R8C6A.F1 RTAVR/IOR/SLICE_594
ROUTE 1 2.284 R8C6A.F1 to R5C6B.D1 RTAVR/IOR/n151
CTOOFX_DEL --- 1.359 R5C6B.D1 to R5C6B.OFX0 RTAVR/IOR/mux_57_1452_1455_1458_1461_1464_1467_1470/MUX21/SLICE_441
ROUTE 1 2.198 R5C6B.OFX0 to R5C8C.D0 RTAVR/IOR/n178
CTOOFX_DEL --- 1.359 R5C8C.D0 to R5C8C.OFX0 RTAVR/IOR/SLICE_320
ROUTE 1 0.000 R5C8C.OFX0 to R5C8C.DI0 RTAVR/IOR/n214 (to CLK90_OUT)
--------
31.188 (35.5% logic, 64.5% route), 11 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_122:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C3A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/IOR/SLICE_320:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 3.680 LPLL.CLKOS to R5C8C.CLK CLK90_OUT
--------
-66.968 (112.3% logic, -12.3% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 8.920ns (weighted slack = 17.840ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i1 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/r_do_i6 (to CLK90_OUT +)
Delay: 31.157ns (32.5% logic, 67.5% route), 10 logic levels.
Constraint Details:
31.157ns physical path delay ISP/SLICE_122 to RTAVR/IOR/SLICE_319 meets
41.667ns delay constraint less
1.158ns skew and
0.000ns feedback compensation and
0.432ns DIN_SET requirement (totaling 40.077ns) by 8.920ns
Physical Path Details:
Data path ISP/SLICE_122 to RTAVR/IOR/SLICE_319:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C3A.CLK to R10C3A.Q1 ISP/SLICE_122 (from CLK180_OUT)
ROUTE 5 3.932 R10C3A.Q1 to R7C8C.C1 ISP_ADDR_1
CTOF_DEL --- 0.923 R7C8C.C1 to R7C8C.F1 RTAVR/SLICE_389
ROUTE 49 3.502 R7C8C.F1 to R5C6C.D1 RTAVR/IOR_ADDRB_1
CTOF_DEL --- 0.923 R5C6C.D1 to R5C6C.F1 RTAVR/IOR/SLICE_585
ROUTE 11 2.642 R5C6C.F1 to R7C5B.C1 RTAVR/IOR/n8_adj_53
CTOF_DEL --- 0.923 R7C5B.C1 to R7C5B.F1 RTAVR/IOR/SLICE_593
ROUTE 7 1.203 R7C5B.F1 to R7C5D.C1 RTAVR/IOR/n11_adj_49
CTOF_DEL --- 0.923 R7C5D.C1 to R7C5D.F1 RTAVR/IOR/SLICE_649
ROUTE 1 2.221 R7C5D.F1 to R8C5A.A0 RTAVR/IOR/n116
CTOF_DEL --- 0.923 R8C5A.A0 to R8C5A.F0 RTAVR/IOR/SLICE_588
ROUTE 1 1.482 R8C5A.F0 to R8C5A.D1 RTAVR/IOR/n125
CTOF_DEL --- 0.923 R8C5A.D1 to R8C5A.F1 RTAVR/IOR/SLICE_588
ROUTE 1 2.284 R8C5A.F1 to R5C5B.D1 RTAVR/IOR/n134
CTOF_DEL --- 0.923 R5C5B.D1 to R5C5B.F1 RTAVR/IOR/SLICE_692
ROUTE 1 1.559 R5C5B.F1 to R3C5A.D1 RTAVR/IOR/n152
CTOOFX_DEL --- 1.359 R3C5A.D1 to R3C5A.OFX0 RTAVR/IOR/mux_57_1452_1455_1458_1461_1464_1467/MUX21/SLICE_442
ROUTE 1 2.198 R3C5A.OFX0 to R3C8B.D0 RTAVR/IOR/n179
CTOOFX_DEL --- 1.359 R3C8B.D0 to R3C8B.OFX0 RTAVR/IOR/SLICE_319
ROUTE 1 0.000 R3C8B.OFX0 to R3C8B.DI0 RTAVR/IOR/n215 (to CLK90_OUT)
--------
31.157 (32.5% logic, 67.5% route), 10 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_122:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C3A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/IOR/SLICE_319:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 3.680 LPLL.CLKOS to R3C8B.CLK CLK90_OUT
--------
-66.968 (112.3% logic, -12.3% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 9.161ns (weighted slack = 18.322ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i0 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/r_do_i6 (to CLK90_OUT +)
Delay: 30.916ns (32.8% logic, 67.2% route), 10 logic levels.
Constraint Details:
30.916ns physical path delay ISP/SLICE_122 to RTAVR/IOR/SLICE_319 meets
41.667ns delay constraint less
1.158ns skew and
0.000ns feedback compensation and
0.432ns DIN_SET requirement (totaling 40.077ns) by 9.161ns
Physical Path Details:
Data path ISP/SLICE_122 to RTAVR/IOR/SLICE_319:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C3A.CLK to R10C3A.Q0 ISP/SLICE_122 (from CLK180_OUT)
ROUTE 4 3.984 R10C3A.Q0 to R7C8C.C0 ISP_ADDR_0
CTOF_DEL --- 0.923 R7C8C.C0 to R7C8C.F0 RTAVR/SLICE_389
ROUTE 49 3.209 R7C8C.F0 to R5C6C.C1 RTAVR/IOR_ADDRB_0
CTOF_DEL --- 0.923 R5C6C.C1 to R5C6C.F1 RTAVR/IOR/SLICE_585
ROUTE 11 2.642 R5C6C.F1 to R7C5B.C1 RTAVR/IOR/n8_adj_53
CTOF_DEL --- 0.923 R7C5B.C1 to R7C5B.F1 RTAVR/IOR/SLICE_593
ROUTE 7 1.203 R7C5B.F1 to R7C5D.C1 RTAVR/IOR/n11_adj_49
CTOF_DEL --- 0.923 R7C5D.C1 to R7C5D.F1 RTAVR/IOR/SLICE_649
ROUTE 1 2.221 R7C5D.F1 to R8C5A.A0 RTAVR/IOR/n116
CTOF_DEL --- 0.923 R8C5A.A0 to R8C5A.F0 RTAVR/IOR/SLICE_588
ROUTE 1 1.482 R8C5A.F0 to R8C5A.D1 RTAVR/IOR/n125
CTOF_DEL --- 0.923 R8C5A.D1 to R8C5A.F1 RTAVR/IOR/SLICE_588
ROUTE 1 2.284 R8C5A.F1 to R5C5B.D1 RTAVR/IOR/n134
CTOF_DEL --- 0.923 R5C5B.D1 to R5C5B.F1 RTAVR/IOR/SLICE_692
ROUTE 1 1.559 R5C5B.F1 to R3C5A.D1 RTAVR/IOR/n152
CTOOFX_DEL --- 1.359 R3C5A.D1 to R3C5A.OFX0 RTAVR/IOR/mux_57_1452_1455_1458_1461_1464_1467/MUX21/SLICE_442
ROUTE 1 2.198 R3C5A.OFX0 to R3C8B.D0 RTAVR/IOR/n179
CTOOFX_DEL --- 1.359 R3C8B.D0 to R3C8B.OFX0 RTAVR/IOR/SLICE_319
ROUTE 1 0.000 R3C8B.OFX0 to R3C8B.DI0 RTAVR/IOR/n215 (to CLK90_OUT)
--------
30.916 (32.8% logic, 67.2% route), 10 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_122:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C3A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/IOR/SLICE_319:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 3.680 LPLL.CLKOS to R3C8B.CLK CLK90_OUT
--------
-66.968 (112.3% logic, -12.3% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 9.437ns (weighted slack = 18.874ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i1 (from CLK180_OUT -)
Destination: FF Data in RTAVR/IOR/r_do_i7 (to CLK90_OUT +)
Delay: 30.640ns (36.1% logic, 63.9% route), 11 logic levels.
Constraint Details:
30.640ns physical path delay ISP/SLICE_122 to RTAVR/IOR/SLICE_320 meets
41.667ns delay constraint less
1.158ns skew and
0.000ns feedback compensation and
0.432ns DIN_SET requirement (totaling 40.077ns) by 9.437ns
Physical Path Details:
Data path ISP/SLICE_122 to RTAVR/IOR/SLICE_320:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C3A.CLK to R10C3A.Q1 ISP/SLICE_122 (from CLK180_OUT)
ROUTE 5 3.932 R10C3A.Q1 to R7C8C.C1 ISP_ADDR_1
CTOF_DEL --- 0.923 R7C8C.C1 to R7C8C.F1 RTAVR/SLICE_389
ROUTE 49 1.960 R7C8C.F1 to R7C8A.C1 RTAVR/IOR_ADDRB_1
CTOF_DEL --- 0.923 R7C8A.C1 to R7C8A.F1 RTAVR/SLICE_611
ROUTE 3 1.877 R7C8A.F1 to R7C6D.C1 RTAVR/IOR/n8_adj_54
CTOF_DEL --- 0.923 R7C6D.C1 to R7C6D.F1 RTAVR/IOR/SLICE_577
ROUTE 7 2.595 R7C6D.F1 to R8C5B.C1 RTAVR/IOR/n11_adj_48
CTOF_DEL --- 0.923 R8C5B.C1 to R8C5B.F1 RTAVR/IOR/SLICE_648
ROUTE 1 1.488 R8C5B.F1 to R8C6B.D0 RTAVR/IOR/n115
CTOF_DEL --- 0.923 R8C6B.D0 to R8C6B.F0 RTAVR/IOR/SLICE_586
ROUTE 1 1.002 R8C6B.F0 to R8C6B.C1 RTAVR/IOR/n124
CTOF_DEL --- 0.923 R8C6B.C1 to R8C6B.F1 RTAVR/IOR/SLICE_586
ROUTE 1 0.765 R8C6B.F1 to R8C6A.D0 RTAVR/IOR/n133
CTOF_DEL --- 0.923 R8C6A.D0 to R8C6A.F0 RTAVR/IOR/SLICE_594
ROUTE 1 1.482 R8C6A.F0 to R8C6A.D1 RTAVR/IOR/n142
CTOF_DEL --- 0.923 R8C6A.D1 to R8C6A.F1 RTAVR/IOR/SLICE_594
ROUTE 1 2.284 R8C6A.F1 to R5C6B.D1 RTAVR/IOR/n151
CTOOFX_DEL --- 1.359 R5C6B.D1 to R5C6B.OFX0 RTAVR/IOR/mux_57_1452_1455_1458_1461_1464_1467_1470/MUX21/SLICE_441
ROUTE 1 2.198 R5C6B.OFX0 to R5C8C.D0 RTAVR/IOR/n178
CTOOFX_DEL --- 1.359 R5C8C.D0 to R5C8C.OFX0 RTAVR/IOR/SLICE_320
ROUTE 1 0.000 R5C8C.OFX0 to R5C8C.DI0 RTAVR/IOR/n214 (to CLK90_OUT)
--------
30.640 (36.1% logic, 63.9% route), 11 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_122:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C3A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/IOR/SLICE_320:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 3.680 LPLL.CLKOS to R5C8C.CLK CLK90_OUT
--------
-66.968 (112.3% logic, -12.3% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Report: 14.504MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.405ns (weighted slack = 12.810ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i8 (from CLK180_OUT -)
Destination: DP8KC Port RTAVR/GPR/gpr_lo_d10(ASIC) (to CLK270_OUT +)
Delay: 37.089ns (32.4% logic, 67.6% route), 13 logic levels.
Constraint Details:
37.089ns physical path delay ISP/SLICE_126 to RTAVR/GPR/gpr_lo_d10 meets
41.667ns delay constraint less
-1.662ns skew and
0.000ns feedback compensation and
-0.165ns DATA_SET requirement (totaling 43.494ns) by 6.405ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/GPR/gpr_lo_d10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q0 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.816 R10C4A.Q0 to R7C9D.C1 ISP_ADDR_8
CTOF_DEL --- 0.923 R7C9D.C1 to R7C9D.F1 RTAVR/SLICE_566
ROUTE 4 1.680 R7C9D.F1 to R7C7A.D0 RTAVR/RAM_ADDRB_8
CTOF_DEL --- 0.923 R7C7A.D0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 2.930 R8C7B.F0 to R8C14B.C1 RTAVR/IOR/i_usart/n494
CTOOFX_DEL --- 1.359 R8C14B.C1 to R8C14B.OFX0 RTAVR/SLICE_406
ROUTE 1 0.000 R8C14B.OFX0 to R8C14A.FXA RTAVR/n11073
FXTOOFX_DE --- 0.478 R8C14A.FXA to R8C14A.OFX1 RTAVR/i10679/SLICE_425
ROUTE 2 1.598 R8C14A.OFX1 to R7C14A.D0 RTAVR/GPR_DI_3
CTOF_DEL --- 0.923 R7C14A.D0 to R7C14A.F0 RTAVR/GPR/SLICE_186
ROUTE 4 2.643 R7C14A.F0 to EBR_R6C14.DIA3 RTAVR/GPR/DI2_AL_3 (to CLK270_OUT)
--------
37.089 (32.4% logic, 67.6% route), 13 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/GPR/gpr_lo_d10:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 3.954 LPLL.CLKOS3 to EBR_R6C14.CLKA CLK270_OUT
--------
-64.148 (113.3% logic, -13.3% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 6.834ns (weighted slack = 13.668ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i8 (from CLK180_OUT -)
Destination: FF Data in RTAVR/GPR/gpr_hi3/RAM1 (to CLK270_OUT +)
FF RTAVR/GPR/gpr_hi3/RAM1
Delay: 37.121ns (32.4% logic, 67.6% route), 14 logic levels.
Constraint Details:
37.121ns physical path delay ISP/SLICE_126 to RTAVR/GPR/gpr_hi3/SLICE_74 meets
41.667ns delay constraint less
-1.388ns skew and
0.000ns feedback compensation and
-0.900ns WD_SET requirement (totaling 43.955ns) by 6.834ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/GPR/gpr_hi3/SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q0 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.816 R10C4A.Q0 to R7C9D.C1 ISP_ADDR_8
CTOF_DEL --- 0.923 R7C9D.C1 to R7C9D.F1 RTAVR/SLICE_566
ROUTE 4 1.680 R7C9D.F1 to R7C7A.D0 RTAVR/RAM_ADDRB_8
CTOF_DEL --- 0.923 R7C7A.D0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 2.930 R8C7B.F0 to R8C14B.C1 RTAVR/IOR/i_usart/n494
CTOOFX_DEL --- 1.359 R8C14B.C1 to R8C14B.OFX0 RTAVR/SLICE_406
ROUTE 1 0.000 R8C14B.OFX0 to R8C14A.FXA RTAVR/n11073
FXTOOFX_DE --- 0.478 R8C14A.FXA to R8C14A.OFX1 RTAVR/i10679/SLICE_425
ROUTE 2 1.669 R8C14A.OFX1 to R10C14D.D1 RTAVR/GPR_DI_3
CTOF_DEL --- 0.923 R10C14D.D1 to R10C14D.F1 RTAVR/GPR/SLICE_654
ROUTE 3 2.604 R10C14D.F1 to R10C10C.D1 RTAVR/GPR/DI2_AH_3
ZERO_DEL --- 0.000 R10C10C.D1 to R10C10C.WDO3 RTAVR/GPR/gpr_hi3/SLICE_72
ROUTE 1 0.000 R10C10C.WDO3 to R10C10B.WD1 RTAVR/GPR/gpr_hi3/WD3_INT (to CLK270_OUT)
--------
37.121 (32.4% logic, 67.6% route), 14 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/GPR/gpr_hi3/SLICE_74:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 3.680 LPLL.CLKOS3 to R10C10B.WCK CLK270_OUT
--------
-64.422 (112.8% logic, -12.8% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 6.973ns (weighted slack = 13.946ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i8 (from CLK180_OUT -)
Destination: FF Data in RTAVR/GPR/gpr_lo_d01/RAM1 (to CLK270_OUT +)
FF RTAVR/GPR/gpr_lo_d01/RAM1
Delay: 36.982ns (32.5% logic, 67.5% route), 14 logic levels.
Constraint Details:
36.982ns physical path delay ISP/SLICE_126 to RTAVR/GPR/gpr_lo_d01/SLICE_80 meets
41.667ns delay constraint less
-1.388ns skew and
0.000ns feedback compensation and
-0.900ns WD_SET requirement (totaling 43.955ns) by 6.973ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/GPR/gpr_lo_d01/SLICE_80:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q0 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.816 R10C4A.Q0 to R7C9D.C1 ISP_ADDR_8
CTOF_DEL --- 0.923 R7C9D.C1 to R7C9D.F1 RTAVR/SLICE_566
ROUTE 4 1.680 R7C9D.F1 to R7C7A.D0 RTAVR/RAM_ADDRB_8
CTOF_DEL --- 0.923 R7C7A.D0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 2.930 R8C7B.F0 to R8C14B.C1 RTAVR/IOR/i_usart/n494
CTOOFX_DEL --- 1.359 R8C14B.C1 to R8C14B.OFX0 RTAVR/SLICE_406
ROUTE 1 0.000 R8C14B.OFX0 to R8C14A.FXA RTAVR/n11073
FXTOOFX_DE --- 0.478 R8C14A.FXA to R8C14A.OFX1 RTAVR/i10679/SLICE_425
ROUTE 2 1.598 R8C14A.OFX1 to R7C14A.D0 RTAVR/GPR_DI_3
CTOF_DEL --- 0.923 R7C14A.D0 to R7C14A.F0 RTAVR/GPR/SLICE_186
ROUTE 4 2.536 R7C14A.F0 to R7C13C.D1 RTAVR/GPR/DI2_AL_3
ZERO_DEL --- 0.000 R7C13C.D1 to R7C13C.WDO3 RTAVR/GPR/gpr_lo_d01/SLICE_78
ROUTE 1 0.000 R7C13C.WDO3 to R7C13B.WD1 RTAVR/GPR/gpr_lo_d01/WD3_INT (to CLK270_OUT)
--------
36.982 (32.5% logic, 67.5% route), 14 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/GPR/gpr_lo_d01/SLICE_80:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 3.680 LPLL.CLKOS3 to R7C13B.WCK CLK270_OUT
--------
-64.422 (112.8% logic, -12.8% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 6.981ns (weighted slack = 13.962ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i9 (from CLK180_OUT -)
Destination: DP8KC Port RTAVR/GPR/gpr_lo_d10(ASIC) (to CLK270_OUT +)
Delay: 36.513ns (32.9% logic, 67.1% route), 13 logic levels.
Constraint Details:
36.513ns physical path delay ISP/SLICE_126 to RTAVR/GPR/gpr_lo_d10 meets
41.667ns delay constraint less
-1.662ns skew and
0.000ns feedback compensation and
-0.165ns DATA_SET requirement (totaling 43.494ns) by 6.981ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/GPR/gpr_lo_d10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q1 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.221 R10C4A.Q1 to R7C7A.D1 ISP_ADDR_9
CTOF_DEL --- 0.923 R7C7A.D1 to R7C7A.F1 RTAVR/SLICE_533
ROUTE 4 1.699 R7C7A.F1 to R7C7A.B0 RTAVR/RAM_ADDRB_9
CTOF_DEL --- 0.923 R7C7A.B0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 2.930 R8C7B.F0 to R8C14B.C1 RTAVR/IOR/i_usart/n494
CTOOFX_DEL --- 1.359 R8C14B.C1 to R8C14B.OFX0 RTAVR/SLICE_406
ROUTE 1 0.000 R8C14B.OFX0 to R8C14A.FXA RTAVR/n11073
FXTOOFX_DE --- 0.478 R8C14A.FXA to R8C14A.OFX1 RTAVR/i10679/SLICE_425
ROUTE 2 1.598 R8C14A.OFX1 to R7C14A.D0 RTAVR/GPR_DI_3
CTOF_DEL --- 0.923 R7C14A.D0 to R7C14A.F0 RTAVR/GPR/SLICE_186
ROUTE 4 2.643 R7C14A.F0 to EBR_R6C14.DIA3 RTAVR/GPR/DI2_AL_3 (to CLK270_OUT)
--------
36.513 (32.9% logic, 67.1% route), 13 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/GPR/gpr_lo_d10:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 3.954 LPLL.CLKOS3 to EBR_R6C14.CLKA CLK270_OUT
--------
-64.148 (113.3% logic, -13.3% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 7.159ns (weighted slack = 14.318ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i8 (from CLK180_OUT -)
Destination: FF Data in RTAVR/GPR/gpr_hi2/RAM1 (to CLK270_OUT +)
FF RTAVR/GPR/gpr_hi2/RAM1
Delay: 36.796ns (32.7% logic, 67.3% route), 14 logic levels.
Constraint Details:
36.796ns physical path delay ISP/SLICE_126 to RTAVR/GPR/gpr_hi2/SLICE_98 meets
41.667ns delay constraint less
-1.388ns skew and
0.000ns feedback compensation and
-0.900ns WD_SET requirement (totaling 43.955ns) by 7.159ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/GPR/gpr_hi2/SLICE_98:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q0 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.816 R10C4A.Q0 to R7C9D.C1 ISP_ADDR_8
CTOF_DEL --- 0.923 R7C9D.C1 to R7C9D.F1 RTAVR/SLICE_566
ROUTE 4 1.680 R7C9D.F1 to R7C7A.D0 RTAVR/RAM_ADDRB_8
CTOF_DEL --- 0.923 R7C7A.D0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 2.930 R8C7B.F0 to R8C14B.C1 RTAVR/IOR/i_usart/n494
CTOOFX_DEL --- 1.359 R8C14B.C1 to R8C14B.OFX0 RTAVR/SLICE_406
ROUTE 1 0.000 R8C14B.OFX0 to R8C14A.FXA RTAVR/n11073
FXTOOFX_DE --- 0.478 R8C14A.FXA to R8C14A.OFX1 RTAVR/i10679/SLICE_425
ROUTE 2 1.669 R8C14A.OFX1 to R10C14D.D1 RTAVR/GPR_DI_3
CTOF_DEL --- 0.923 R10C14D.D1 to R10C14D.F1 RTAVR/GPR/SLICE_654
ROUTE 3 2.279 R10C14D.F1 to R10C11C.D1 RTAVR/GPR/DI2_AH_3
ZERO_DEL --- 0.000 R10C11C.D1 to R10C11C.WDO3 RTAVR/GPR/gpr_hi2/SLICE_96
ROUTE 1 0.000 R10C11C.WDO3 to R10C11B.WD1 RTAVR/GPR/gpr_hi2/WD3_INT (to CLK270_OUT)
--------
36.796 (32.7% logic, 67.3% route), 14 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/GPR/gpr_hi2/SLICE_98:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 3.680 LPLL.CLKOS3 to R10C11B.WCK CLK270_OUT
--------
-64.422 (112.8% logic, -12.8% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 7.190ns (weighted slack = 14.380ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i8 (from CLK180_OUT -)
Destination: FF Data in RTAVR/GPR/gpr_lo1/RAM1 (to CLK270_OUT +)
FF RTAVR/GPR/gpr_lo1/RAM1
Delay: 36.765ns (32.7% logic, 67.3% route), 14 logic levels.
Constraint Details:
36.765ns physical path delay ISP/SLICE_126 to RTAVR/GPR/gpr_lo1/SLICE_83 meets
41.667ns delay constraint less
-1.388ns skew and
0.000ns feedback compensation and
-0.900ns WD_SET requirement (totaling 43.955ns) by 7.190ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/GPR/gpr_lo1/SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q0 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.816 R10C4A.Q0 to R7C9D.C1 ISP_ADDR_8
CTOF_DEL --- 0.923 R7C9D.C1 to R7C9D.F1 RTAVR/SLICE_566
ROUTE 4 1.680 R7C9D.F1 to R7C7A.D0 RTAVR/RAM_ADDRB_8
CTOF_DEL --- 0.923 R7C7A.D0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 2.930 R8C7B.F0 to R8C14B.C1 RTAVR/IOR/i_usart/n494
CTOOFX_DEL --- 1.359 R8C14B.C1 to R8C14B.OFX0 RTAVR/SLICE_406
ROUTE 1 0.000 R8C14B.OFX0 to R8C14A.FXA RTAVR/n11073
FXTOOFX_DE --- 0.478 R8C14A.FXA to R8C14A.OFX1 RTAVR/i10679/SLICE_425
ROUTE 2 1.598 R8C14A.OFX1 to R7C14A.D0 RTAVR/GPR_DI_3
CTOF_DEL --- 0.923 R7C14A.D0 to R7C14A.F0 RTAVR/GPR/SLICE_186
ROUTE 4 2.319 R7C14A.F0 to R8C15C.D1 RTAVR/GPR/DI2_AL_3
ZERO_DEL --- 0.000 R8C15C.D1 to R8C15C.WDO3 RTAVR/GPR/gpr_lo1/SLICE_81
ROUTE 1 0.000 R8C15C.WDO3 to R8C15B.WD1 RTAVR/GPR/gpr_lo1/WD3_INT (to CLK270_OUT)
--------
36.765 (32.7% logic, 67.3% route), 14 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/GPR/gpr_lo1/SLICE_83:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 3.680 LPLL.CLKOS3 to R8C15B.WCK CLK270_OUT
--------
-64.422 (112.8% logic, -12.8% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 7.357ns (weighted slack = 14.714ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i10 (from CLK180_OUT -)
Destination: DP8KC Port RTAVR/GPR/gpr_lo_d10(ASIC) (to CLK270_OUT +)
Delay: 36.137ns (33.3% logic, 66.7% route), 13 logic levels.
Constraint Details:
36.137ns physical path delay ISP/SLICE_127 to RTAVR/GPR/gpr_lo_d10 meets
41.667ns delay constraint less
-1.662ns skew and
0.000ns feedback compensation and
-0.165ns DATA_SET requirement (totaling 43.494ns) by 7.357ns
Physical Path Details:
Data path ISP/SLICE_127 to RTAVR/GPR/gpr_lo_d10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R9C6C.CLK to R9C6C.Q0 ISP/SLICE_127 (from CLK180_OUT)
ROUTE 2 2.248 R9C6C.Q0 to R7C7C.D1 ISP_ADDR_10
CTOF_DEL --- 0.923 R7C7C.D1 to R7C7C.F1 RTAVR/SLICE_565
ROUTE 4 2.296 R7C7C.F1 to R7C7A.A0 RTAVR/RAM_ADDRB_10
CTOF_DEL --- 0.923 R7C7A.A0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 2.930 R8C7B.F0 to R8C14B.C1 RTAVR/IOR/i_usart/n494
CTOOFX_DEL --- 1.359 R8C14B.C1 to R8C14B.OFX0 RTAVR/SLICE_406
ROUTE 1 0.000 R8C14B.OFX0 to R8C14A.FXA RTAVR/n11073
FXTOOFX_DE --- 0.478 R8C14A.FXA to R8C14A.OFX1 RTAVR/i10679/SLICE_425
ROUTE 2 1.598 R8C14A.OFX1 to R7C14A.D0 RTAVR/GPR_DI_3
CTOF_DEL --- 0.923 R7C14A.D0 to R7C14A.F0 RTAVR/GPR/SLICE_186
ROUTE 4 2.643 R7C14A.F0 to EBR_R6C14.DIA3 RTAVR/GPR/DI2_AL_3 (to CLK270_OUT)
--------
36.137 (33.3% logic, 66.7% route), 13 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_127:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R9C6C.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/GPR/gpr_lo_d10:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 3.954 LPLL.CLKOS3 to EBR_R6C14.CLKA CLK270_OUT
--------
-64.148 (113.3% logic, -13.3% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 7.410ns (weighted slack = 14.820ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i9 (from CLK180_OUT -)
Destination: FF Data in RTAVR/GPR/gpr_hi3/RAM1 (to CLK270_OUT +)
FF RTAVR/GPR/gpr_hi3/RAM1
Delay: 36.545ns (32.9% logic, 67.1% route), 14 logic levels.
Constraint Details:
36.545ns physical path delay ISP/SLICE_126 to RTAVR/GPR/gpr_hi3/SLICE_74 meets
41.667ns delay constraint less
-1.388ns skew and
0.000ns feedback compensation and
-0.900ns WD_SET requirement (totaling 43.955ns) by 7.410ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/GPR/gpr_hi3/SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q1 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.221 R10C4A.Q1 to R7C7A.D1 ISP_ADDR_9
CTOF_DEL --- 0.923 R7C7A.D1 to R7C7A.F1 RTAVR/SLICE_533
ROUTE 4 1.699 R7C7A.F1 to R7C7A.B0 RTAVR/RAM_ADDRB_9
CTOF_DEL --- 0.923 R7C7A.B0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 2.930 R8C7B.F0 to R8C14B.C1 RTAVR/IOR/i_usart/n494
CTOOFX_DEL --- 1.359 R8C14B.C1 to R8C14B.OFX0 RTAVR/SLICE_406
ROUTE 1 0.000 R8C14B.OFX0 to R8C14A.FXA RTAVR/n11073
FXTOOFX_DE --- 0.478 R8C14A.FXA to R8C14A.OFX1 RTAVR/i10679/SLICE_425
ROUTE 2 1.669 R8C14A.OFX1 to R10C14D.D1 RTAVR/GPR_DI_3
CTOF_DEL --- 0.923 R10C14D.D1 to R10C14D.F1 RTAVR/GPR/SLICE_654
ROUTE 3 2.604 R10C14D.F1 to R10C10C.D1 RTAVR/GPR/DI2_AH_3
ZERO_DEL --- 0.000 R10C10C.D1 to R10C10C.WDO3 RTAVR/GPR/gpr_hi3/SLICE_72
ROUTE 1 0.000 R10C10C.WDO3 to R10C10B.WD1 RTAVR/GPR/gpr_hi3/WD3_INT (to CLK270_OUT)
--------
36.545 (32.9% logic, 67.1% route), 14 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/GPR/gpr_hi3/SLICE_74:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 3.680 LPLL.CLKOS3 to R10C10B.WCK CLK270_OUT
--------
-64.422 (112.8% logic, -12.8% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 7.549ns (weighted slack = 15.098ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i9 (from CLK180_OUT -)
Destination: FF Data in RTAVR/GPR/gpr_lo_d01/RAM1 (to CLK270_OUT +)
FF RTAVR/GPR/gpr_lo_d01/RAM1
Delay: 36.406ns (33.0% logic, 67.0% route), 14 logic levels.
Constraint Details:
36.406ns physical path delay ISP/SLICE_126 to RTAVR/GPR/gpr_lo_d01/SLICE_80 meets
41.667ns delay constraint less
-1.388ns skew and
0.000ns feedback compensation and
-0.900ns WD_SET requirement (totaling 43.955ns) by 7.549ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/GPR/gpr_lo_d01/SLICE_80:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q1 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.221 R10C4A.Q1 to R7C7A.D1 ISP_ADDR_9
CTOF_DEL --- 0.923 R7C7A.D1 to R7C7A.F1 RTAVR/SLICE_533
ROUTE 4 1.699 R7C7A.F1 to R7C7A.B0 RTAVR/RAM_ADDRB_9
CTOF_DEL --- 0.923 R7C7A.B0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 2.930 R8C7B.F0 to R8C14B.C1 RTAVR/IOR/i_usart/n494
CTOOFX_DEL --- 1.359 R8C14B.C1 to R8C14B.OFX0 RTAVR/SLICE_406
ROUTE 1 0.000 R8C14B.OFX0 to R8C14A.FXA RTAVR/n11073
FXTOOFX_DE --- 0.478 R8C14A.FXA to R8C14A.OFX1 RTAVR/i10679/SLICE_425
ROUTE 2 1.598 R8C14A.OFX1 to R7C14A.D0 RTAVR/GPR_DI_3
CTOF_DEL --- 0.923 R7C14A.D0 to R7C14A.F0 RTAVR/GPR/SLICE_186
ROUTE 4 2.536 R7C14A.F0 to R7C13C.D1 RTAVR/GPR/DI2_AL_3
ZERO_DEL --- 0.000 R7C13C.D1 to R7C13C.WDO3 RTAVR/GPR/gpr_lo_d01/SLICE_78
ROUTE 1 0.000 R7C13C.WDO3 to R7C13B.WD1 RTAVR/GPR/gpr_lo_d01/WD3_INT (to CLK270_OUT)
--------
36.406 (33.0% logic, 67.0% route), 14 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/GPR/gpr_lo_d01/SLICE_80:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 3.680 LPLL.CLKOS3 to R7C13B.WCK CLK270_OUT
--------
-64.422 (112.8% logic, -12.8% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Passed: The following path meets requirements by 7.735ns (weighted slack = 15.470ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ISP/r_pr_665__i9 (from CLK180_OUT -)
Destination: FF Data in RTAVR/GPR/gpr_hi2/RAM1 (to CLK270_OUT +)
FF RTAVR/GPR/gpr_hi2/RAM1
Delay: 36.220ns (33.2% logic, 66.8% route), 14 logic levels.
Constraint Details:
36.220ns physical path delay ISP/SLICE_126 to RTAVR/GPR/gpr_hi2/SLICE_98 meets
41.667ns delay constraint less
-1.388ns skew and
0.000ns feedback compensation and
-0.900ns WD_SET requirement (totaling 43.955ns) by 7.735ns
Physical Path Details:
Data path ISP/SLICE_126 to RTAVR/GPR/gpr_hi2/SLICE_98:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 R10C4A.CLK to R10C4A.Q1 ISP/SLICE_126 (from CLK180_OUT)
ROUTE 2 3.221 R10C4A.Q1 to R7C7A.D1 ISP_ADDR_9
CTOF_DEL --- 0.923 R7C7A.D1 to R7C7A.F1 RTAVR/SLICE_533
ROUTE 4 1.699 R7C7A.F1 to R7C7A.B0 RTAVR/RAM_ADDRB_9
CTOF_DEL --- 0.923 R7C7A.B0 to R7C7A.F0 RTAVR/SLICE_533
ROUTE 1 0.765 R7C7A.F0 to R7C7B.D0 RTAVR/n10_adj_78
CTOF_DEL --- 0.923 R7C7B.D0 to R7C7B.F0 RTAVR/SLICE_534
ROUTE 3 2.279 R7C7B.F0 to R7C9C.D1 RTAVR/n3154
CTOF_DEL --- 0.923 R7C9C.D1 to R7C9C.F1 RTAVR/SLICE_530
ROUTE 11 2.864 R7C9C.F1 to R8C3B.D1 RTAVR/n3155
CTOF_DEL --- 0.923 R8C3B.D1 to R8C3B.F1 RTAVR/SLICE_597
ROUTE 8 0.966 R8C3B.F1 to R8C3A.D0 RTAVR/IOR_WEB
CTOF_DEL --- 0.923 R8C3A.D0 to R8C3A.F0 RTAVR/IOR/SLICE_572
ROUTE 4 2.880 R8C3A.F0 to R8C7A.C0 RTAVR/IOR/WE_ucsrb
CTOF_DEL --- 0.923 R8C7A.C0 to R8C7A.F0 RTAVR/IOR/SLICE_605
ROUTE 3 1.563 R8C7A.F0 to R8C7B.D1 RTAVR/IOR/n363
CTOF_DEL --- 0.923 R8C7B.D1 to R8C7B.F1 RTAVR/IOR/SLICE_300
ROUTE 3 1.083 R8C7B.F1 to R8C7B.C0 RTAVR/IOR/n364
CTOF_DEL --- 0.923 R8C7B.C0 to R8C7B.F0 RTAVR/IOR/SLICE_300
ROUTE 8 2.930 R8C7B.F0 to R8C14B.C1 RTAVR/IOR/i_usart/n494
CTOOFX_DEL --- 1.359 R8C14B.C1 to R8C14B.OFX0 RTAVR/SLICE_406
ROUTE 1 0.000 R8C14B.OFX0 to R8C14A.FXA RTAVR/n11073
FXTOOFX_DE --- 0.478 R8C14A.FXA to R8C14A.OFX1 RTAVR/i10679/SLICE_425
ROUTE 2 1.669 R8C14A.OFX1 to R10C14D.D1 RTAVR/GPR_DI_3
CTOF_DEL --- 0.923 R10C14D.D1 to R10C14D.F1 RTAVR/GPR/SLICE_654
ROUTE 3 2.279 R10C14D.F1 to R10C11C.D1 RTAVR/GPR/DI2_AH_3
ZERO_DEL --- 0.000 R10C11C.D1 to R10C11C.WDO3 RTAVR/GPR/gpr_hi2/SLICE_96
ROUTE 1 0.000 R10C11C.WDO3 to R10C11B.WD1 RTAVR/GPR/gpr_hi2/WD3_INT (to CLK270_OUT)
--------
36.220 (33.2% logic, 66.8% route), 14 logic levels.
Clock Skew Details:
Source Clock Path EXTOSC to ISP/SLICE_126:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 3.680 LPLL.CLKOS2 to R10C4A.CLK CLK180_OUT
--------
-65.810 (112.6% logic, -12.6% route), 3 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Destination Clock Path EXTOSC to RTAVR/GPR/gpr_hi2/SLICE_98:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.385 27.PAD to 27.PADDI EXTOSC
ROUTE 2 2.090 27.PADDI to DCM6.CLK1 EXTOSC_c
MUX_DEL --- 0.000 DCM6.CLK1 to DCM6.DCMOUT clk_selector
ROUTE 1 2.497 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 3.680 LPLL.CLKOS3 to R10C11B.WCK CLK270_OUT
--------
-64.422 (112.8% logic, -12.8% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 3.954 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-74.055 (105.3% logic, -5.3% route), 1 logic levels.
Report: 14.187MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "EXTOSC" 24.000000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 35.006ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD EXTOSC
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
Preference: PERIOD PORT "TOP_TCK" 0.100000 nS ;
0 items scored, 1 timing error detected.
Note: Component internal maximum frequency has been exceeded.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 13.176ns
The internal maximum frequency of the following component is 75.324 MHz
Logical Details: Cell type Pin name Component name
Destination: SP8KC CLKA RTAVR/ROM/rom0
Delay: 13.276ns -- based on Minimum Pulse Width
Warning: 13.276ns is the minimum period for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "CLK180_OUT" 12.000000 | | |
MHz ; | 12.000 MHz| 14.127 MHz| 11
| | |
FREQUENCY NET "CLK_INT" 2.080000 MHz ; | -| -| 0
| | |
FREQUENCY NET "CLK_IN0" 12.000000 MHz ; | -| -| 0
| | |
FREQUENCY NET "CLK0_OUT" 12.000000 MHz | | |
; | 12.000 MHz| 15.267 MHz| 21
| | |
FREQUENCY NET "CLK90_OUT" 12.000000 MHz | | |
; | 12.000 MHz| 14.504 MHz| 11
| | |
FREQUENCY NET "CLK270_OUT" 12.000000 | | |
MHz ; | 12.000 MHz| 14.187 MHz| 13
| | |
FREQUENCY PORT "EXTOSC" 24.000000 MHz ; | 24.000 MHz| 150.150 MHz| 0
| | |
PERIOD PORT "TOP_TCK" 0.100000 nS ; | 0.100 ns| 13.276 ns| 0 *
| | |
----------------------------------------------------------------------------
1 preference(marked by "*" above) not met.
No net is responsible for more than 10% of the timing errors.
Clock Domains Analysis
------------------------
Found 9 clocks:
Clock Domain: CLK180_OUT Source: pll.CLKOS2 Loads: 149
Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ;
Data transfers from:
Clock Domain: CLK0_OUT Source: pll.CLKOP
Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; Transfers: 50
Clock Domain: CLK90_OUT Source: pll.CLKOS
Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; Transfers: 14
Clock Domain: CLK270_OUT Source: pll.CLKOS3
Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; Transfers: 16
Clock Domain: RTAVR/CLK_B Source: RTAVR/SLICE_570.F0
Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; Transfers: 17
Clock Domain: RTAVR/RAM/CLK_90_270 Source: RTAVR/SLICE_408.F1
Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; Transfers: 8
Clock Domain: CLK_IN0 Source: clk_selector.DCMOUT Loads: 1
No transfer within this clock domain is found
Clock Domain: CLK0_OUT Source: pll.CLKOP Loads: 113
Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ;
Data transfers from:
Clock Domain: CLK180_OUT Source: pll.CLKOS2
Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; Transfers: 65
Clock Domain: CLK90_OUT Source: pll.CLKOS
Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; Transfers: 8
Clock Domain: CLK270_OUT Source: pll.CLKOS3
Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; Transfers: 70
Clock Domain: RTAVR/CLK_L Source: RTAVR/SLICE_644.F1
Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; Transfers: 16
Clock Domain: RTAVR/CLK_B Source: RTAVR/SLICE_570.F0
Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; Transfers: 17
Clock Domain: RTAVR/RAM/CLK_90_270 Source: RTAVR/SLICE_408.F1
Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; Transfers: 8
Clock Domain: CLK90_OUT Source: pll.CLKOS Loads: 16
No transfer within this clock domain is found
Data transfers from:
Clock Domain: CLK180_OUT Source: pll.CLKOS2
Covered under: FREQUENCY NET "CLK90_OUT" 12.000000 MHz ; Transfers: 83
Clock Domain: CLK0_OUT Source: pll.CLKOP
Covered under: FREQUENCY NET "CLK90_OUT" 12.000000 MHz ; Transfers: 36
Clock Domain: CLK270_OUT Source: pll.CLKOS3
Covered under: FREQUENCY NET "CLK90_OUT" 12.000000 MHz ; Transfers: 18
Clock Domain: RTAVR/CLK_L Source: RTAVR/SLICE_644.F1
Covered under: FREQUENCY NET "CLK90_OUT" 12.000000 MHz ; Transfers: 13
Clock Domain: CLK270_OUT Source: pll.CLKOS3 Loads: 46
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ;
Data transfers from:
Clock Domain: CLK180_OUT Source: pll.CLKOS2
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 37
Clock Domain: CLK0_OUT Source: pll.CLKOP
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 92
Clock Domain: CLK90_OUT Source: pll.CLKOS
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 15
Clock Domain: RTAVR/CLK_B Source: RTAVR/SLICE_570.F0
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 17
Clock Domain: RTAVR/RAM/CLK_90_270 Source: RTAVR/SLICE_408.F1
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 8
Clock Domain: TOP_TCK_c Source: TOP_TCK.PAD Loads: 1
No transfer within this clock domain is found
Data transfers from:
Clock Domain: CLK180_OUT Source: pll.CLKOS2
Not reported because source and destination domains are unrelated.
Clock Domain: RTAVR/CLK_L Source: RTAVR/SLICE_644.F1 Loads: 8
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RTAVR/CLK_B Source: RTAVR/SLICE_570.F0
Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; Transfers: 16
Clock Domain: RTAVR/CLK_B Source: RTAVR/SLICE_570.F0 Loads: 9
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ;
Data transfers from:
Clock Domain: CLK180_OUT Source: pll.CLKOS2
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 26
Clock Domain: CLK0_OUT Source: pll.CLKOP
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 50
Clock Domain: CLK90_OUT Source: pll.CLKOS
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 8
Clock Domain: RTAVR/RAM/CLK_90_270 Source: RTAVR/SLICE_408.F1 Loads: 2
No transfer within this clock domain is found
Data transfers from:
Clock Domain: CLK180_OUT Source: pll.CLKOS2
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 24
Clock Domain: CLK0_OUT Source: pll.CLKOP
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 39
Clock Domain: CLK90_OUT Source: pll.CLKOS
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 8
Timing summary (Setup):
---------------
Timing errors: 1 Score: 0
Cumulative negative slack: 13176
Note: Component internal maximum frequency has been exceeded.
Constraints cover 672627 paths, 27 nets, and 5032 connections (94.5% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond_1.4_Production (87)
Sat Feb 25 14:03:10 2012
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 1 -sphld m -o MachXO2_Breakout_rtavr_xo2.twr MachXO2_Breakout_rtavr_xo2.ncd MachXO2_Breakout_rtavr_xo2.prf
Design file: machxo2_breakout_rtavr_xo2.ncd
Preference file: machxo2_breakout_rtavr_xo2.prf
Device,speed: LCMXO2-1200ZE,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "CLK180_OUT" 12.000000 MHz (196 errors)
4096 items scored, 196 timing errors detected.
FREQUENCY NET "CLK_INT" 2.080000 MHz (0 errors) 0 items scored, 0 timing errors detected.
FREQUENCY NET "CLK_IN0" 12.000000 MHz (0 errors) 0 items scored, 0 timing errors detected.
FREQUENCY NET "CLK0_OUT" 12.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
FREQUENCY NET "CLK90_OUT" 12.000000 MHz (6 errors)
2103 items scored, 6 timing errors detected.
FREQUENCY NET "CLK270_OUT" 12.000000 MHz (1764 errors)
4096 items scored, 1764 timing errors detected.
FREQUENCY PORT "EXTOSC" 24.000000 MHz (0 errors) 0 items scored, 0 timing errors detected.
PERIOD PORT "TOP_TCK" 0.100000 nS (0 errors) 0 items scored, 0 timing errors detected.
WARNING - trce: Input and feedback clock frequencies do not match their divider settings for pll
WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz.
WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz.
WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz.
WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ;
4096 items scored, 196 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 1.374ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/s2_DOBL_i2 (from CLK0_OUT +)
Destination: FF Data in RTAVR/IOR/i_port_c/r_ddr__i3 (to CLK180_OUT +)
Delay: 1.141ns (49.8% logic, 50.2% route), 2 logic levels.
Constraint Details:
1.141ns physical path delay RTAVR/SLICE_103 to RTAVR/IOR/SLICE_224 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-2.547ns skew less
0.000ns feedback compensation requirement (totaling 2.515ns) by 1.374ns
Physical Path Details:
Data path RTAVR/SLICE_103 to RTAVR/IOR/SLICE_224:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R9C10B.CLK to R9C10B.Q0 RTAVR/SLICE_103 (from CLK0_OUT)
ROUTE 11 0.563 R9C10B.Q0 to R9C10C.A1 GPR_DOBL_2
CTOOFX_DEL --- 0.311 R9C10C.A1 to R9C10C.OFX0 RTAVR/IOR/SLICE_224
ROUTE 14 0.010 R9C10C.OFX0 to R9C10C.DI0 RTAVR/IOR_DIB_2 (to CLK180_OUT)
--------
1.141 (49.8% logic, 50.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_103:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R9C10B.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/IOR/SLICE_224:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 1.077 LPLL.CLKOS2 to R9C10C.CLK CLK180_OUT
--------
-71.152 (106.1% logic, -6.1% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 1.288ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/s2_DOBL_i3 (from CLK0_OUT +)
Destination: FF Data in RTAVR/IOR/i_port_c/r_ddr__i4 (to CLK180_OUT +)
Delay: 1.227ns (46.3% logic, 53.7% route), 2 logic levels.
Constraint Details:
1.227ns physical path delay RTAVR/SLICE_103 to RTAVR/IOR/SLICE_225 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-2.547ns skew less
0.000ns feedback compensation requirement (totaling 2.515ns) by 1.288ns
Physical Path Details:
Data path RTAVR/SLICE_103 to RTAVR/IOR/SLICE_225:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R9C10B.CLK to R9C10B.Q1 RTAVR/SLICE_103 (from CLK0_OUT)
ROUTE 13 0.649 R9C10B.Q1 to R7C10A.D1 GPR_DOBL_3
CTOOFX_DEL --- 0.311 R7C10A.D1 to R7C10A.OFX0 RTAVR/IOR/SLICE_225
ROUTE 12 0.010 R7C10A.OFX0 to R7C10A.DI0 RTAVR/IOR_DIB_3 (to CLK180_OUT)
--------
1.227 (46.3% logic, 53.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_103:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R9C10B.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/IOR/SLICE_225:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 1.077 LPLL.CLKOS2 to R7C10A.CLK CLK180_OUT
--------
-71.152 (106.1% logic, -6.1% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 1.246ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/s2_DOBL_i1 (from CLK0_OUT +)
Destination: FF Data in RTAVR/IOR/i_port_c/r_ddr__i2 (to CLK180_OUT +)
Delay: 1.269ns (44.8% logic, 55.2% route), 2 logic levels.
Constraint Details:
1.269ns physical path delay RTAVR/SLICE_102 to RTAVR/IOR/SLICE_223 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-2.547ns skew less
0.000ns feedback compensation requirement (totaling 2.515ns) by 1.246ns
Physical Path Details:
Data path RTAVR/SLICE_102 to RTAVR/IOR/SLICE_223:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R10C11D.CLK to R10C11D.Q1 RTAVR/SLICE_102 (from CLK0_OUT)
ROUTE 11 0.691 R10C11D.Q1 to R9C10D.D1 GPR_DOBL_1
CTOOFX_DEL --- 0.311 R9C10D.D1 to R9C10D.OFX0 RTAVR/IOR/SLICE_223
ROUTE 15 0.010 R9C10D.OFX0 to R9C10D.DI0 RTAVR/IOR_DIB_1 (to CLK180_OUT)
--------
1.269 (44.8% logic, 55.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_102:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R10C11D.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/IOR/SLICE_223:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 1.077 LPLL.CLKOS2 to R9C10D.CLK CLK180_OUT
--------
-71.152 (106.1% logic, -6.1% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 1.217ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/s2_DOBL_i7 (from CLK0_OUT +)
Destination: FF Data in RTAVR/IOR/i_spi/SPIE_132 (to CLK180_OUT +)
Delay: 1.298ns (43.8% logic, 56.2% route), 2 logic levels.
Constraint Details:
1.298ns physical path delay RTAVR/SLICE_105 to RTAVR/IOR/SLICE_160 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-2.547ns skew less
0.000ns feedback compensation requirement (totaling 2.515ns) by 1.217ns
Physical Path Details:
Data path RTAVR/SLICE_105 to RTAVR/IOR/SLICE_160:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R9C12A.CLK to R9C12A.Q1 RTAVR/SLICE_105 (from CLK0_OUT)
ROUTE 12 0.717 R9C12A.Q1 to R8C10C.C1 GPR_DOBL_7
CTOOFX_DEL --- 0.311 R8C10C.C1 to R8C10C.OFX0 RTAVR/IOR/SLICE_160
ROUTE 13 0.013 R8C10C.OFX0 to R8C10C.DI0 RTAVR/IOR_DIB_7 (to CLK180_OUT)
--------
1.298 (43.8% logic, 56.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_105:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R9C12A.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/IOR/SLICE_160:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 1.077 LPLL.CLKOS2 to R8C10C.CLK CLK180_OUT
--------
-71.152 (106.1% logic, -6.1% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 1.103ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s1_predec_107 (from CLK0_OUT +)
Destination: FF Data in RTAVR/GPR/r_doa2_i3 (to CLK180_OUT +)
Delay: 1.412ns (32.3% logic, 67.7% route), 2 logic levels.
Constraint Details:
1.412ns physical path delay RTAVR/SLICE_172 to RTAVR/GPR/SLICE_53 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-2.547ns skew less
0.000ns feedback compensation requirement (totaling 2.515ns) by 1.103ns
Physical Path Details:
Data path RTAVR/SLICE_172 to RTAVR/GPR/SLICE_53:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R5C18C.CLK to R5C18C.Q0 RTAVR/SLICE_172 (from CLK0_OUT)
ROUTE 58 0.956 R5C18C.Q0 to R10C18B.A1 RTAVR/GPR/GPR_PREDEC
CTOF_DEL --- 0.199 R10C18B.A1 to R10C18B.F1 RTAVR/GPR/SLICE_53
ROUTE 1 0.000 R10C18B.F1 to R10C18B.DI1 RTAVR/GPR/DOA2_3 (to CLK180_OUT)
--------
1.412 (32.3% logic, 67.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_172:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R5C18C.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/GPR/SLICE_53:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 1.077 LPLL.CLKOS2 to R10C18B.CLK CLK180_OUT
--------
-71.152 (106.1% logic, -6.1% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 1.103ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s1_predec_107 (from CLK0_OUT +)
Destination: FF Data in RTAVR/GPR/r_doa2_i2 (to CLK180_OUT +)
Delay: 1.412ns (32.3% logic, 67.7% route), 2 logic levels.
Constraint Details:
1.412ns physical path delay RTAVR/SLICE_172 to RTAVR/GPR/SLICE_53 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-2.547ns skew less
0.000ns feedback compensation requirement (totaling 2.515ns) by 1.103ns
Physical Path Details:
Data path RTAVR/SLICE_172 to RTAVR/GPR/SLICE_53:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R5C18C.CLK to R5C18C.Q0 RTAVR/SLICE_172 (from CLK0_OUT)
ROUTE 58 0.956 R5C18C.Q0 to R10C18B.A0 RTAVR/GPR/GPR_PREDEC
CTOF_DEL --- 0.199 R10C18B.A0 to R10C18B.F0 RTAVR/GPR/SLICE_53
ROUTE 1 0.000 R10C18B.F0 to R10C18B.DI0 RTAVR/GPR/DOA2_2 (to CLK180_OUT)
--------
1.412 (32.3% logic, 67.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_172:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R5C18C.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/GPR/SLICE_53:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 1.077 LPLL.CLKOS2 to R10C18B.CLK CLK180_OUT
--------
-71.152 (106.1% logic, -6.1% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 1.082ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s1_predec_107 (from CLK0_OUT +)
Destination: FF Data in RTAVR/GPR/r_doa2_i6 (to CLK180_OUT +)
Delay: 1.433ns (31.8% logic, 68.2% route), 2 logic levels.
Constraint Details:
1.433ns physical path delay RTAVR/SLICE_172 to RTAVR/GPR/SLICE_47 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-2.547ns skew less
0.000ns feedback compensation requirement (totaling 2.515ns) by 1.082ns
Physical Path Details:
Data path RTAVR/SLICE_172 to RTAVR/GPR/SLICE_47:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R5C18C.CLK to R5C18C.Q0 RTAVR/SLICE_172 (from CLK0_OUT)
ROUTE 58 0.977 R5C18C.Q0 to R10C18D.B0 RTAVR/GPR/GPR_PREDEC
CTOF_DEL --- 0.199 R10C18D.B0 to R10C18D.F0 RTAVR/GPR/SLICE_47
ROUTE 1 0.000 R10C18D.F0 to R10C18D.DI0 RTAVR/GPR/DOA2_6 (to CLK180_OUT)
--------
1.433 (31.8% logic, 68.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_172:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R5C18C.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/GPR/SLICE_47:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 1.077 LPLL.CLKOS2 to R10C18D.CLK CLK180_OUT
--------
-71.152 (106.1% logic, -6.1% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 1.082ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s1_predec_107 (from CLK0_OUT +)
Destination: FF Data in RTAVR/GPR/r_doa2_i7 (to CLK180_OUT +)
Delay: 1.433ns (31.8% logic, 68.2% route), 2 logic levels.
Constraint Details:
1.433ns physical path delay RTAVR/SLICE_172 to RTAVR/GPR/SLICE_47 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-2.547ns skew less
0.000ns feedback compensation requirement (totaling 2.515ns) by 1.082ns
Physical Path Details:
Data path RTAVR/SLICE_172 to RTAVR/GPR/SLICE_47:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R5C18C.CLK to R5C18C.Q0 RTAVR/SLICE_172 (from CLK0_OUT)
ROUTE 58 0.977 R5C18C.Q0 to R10C18D.B1 RTAVR/GPR/GPR_PREDEC
CTOF_DEL --- 0.199 R10C18D.B1 to R10C18D.F1 RTAVR/GPR/SLICE_47
ROUTE 1 0.000 R10C18D.F1 to R10C18D.DI1 RTAVR/GPR/DOA2_7 (to CLK180_OUT)
--------
1.433 (31.8% logic, 68.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_172:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R5C18C.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/GPR/SLICE_47:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 1.077 LPLL.CLKOS2 to R10C18D.CLK CLK180_OUT
--------
-71.152 (106.1% logic, -6.1% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 1.078ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s1_predec_107 (from CLK0_OUT +)
Destination: FF Data in RTAVR/GPR/r_doa2_i1 (to CLK180_OUT +)
Delay: 1.437ns (31.7% logic, 68.3% route), 2 logic levels.
Constraint Details:
1.437ns physical path delay RTAVR/SLICE_172 to RTAVR/GPR/SLICE_54 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-2.547ns skew less
0.000ns feedback compensation requirement (totaling 2.515ns) by 1.078ns
Physical Path Details:
Data path RTAVR/SLICE_172 to RTAVR/GPR/SLICE_54:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R5C18C.CLK to R5C18C.Q0 RTAVR/SLICE_172 (from CLK0_OUT)
ROUTE 58 0.981 R5C18C.Q0 to R10C18A.B1 RTAVR/GPR/GPR_PREDEC
CTOF_DEL --- 0.199 R10C18A.B1 to R10C18A.F1 RTAVR/GPR/SLICE_54
ROUTE 1 0.000 R10C18A.F1 to R10C18A.DI1 RTAVR/GPR/DOA2_1 (to CLK180_OUT)
--------
1.437 (31.7% logic, 68.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_172:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R5C18C.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/GPR/SLICE_54:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 1.077 LPLL.CLKOS2 to R10C18A.CLK CLK180_OUT
--------
-71.152 (106.1% logic, -6.1% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 1.030ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/s2_DOBL_i4 (from CLK0_OUT +)
Destination: FF Data in RTAVR/IOR/i_port_c/r_ddr__i5 (to CLK180_OUT +)
Delay: 1.485ns (38.2% logic, 61.8% route), 2 logic levels.
Constraint Details:
1.485ns physical path delay RTAVR/SLICE_104 to RTAVR/IOR/SLICE_226 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-2.547ns skew less
0.000ns feedback compensation requirement (totaling 2.515ns) by 1.030ns
Physical Path Details:
Data path RTAVR/SLICE_104 to RTAVR/IOR/SLICE_226:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R10C12D.CLK to R10C12D.Q0 RTAVR/SLICE_104 (from CLK0_OUT)
ROUTE 11 0.904 R10C12D.Q0 to R7C10D.C1 GPR_DOBL_4
CTOOFX_DEL --- 0.311 R7C10D.C1 to R7C10D.OFX0 RTAVR/IOR/SLICE_226
ROUTE 14 0.013 R7C10D.OFX0 to R7C10D.DI0 RTAVR/IOR_DIB_4 (to CLK180_OUT)
--------
1.485 (38.2% logic, 61.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_104:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R10C12D.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/IOR/SLICE_226:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS2_D --- -75.462 LPLL.CLKI to LPLL.CLKOS2 pll
ROUTE 149 1.077 LPLL.CLKOS2 to R7C10D.CLK CLK180_OUT
--------
-71.152 (106.1% logic, -6.1% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
================================================================================
Preference: FREQUENCY NET "CLK_INT" 2.080000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "CLK_IN0" 12.000000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.854ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_670__i1 (from CLK0_OUT +)
Destination: FF Data in RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_670__i1 (to CLK0_OUT +)
Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels.
Constraint Details:
0.822ns physical path delay RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 0.854ns
Physical Path Details:
Data path RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R3C2B.CLK to R3C2B.Q0 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30 (from CLK0_OUT)
ROUTE 1 0.366 R3C2B.Q0 to R3C2B.A0 RTAVR/IOR/IOR_PS0/i_timer0/n9
CTOF_DEL --- 0.199 R3C2B.A0 to R3C2B.F0 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30
ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 RTAVR/IOR/IOR_PS0/i_timer0/n55 (to CLK0_OUT)
--------
0.822 (55.5% logic, 44.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C2B.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C2B.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.854ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_670__i3 (from CLK0_OUT +)
Destination: FF Data in RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_670__i3 (to CLK0_OUT +)
Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels.
Constraint Details:
0.822ns physical path delay RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 0.854ns
Physical Path Details:
Data path RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R3C2C.CLK to R3C2C.Q0 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29 (from CLK0_OUT)
ROUTE 1 0.366 R3C2C.Q0 to R3C2C.A0 RTAVR/IOR/IOR_PS0/i_timer0/n7
CTOF_DEL --- 0.199 R3C2C.A0 to R3C2C.F0 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29
ROUTE 1 0.000 R3C2C.F0 to R3C2C.DI0 RTAVR/IOR/IOR_PS0/i_timer0/n53 (to CLK0_OUT)
--------
0.822 (55.5% logic, 44.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C2C.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C2C.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.854ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_670__i2 (from CLK0_OUT +)
Destination: FF Data in RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_670__i2 (to CLK0_OUT +)
Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels.
Constraint Details:
0.822ns physical path delay RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 0.854ns
Physical Path Details:
Data path RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R3C2B.CLK to R3C2B.Q1 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30 (from CLK0_OUT)
ROUTE 1 0.366 R3C2B.Q1 to R3C2B.A1 RTAVR/IOR/IOR_PS0/i_timer0/n8
CTOF_DEL --- 0.199 R3C2B.A1 to R3C2B.F1 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30
ROUTE 1 0.000 R3C2B.F1 to R3C2B.DI1 RTAVR/IOR/IOR_PS0/i_timer0/n54 (to CLK0_OUT)
--------
0.822 (55.5% logic, 44.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C2B.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_30:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C2B.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.854ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_670__i6 (from CLK0_OUT +)
Destination: FF Data in RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_670__i6 (to CLK0_OUT +)
Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels.
Constraint Details:
0.822ns physical path delay RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 0.854ns
Physical Path Details:
Data path RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R3C2D.CLK to R3C2D.Q1 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32 (from CLK0_OUT)
ROUTE 1 0.366 R3C2D.Q1 to R3C2D.A1 RTAVR/IOR/IOR_PS0/i_timer0/n4
CTOF_DEL --- 0.199 R3C2D.A1 to R3C2D.F1 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32
ROUTE 1 0.000 R3C2D.F1 to R3C2D.DI1 RTAVR/IOR/IOR_PS0/i_timer0/n50 (to CLK0_OUT)
--------
0.822 (55.5% logic, 44.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C2D.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C2D.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.854ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_670__i0 (from CLK0_OUT +)
Destination: FF Data in RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_670__i0 (to CLK0_OUT +)
Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels.
Constraint Details:
0.822ns physical path delay RTAVR/IOR/IOR_PS0/i_timer0/SLICE_31 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_31 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 0.854ns
Physical Path Details:
Data path RTAVR/IOR/IOR_PS0/i_timer0/SLICE_31 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_31:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R3C2A.CLK to R3C2A.Q1 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_31 (from CLK0_OUT)
ROUTE 1 0.366 R3C2A.Q1 to R3C2A.A1 RTAVR/IOR/IOR_PS0/i_timer0/n10
CTOF_DEL --- 0.199 R3C2A.A1 to R3C2A.F1 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_31
ROUTE 1 0.000 R3C2A.F1 to R3C2A.DI1 RTAVR/IOR/IOR_PS0/i_timer0/n56 (to CLK0_OUT)
--------
0.822 (55.5% logic, 44.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_31:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C2A.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_31:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C2A.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.854ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_670__i4 (from CLK0_OUT +)
Destination: FF Data in RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_670__i4 (to CLK0_OUT +)
Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels.
Constraint Details:
0.822ns physical path delay RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 0.854ns
Physical Path Details:
Data path RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R3C2C.CLK to R3C2C.Q1 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29 (from CLK0_OUT)
ROUTE 1 0.366 R3C2C.Q1 to R3C2C.A1 RTAVR/IOR/IOR_PS0/i_timer0/n6
CTOF_DEL --- 0.199 R3C2C.A1 to R3C2C.F1 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29
ROUTE 1 0.000 R3C2C.F1 to R3C2C.DI1 RTAVR/IOR/IOR_PS0/i_timer0/n52 (to CLK0_OUT)
--------
0.822 (55.5% logic, 44.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C2C.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_29:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C2C.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.857ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_670__i5 (from CLK0_OUT +)
Destination: FF Data in RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_670__i5 (to CLK0_OUT +)
Delay: 0.825ns (55.3% logic, 44.7% route), 2 logic levels.
Constraint Details:
0.825ns physical path delay RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 0.857ns
Physical Path Details:
Data path RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32 to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R3C2D.CLK to R3C2D.Q0 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32 (from CLK0_OUT)
ROUTE 4 0.369 R3C2D.Q0 to R3C2D.A0 RTAVR/IOR/IOR_PS0/i_timer0/r_prescaler_5
CTOF_DEL --- 0.199 R3C2D.A0 to R3C2D.F0 RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32
ROUTE 1 0.000 R3C2D.F0 to R3C2D.DI0 RTAVR/IOR/IOR_PS0/i_timer0/n51 (to CLK0_OUT)
--------
0.825 (55.3% logic, 44.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C2D.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/IOR/IOR_PS0/i_timer0/SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C2D.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.904ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/S1/s1_inst_i9 (from CLK0_OUT +)
Destination: FF Data in RTAVR/S1/s2_ea_pop_445 (to CLK0_OUT +)
Delay: 0.872ns (52.3% logic, 47.7% route), 2 logic levels.
Constraint Details:
0.872ns physical path delay RTAVR/S1/SLICE_165 to RTAVR/S1/SLICE_363 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 0.904ns
Physical Path Details:
Data path RTAVR/S1/SLICE_165 to RTAVR/S1/SLICE_363:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R3C15D.CLK to R3C15D.Q1 RTAVR/S1/SLICE_165 (from CLK0_OUT)
ROUTE 12 0.413 R3C15D.Q1 to R3C15B.D0 RTAVR/S1/INST_9
CTOF_DEL --- 0.199 R3C15B.D0 to R3C15B.F0 RTAVR/S1/SLICE_363
ROUTE 3 0.003 R3C15B.F0 to R3C15B.DI0 RTAVR/S1/n235 (to CLK0_OUT)
--------
0.872 (52.3% logic, 47.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/S1/SLICE_165:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C15D.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/S1/SLICE_363:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R3C15B.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.905ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/S1/s1_inst_i2 (from CLK0_OUT +)
Destination: FF Data in RTAVR/S1/s2_cmd_op1_455 (to CLK0_OUT +)
Delay: 0.873ns (52.2% logic, 47.8% route), 2 logic levels.
Constraint Details:
0.873ns physical path delay RTAVR/S1/SLICE_153 to RTAVR/S1/SLICE_153 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 0.905ns
Physical Path Details:
Data path RTAVR/S1/SLICE_153 to RTAVR/S1/SLICE_153:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R5C19D.CLK to R5C19D.Q1 RTAVR/S1/SLICE_153 (from CLK0_OUT)
ROUTE 14 0.417 R5C19D.Q1 to R5C19D.D0 RTAVR/INST_2
CTOF_DEL --- 0.199 R5C19D.D0 to R5C19D.F0 RTAVR/S1/SLICE_153
ROUTE 1 0.000 R5C19D.F0 to R5C19D.DI0 RTAVR/S1/n10864 (to CLK0_OUT)
--------
0.873 (52.2% logic, 47.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/S1/SLICE_153:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R5C19D.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/S1/SLICE_153:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R5C19D.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.909ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/S1/s1_inst_i13 (from CLK0_OUT +)
Destination: FF Data in RTAVR/S1/s2_alu_imm_454 (to CLK0_OUT +)
Delay: 0.877ns (52.0% logic, 48.0% route), 2 logic levels.
Constraint Details:
0.877ns physical path delay RTAVR/S1/SLICE_149 to RTAVR/S1/SLICE_142 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.032ns) by 0.909ns
Physical Path Details:
Data path RTAVR/S1/SLICE_149 to RTAVR/S1/SLICE_142:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R4C18B.CLK to R4C18B.Q1 RTAVR/S1/SLICE_149 (from CLK0_OUT)
ROUTE 20 0.421 R4C18B.Q1 to R4C19B.D0 RTAVR/INST_13
CTOF_DEL --- 0.199 R4C19B.D0 to R4C19B.F0 RTAVR/S1/SLICE_142
ROUTE 1 0.000 R4C19B.F0 to R4C19B.DI0 RTAVR/S1/f_alu_imm (to CLK0_OUT)
--------
0.877 (52.0% logic, 48.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path pll to RTAVR/S1/SLICE_149:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R4C18B.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path pll to RTAVR/S1/SLICE_142:
Name Fanout Delay (ns) Site Resource
ROUTE 113 1.077 LPLL.CLKOP to R4C19B.CLK CLK0_OUT
--------
1.077 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: FREQUENCY NET "CLK90_OUT" 12.000000 MHz ;
2103 items scored, 6 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 0.491ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s1_addr_bh_i3 (from CLK0_OUT +)
Destination: FF Data in RTAVR/GPR/r_wb_addr_i2 (to CLK90_OUT +)
Delay: 0.866ns (52.7% logic, 47.3% route), 2 logic levels.
Constraint Details:
0.866ns physical path delay RTAVR/SLICE_171 to RTAVR/SLICE_196 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-1.389ns skew less
0.000ns feedback compensation requirement (totaling 1.357ns) by 0.491ns
Physical Path Details:
Data path RTAVR/SLICE_171 to RTAVR/SLICE_196:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R5C16D.CLK to R5C16D.Q1 RTAVR/SLICE_171 (from CLK0_OUT)
ROUTE 2 0.410 R5C16D.Q1 to R5C16C.D0 RTAVR/GPR/GPR_ADDRBH_3
CTOF_DEL --- 0.199 R5C16C.D0 to R5C16C.F0 RTAVR/SLICE_196
ROUTE 1 0.000 R5C16C.F0 to R5C16C.DI0 RTAVR/GPR/n351 (to CLK90_OUT)
--------
0.866 (52.7% logic, 47.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_171:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R5C16D.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/SLICE_196:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 1.077 LPLL.CLKOS to R5C16C.CLK CLK90_OUT
--------
-72.310 (106.0% logic, -6.0% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 0.473ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/S0/s1_addr_ah_i0 (from CLK0_OUT +)
Destination: FF Data in RTAVR/GPR/r_wb_addr_0_82 (to CLK90_OUT +)
Delay: 0.884ns (51.6% logic, 48.4% route), 2 logic levels.
Constraint Details:
0.884ns physical path delay RTAVR/S0/SLICE_206 to RTAVR/GPR/SLICE_195 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-1.389ns skew less
0.000ns feedback compensation requirement (totaling 1.357ns) by 0.473ns
Physical Path Details:
Data path RTAVR/S0/SLICE_206 to RTAVR/GPR/SLICE_195:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R5C18D.CLK to R5C18D.Q1 RTAVR/S0/SLICE_206 (from CLK0_OUT)
ROUTE 1 0.428 R5C18D.Q1 to R5C16B.D0 RTAVR/GPR_ADDRAH_0
CTOF_DEL --- 0.199 R5C16B.D0 to R5C16B.F0 RTAVR/GPR/SLICE_195
ROUTE 1 0.000 R5C16B.F0 to R5C16B.DI0 RTAVR/GPR/n349 (to CLK90_OUT)
--------
0.884 (51.6% logic, 48.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/S0/SLICE_206:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R5C18D.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/GPR/SLICE_195:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 1.077 LPLL.CLKOS to R5C16B.CLK CLK90_OUT
--------
-72.310 (106.0% logic, -6.0% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 0.461ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s1_addr_bh_i2 (from CLK0_OUT +)
Destination: FF Data in RTAVR/GPR/r_wb_addr_i1 (to CLK90_OUT +)
Delay: 0.896ns (50.9% logic, 49.1% route), 2 logic levels.
Constraint Details:
0.896ns physical path delay RTAVR/SLICE_171 to RTAVR/GPR/SLICE_195 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-1.389ns skew less
0.000ns feedback compensation requirement (totaling 1.357ns) by 0.461ns
Physical Path Details:
Data path RTAVR/SLICE_171 to RTAVR/GPR/SLICE_195:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R5C16D.CLK to R5C16D.Q0 RTAVR/SLICE_171 (from CLK0_OUT)
ROUTE 2 0.440 R5C16D.Q0 to R5C16B.C1 RTAVR/GPR/GPR_ADDRBH_2
CTOF_DEL --- 0.199 R5C16B.C1 to R5C16B.F1 RTAVR/GPR/SLICE_195
ROUTE 1 0.000 R5C16B.F1 to R5C16B.DI1 RTAVR/GPR/n352 (to CLK90_OUT)
--------
0.896 (50.9% logic, 49.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_171:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R5C16D.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/GPR/SLICE_195:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 1.077 LPLL.CLKOS to R5C16B.CLK CLK90_OUT
--------
-72.310 (106.0% logic, -6.0% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 0.336ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s1_addr_bh_i0 (from CLK0_OUT +)
Destination: FF Data in RTAVR/GPR/r_wb_addr_0_82 (to CLK90_OUT +)
Delay: 1.021ns (44.7% logic, 55.3% route), 2 logic levels.
Constraint Details:
1.021ns physical path delay RTAVR/SLICE_170 to RTAVR/GPR/SLICE_195 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-1.389ns skew less
0.000ns feedback compensation requirement (totaling 1.357ns) by 0.336ns
Physical Path Details:
Data path RTAVR/SLICE_170 to RTAVR/GPR/SLICE_195:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R5C15A.CLK to R5C15A.Q0 RTAVR/SLICE_170 (from CLK0_OUT)
ROUTE 2 0.565 R5C15A.Q0 to R5C16B.A0 RTAVR/GPR/GPR_ADDRBH_0
CTOF_DEL --- 0.199 R5C16B.A0 to R5C16B.F0 RTAVR/GPR/SLICE_195
ROUTE 1 0.000 R5C16B.F0 to R5C16B.DI0 RTAVR/GPR/n349 (to CLK90_OUT)
--------
1.021 (44.7% logic, 55.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_170:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R5C15A.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/GPR/SLICE_195:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 1.077 LPLL.CLKOS to R5C16B.CLK CLK90_OUT
--------
-72.310 (106.0% logic, -6.0% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 0.222ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/GPR/s1_addr_bh_i1 (from CLK0_OUT +)
Destination: FF Data in RTAVR/GPR/r_wb_addr_i0 (to CLK90_OUT +)
Delay: 1.135ns (40.2% logic, 59.8% route), 2 logic levels.
Constraint Details:
1.135ns physical path delay RTAVR/SLICE_170 to RTAVR/GPR/SLICE_173 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-1.389ns skew less
0.000ns feedback compensation requirement (totaling 1.357ns) by 0.222ns
Physical Path Details:
Data path RTAVR/SLICE_170 to RTAVR/GPR/SLICE_173:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R5C15A.CLK to R5C15A.Q1 RTAVR/SLICE_170 (from CLK0_OUT)
ROUTE 2 0.679 R5C15A.Q1 to R7C15A.C0 RTAVR/GPR/GPR_ADDRBH_1
CTOF_DEL --- 0.199 R7C15A.C0 to R7C15A.F0 RTAVR/GPR/SLICE_173
ROUTE 1 0.000 R7C15A.F0 to R7C15A.DI0 RTAVR/GPR/n353 (to CLK90_OUT)
--------
1.135 (40.2% logic, 59.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_170:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R5C15A.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/GPR/SLICE_173:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 1.077 LPLL.CLKOS to R7C15A.CLK CLK90_OUT
--------
-72.310 (106.0% logic, -6.0% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 0.150ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/S0/s1_addr_ah_i1 (from CLK0_OUT +)
Destination: FF Data in RTAVR/GPR/r_wb_addr_i0 (to CLK90_OUT +)
Delay: 1.207ns (37.8% logic, 62.2% route), 2 logic levels.
Constraint Details:
1.207ns physical path delay RTAVR/S0/SLICE_322 to RTAVR/GPR/SLICE_173 exceeds
-0.032ns DIN_HLD and
0.000ns delay constraint less
-1.389ns skew less
0.000ns feedback compensation requirement (totaling 1.357ns) by 0.150ns
Physical Path Details:
Data path RTAVR/S0/SLICE_322 to RTAVR/GPR/SLICE_173:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R4C15B.CLK to R4C15B.Q1 RTAVR/S0/SLICE_322 (from CLK0_OUT)
ROUTE 1 0.751 R4C15B.Q1 to R7C15A.D0 RTAVR/GPR_ADDRAH_1
CTOF_DEL --- 0.199 R7C15A.D0 to R7C15A.F0 RTAVR/GPR/SLICE_173
ROUTE 1 0.000 R7C15A.F0 to R7C15A.DI0 RTAVR/GPR/n353 (to CLK90_OUT)
--------
1.207 (37.8% logic, 62.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/S0/SLICE_322:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R4C15B.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/GPR/SLICE_173:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 1.077 LPLL.CLKOS to R7C15A.CLK CLK90_OUT
--------
-72.310 (106.0% logic, -6.0% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Passed: The following path meets requirements by 0.132ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/S1/s2_cmd_bld_466 (from CLK0_OUT +)
Destination: FF Data in RTAVR/GPR/r_wb_addr_i1 (to CLK90_OUT +)
Delay: 1.489ns (44.0% logic, 56.0% route), 3 logic levels.
Constraint Details:
1.489ns physical path delay RTAVR/S1/SLICE_148 to RTAVR/GPR/SLICE_195 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
-1.389ns skew less
0.000ns feedback compensation requirement (totaling 1.357ns) by 0.132ns
Physical Path Details:
Data path RTAVR/S1/SLICE_148 to RTAVR/GPR/SLICE_195:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R5C18A.CLK to R5C18A.Q0 RTAVR/S1/SLICE_148 (from CLK0_OUT)
ROUTE 9 0.615 R5C18A.Q0 to R5C16C.D1 RTAVR/CMD_BLD
CTOF_DEL --- 0.199 R5C16C.D1 to R5C16C.F1 RTAVR/SLICE_196
ROUTE 6 0.219 R5C16C.F1 to R5C16B.D1 RTAVR/GPR_WE
CTOF_DEL --- 0.199 R5C16B.D1 to R5C16B.F1 RTAVR/GPR/SLICE_195
ROUTE 1 0.000 R5C16B.F1 to R5C16B.DI1 RTAVR/GPR/n352 (to CLK90_OUT)
--------
1.489 (44.0% logic, 56.0% route), 3 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/S1/SLICE_148:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R5C18A.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/GPR/SLICE_195:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 1.077 LPLL.CLKOS to R5C16B.CLK CLK90_OUT
--------
-72.310 (106.0% logic, -6.0% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Passed: The following path meets requirements by 0.162ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/S1/s2_cmd_bld_466 (from CLK0_OUT +)
Destination: FF Data in RTAVR/GPR/r_wb_addr_i2 (to CLK90_OUT +)
Delay: 1.519ns (43.1% logic, 56.9% route), 3 logic levels.
Constraint Details:
1.519ns physical path delay RTAVR/S1/SLICE_148 to RTAVR/SLICE_196 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
-1.389ns skew less
0.000ns feedback compensation requirement (totaling 1.357ns) by 0.162ns
Physical Path Details:
Data path RTAVR/S1/SLICE_148 to RTAVR/SLICE_196:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R5C18A.CLK to R5C18A.Q0 RTAVR/S1/SLICE_148 (from CLK0_OUT)
ROUTE 9 0.615 R5C18A.Q0 to R5C16C.D1 RTAVR/CMD_BLD
CTOF_DEL --- 0.199 R5C16C.D1 to R5C16C.F1 RTAVR/SLICE_196
ROUTE 6 0.249 R5C16C.F1 to R5C16C.C0 RTAVR/GPR_WE
CTOF_DEL --- 0.199 R5C16C.C0 to R5C16C.F0 RTAVR/SLICE_196
ROUTE 1 0.000 R5C16C.F0 to R5C16C.DI0 RTAVR/GPR/n351 (to CLK90_OUT)
--------
1.519 (43.1% logic, 56.9% route), 3 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/S1/SLICE_148:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R5C18A.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/SLICE_196:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 1.077 LPLL.CLKOS to R5C16C.CLK CLK90_OUT
--------
-72.310 (106.0% logic, -6.0% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Passed: The following path meets requirements by 0.186ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/S0/s1_addr_ah_i2 (from CLK0_OUT +)
Destination: FF Data in RTAVR/GPR/r_wb_addr_i1 (to CLK90_OUT +)
Delay: 1.543ns (29.6% logic, 70.4% route), 2 logic levels.
Constraint Details:
1.543ns physical path delay RTAVR/SLICE_9 to RTAVR/GPR/SLICE_195 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
-1.389ns skew less
0.000ns feedback compensation requirement (totaling 1.357ns) by 0.186ns
Physical Path Details:
Data path RTAVR/SLICE_9 to RTAVR/GPR/SLICE_195:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R3C12B.CLK to R3C12B.Q0 RTAVR/SLICE_9 (from CLK0_OUT)
ROUTE 1 1.087 R3C12B.Q0 to R5C16B.A1 RTAVR/GPR_ADDRAH_2
CTOF_DEL --- 0.199 R5C16B.A1 to R5C16B.F1 RTAVR/GPR/SLICE_195
ROUTE 1 0.000 R5C16B.F1 to R5C16B.DI1 RTAVR/GPR/n352 (to CLK90_OUT)
--------
1.543 (29.6% logic, 70.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R3C12B.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/GPR/SLICE_195:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 1.077 LPLL.CLKOS to R5C16B.CLK CLK90_OUT
--------
-72.310 (106.0% logic, -6.0% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Passed: The following path meets requirements by 0.217ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/S0/s1_addr_ah_i3 (from CLK0_OUT +)
Destination: FF Data in RTAVR/GPR/r_wb_addr_i2 (to CLK90_OUT +)
Delay: 1.574ns (29.0% logic, 71.0% route), 2 logic levels.
Constraint Details:
1.574ns physical path delay RTAVR/SLICE_9 to RTAVR/SLICE_196 meets
-0.032ns DIN_HLD and
0.000ns delay constraint less
-1.389ns skew less
0.000ns feedback compensation requirement (totaling 1.357ns) by 0.217ns
Physical Path Details:
Data path RTAVR/SLICE_9 to RTAVR/SLICE_196:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R3C12B.CLK to R3C12B.Q1 RTAVR/SLICE_9 (from CLK0_OUT)
ROUTE 1 1.118 R3C12B.Q1 to R5C16C.B0 RTAVR/GPR_ADDRAH_3
CTOF_DEL --- 0.199 R5C16C.B0 to R5C16C.F0 RTAVR/SLICE_196
ROUTE 1 0.000 R5C16C.F0 to R5C16C.DI0 RTAVR/GPR/n351 (to CLK90_OUT)
--------
1.574 (29.0% logic, 71.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R3C12B.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/SLICE_196:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 1.077 LPLL.CLKOS to R5C16C.CLK CLK90_OUT
--------
-72.310 (106.0% logic, -6.0% route), 2 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
================================================================================
Preference: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ;
4096 items scored, 1764 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 4.700ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/s2_DOBL_i7 (from CLK0_OUT +)
Destination: SP8KC Port RTAVR/RAM/mem0(ASIC) (to RTAVR/RAM/CLK_90_270 +)
Delay: 2.469ns (23.0% logic, 77.0% route), 2 logic levels.
Constraint Details:
2.469ns physical path delay RTAVR/SLICE_105 to RTAVR/RAM/mem0 exceeds
0.070ns DATA_HLD and
0.000ns delay constraint less
-7.099ns skew less
0.000ns feedback compensation requirement (totaling 7.169ns) by 4.700ns
Physical Path Details:
Data path RTAVR/SLICE_105 to RTAVR/RAM/mem0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R9C12A.CLK to R9C12A.Q1 RTAVR/SLICE_105 (from CLK0_OUT)
ROUTE 12 0.717 R9C12A.Q1 to R8C10C.C1 GPR_DOBL_7
CTOOFX_DEL --- 0.311 R8C10C.C1 to R8C10C.OFX0 RTAVR/IOR/SLICE_160
ROUTE 13 1.184 R8C10C.OFX0 to EBR_R6C4.DI3 RTAVR/IOR_DIB_7 (to RTAVR/RAM/CLK_90_270)
--------
2.469 (23.0% logic, 77.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_105:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R9C12A.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/RAM/mem0:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 1.622 LPLL.CLKOS3 to R9C11D.C1 CLK270_OUT
CTOF_DEL --- 0.292 R9C11D.C1 to R9C11D.F1 RTAVR/SLICE_408
ROUTE 2 2.327 R9C11D.F1 to EBR_R6C4.CLK RTAVR/RAM/CLK_90_270
--------
-66.600 (110.8% logic, -10.8% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 4.644ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/s2_DOBL_i2 (from CLK0_OUT +)
Destination: SP8KC Port RTAVR/ROM/rom1(ASIC) (to RTAVR/CLK_B +)
Delay: 2.018ns (28.1% logic, 71.9% route), 2 logic levels.
Constraint Details:
2.018ns physical path delay RTAVR/SLICE_103 to RTAVR/ROM/rom1 exceeds
0.070ns DATA_HLD and
0.000ns delay constraint less
-6.592ns skew less
0.000ns feedback compensation requirement (totaling 6.662ns) by 4.644ns
Physical Path Details:
Data path RTAVR/SLICE_103 to RTAVR/ROM/rom1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R9C10B.CLK to R9C10B.Q0 RTAVR/SLICE_103 (from CLK0_OUT)
ROUTE 11 0.563 R9C10B.Q0 to R9C10C.A1 GPR_DOBL_2
CTOOFX_DEL --- 0.311 R9C10C.A1 to R9C10C.OFX0 RTAVR/IOR/SLICE_224
ROUTE 14 0.887 R9C10C.OFX0 to EBR_R6C7.DI2 RTAVR/IOR_DIB_2 (to RTAVR/CLK_B)
--------
2.018 (28.1% logic, 71.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_103:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R9C10B.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/ROM/rom1:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 1.655 LPLL.CLKOS to R7C12D.C1 CLK90_OUT
CTOF_DEL --- 0.292 R7C12D.C1 to R7C12D.F1 RTAVR/SLICE_570
ROUTE 1 2.305 R7C12D.F1 to R7C12D.D0 RTAVR/RAM/n4
CTOF_DEL --- 0.292 R7C12D.D0 to R7C12D.F0 RTAVR/SLICE_570
ROUTE 9 1.736 R7C12D.F0 to EBR_R6C7.CLK RTAVR/CLK_B
--------
-67.107 (113.3% logic, -13.3% route), 4 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 4.641ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/S1/s2_ea_i10 (from CLK0_OUT +)
Destination: SP8KC Port RTAVR/RAM/mem0(ASIC) (to RTAVR/RAM/CLK_90_270 +)
Delay: 2.518ns (18.1% logic, 81.9% route), 2 logic levels.
Constraint Details:
2.518ns physical path delay RTAVR/S1/SLICE_376 to RTAVR/RAM/mem0 exceeds
0.060ns ADDR_HLD and
0.000ns delay constraint less
-7.099ns skew less
0.000ns feedback compensation requirement (totaling 7.159ns) by 4.641ns
Physical Path Details:
Data path RTAVR/S1/SLICE_376 to RTAVR/RAM/mem0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R5C10D.CLK to R5C10D.Q0 RTAVR/S1/SLICE_376 (from CLK0_OUT)
ROUTE 1 1.076 R5C10D.Q0 to R7C7C.B1 RTAVR/S1_EA_10
CTOF_DEL --- 0.199 R7C7C.B1 to R7C7C.F1 RTAVR/SLICE_565
ROUTE 4 0.986 R7C7C.F1 to EBR_R6C4.AD12 RTAVR/RAM_ADDRB_10 (to RTAVR/RAM/CLK_90_270)
--------
2.518 (18.1% logic, 81.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/S1/SLICE_376:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R5C10D.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/RAM/mem0:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 1.622 LPLL.CLKOS3 to R9C11D.C1 CLK270_OUT
CTOF_DEL --- 0.292 R9C11D.C1 to R9C11D.F1 RTAVR/SLICE_408
ROUTE 2 2.327 R9C11D.F1 to EBR_R6C4.CLK RTAVR/RAM/CLK_90_270
--------
-66.600 (110.8% logic, -10.8% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 4.590ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/S1/s2_ea_i2 (from CLK0_OUT +)
Destination: SP8KC Port RTAVR/RAM/mem0(ASIC) (to RTAVR/RAM/CLK_90_270 +)
Delay: 2.569ns (17.8% logic, 82.2% route), 2 logic levels.
Constraint Details:
2.569ns physical path delay RTAVR/S1/SLICE_368 to RTAVR/RAM/mem0 exceeds
0.060ns ADDR_HLD and
0.000ns delay constraint less
-7.099ns skew less
0.000ns feedback compensation requirement (totaling 7.159ns) by 4.590ns
Physical Path Details:
Data path RTAVR/S1/SLICE_368 to RTAVR/RAM/mem0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R4C11C.CLK to R4C11C.Q1 RTAVR/S1/SLICE_368 (from CLK0_OUT)
ROUTE 9 1.373 R4C11C.Q1 to R4C6C.A1 RTAVR/S1_EA_2
CTOF_DEL --- 0.199 R4C6C.A1 to R4C6C.F1 RTAVR/SLICE_569
ROUTE 41 0.740 R4C6C.F1 to EBR_R6C4.AD4 RTAVR/IOR_ADDRB_2 (to RTAVR/RAM/CLK_90_270)
--------
2.569 (17.8% logic, 82.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/S1/SLICE_368:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R4C11C.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/RAM/mem0:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 1.622 LPLL.CLKOS3 to R9C11D.C1 CLK270_OUT
CTOF_DEL --- 0.292 R9C11D.C1 to R9C11D.F1 RTAVR/SLICE_408
ROUTE 2 2.327 R9C11D.F1 to EBR_R6C4.CLK RTAVR/RAM/CLK_90_270
--------
-66.600 (110.8% logic, -10.8% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 4.581ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/S1/s2_ea_i3 (from CLK0_OUT +)
Destination: SP8KC Port RTAVR/RAM/mem0(ASIC) (to RTAVR/RAM/CLK_90_270 +)
Delay: 2.578ns (17.7% logic, 82.3% route), 2 logic levels.
Constraint Details:
2.578ns physical path delay RTAVR/S1/SLICE_369 to RTAVR/RAM/mem0 exceeds
0.060ns ADDR_HLD and
0.000ns delay constraint less
-7.099ns skew less
0.000ns feedback compensation requirement (totaling 7.159ns) by 4.581ns
Physical Path Details:
Data path RTAVR/S1/SLICE_369 to RTAVR/RAM/mem0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R5C13A.CLK to R5C13A.Q1 RTAVR/S1/SLICE_369 (from CLK0_OUT)
ROUTE 2 1.121 R5C13A.Q1 to R5C7B.B0 RTAVR/S1_EA_3
CTOF_DEL --- 0.199 R5C7B.B0 to R5C7B.F0 RTAVR/IOR/IOR_PS0/SLICE_499
ROUTE 36 1.001 R5C7B.F0 to EBR_R6C4.AD5 RTAVR/IOR_ADDRB_3 (to RTAVR/RAM/CLK_90_270)
--------
2.578 (17.7% logic, 82.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/S1/SLICE_369:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R5C13A.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/RAM/mem0:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 1.622 LPLL.CLKOS3 to R9C11D.C1 CLK270_OUT
CTOF_DEL --- 0.292 R9C11D.C1 to R9C11D.F1 RTAVR/SLICE_408
ROUTE 2 2.327 R9C11D.F1 to EBR_R6C4.CLK RTAVR/RAM/CLK_90_270
--------
-66.600 (110.8% logic, -10.8% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 4.567ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/S1/r_pc_i0_i3 (from CLK0_OUT +)
Destination: SP8KC Port RTAVR/ROM/rom3(ASIC) (to RTAVR/CLK_B +)
Delay: 2.085ns (21.9% logic, 78.1% route), 2 logic levels.
Constraint Details:
2.085ns physical path delay RTAVR/S1/SLICE_331 to RTAVR/ROM/rom3 exceeds
0.060ns ADDR_HLD and
0.000ns delay constraint less
-6.592ns skew less
0.000ns feedback compensation requirement (totaling 6.652ns) by 4.567ns
Physical Path Details:
Data path RTAVR/S1/SLICE_331 to RTAVR/ROM/rom3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R2C12B.CLK to R2C12B.Q0 RTAVR/S1/SLICE_331 (from CLK0_OUT)
ROUTE 3 0.788 R2C12B.Q0 to R4C6A.C0 RTAVR/ROM_ADDRA_3
CTOF_DEL --- 0.199 R4C6A.C0 to R4C6A.F0 RTAVR/SLICE_670
ROUTE 4 0.841 R4C6A.F0 to EBR_R6C10.AD5 RTAVR/ROM/ADDR_AB_3 (to RTAVR/CLK_B)
--------
2.085 (21.9% logic, 78.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/S1/SLICE_331:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R2C12B.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/ROM/rom3:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 1.655 LPLL.CLKOS to R7C12D.C1 CLK90_OUT
CTOF_DEL --- 0.292 R7C12D.C1 to R7C12D.F1 RTAVR/SLICE_570
ROUTE 1 2.305 R7C12D.F1 to R7C12D.D0 RTAVR/RAM/n4
CTOF_DEL --- 0.292 R7C12D.D0 to R7C12D.F0 RTAVR/SLICE_570
ROUTE 9 1.736 R7C12D.F0 to EBR_R6C10.CLK RTAVR/CLK_B
--------
-67.107 (113.3% logic, -13.3% route), 4 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 4.552ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/s2_DOBL_i4 (from CLK0_OUT +)
Destination: SP8KC Port RTAVR/RAM/mem0(ASIC) (to RTAVR/RAM/CLK_90_270 +)
Delay: 2.617ns (21.7% logic, 78.3% route), 2 logic levels.
Constraint Details:
2.617ns physical path delay RTAVR/SLICE_104 to RTAVR/RAM/mem0 exceeds
0.070ns DATA_HLD and
0.000ns delay constraint less
-7.099ns skew less
0.000ns feedback compensation requirement (totaling 7.169ns) by 4.552ns
Physical Path Details:
Data path RTAVR/SLICE_104 to RTAVR/RAM/mem0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R10C12D.CLK to R10C12D.Q0 RTAVR/SLICE_104 (from CLK0_OUT)
ROUTE 11 0.904 R10C12D.Q0 to R7C10D.C1 GPR_DOBL_4
CTOOFX_DEL --- 0.311 R7C10D.C1 to R7C10D.OFX0 RTAVR/IOR/SLICE_226
ROUTE 14 1.145 R7C10D.OFX0 to EBR_R6C4.DI0 RTAVR/IOR_DIB_4 (to RTAVR/RAM/CLK_90_270)
--------
2.617 (21.7% logic, 78.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_104:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R10C12D.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/RAM/mem0:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 1.622 LPLL.CLKOS3 to R9C11D.C1 CLK270_OUT
CTOF_DEL --- 0.292 R9C11D.C1 to R9C11D.F1 RTAVR/SLICE_408
ROUTE 2 2.327 R9C11D.F1 to EBR_R6C4.CLK RTAVR/RAM/CLK_90_270
--------
-66.600 (110.8% logic, -10.8% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 4.443ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/s2_DOBL_i3 (from CLK0_OUT +)
Destination: SP8KC Port RTAVR/ROM/rom1(ASIC) (to RTAVR/CLK_B +)
Delay: 2.219ns (25.6% logic, 74.4% route), 2 logic levels.
Constraint Details:
2.219ns physical path delay RTAVR/SLICE_103 to RTAVR/ROM/rom1 exceeds
0.070ns DATA_HLD and
0.000ns delay constraint less
-6.592ns skew less
0.000ns feedback compensation requirement (totaling 6.662ns) by 4.443ns
Physical Path Details:
Data path RTAVR/SLICE_103 to RTAVR/ROM/rom1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R9C10B.CLK to R9C10B.Q1 RTAVR/SLICE_103 (from CLK0_OUT)
ROUTE 13 0.649 R9C10B.Q1 to R7C10A.D1 GPR_DOBL_3
CTOOFX_DEL --- 0.311 R7C10A.D1 to R7C10A.OFX0 RTAVR/IOR/SLICE_225
ROUTE 12 1.002 R7C10A.OFX0 to EBR_R6C7.DI3 RTAVR/IOR_DIB_3 (to RTAVR/CLK_B)
--------
2.219 (25.6% logic, 74.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/SLICE_103:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R9C10B.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/ROM/rom1:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS_DE --- -76.620 LPLL.CLKI to LPLL.CLKOS pll
ROUTE 16 1.655 LPLL.CLKOS to R7C12D.C1 CLK90_OUT
CTOF_DEL --- 0.292 R7C12D.C1 to R7C12D.F1 RTAVR/SLICE_570
ROUTE 1 2.305 R7C12D.F1 to R7C12D.D0 RTAVR/RAM/n4
CTOF_DEL --- 0.292 R7C12D.D0 to R7C12D.F0 RTAVR/SLICE_570
ROUTE 9 1.736 R7C12D.F0 to EBR_R6C7.CLK RTAVR/CLK_B
--------
-67.107 (113.3% logic, -13.3% route), 4 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 4.387ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/S1/s2_ea_i4 (from CLK0_OUT +)
Destination: SP8KC Port RTAVR/RAM/mem0(ASIC) (to RTAVR/RAM/CLK_90_270 +)
Delay: 2.772ns (16.5% logic, 83.5% route), 2 logic levels.
Constraint Details:
2.772ns physical path delay RTAVR/S1/SLICE_370 to RTAVR/RAM/mem0 exceeds
0.060ns ADDR_HLD and
0.000ns delay constraint less
-7.099ns skew less
0.000ns feedback compensation requirement (totaling 7.159ns) by 4.387ns
Physical Path Details:
Data path RTAVR/S1/SLICE_370 to RTAVR/RAM/mem0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R2C11C.CLK to R2C11C.Q1 RTAVR/S1/SLICE_370 (from CLK0_OUT)
ROUTE 1 1.093 R2C11C.Q1 to R3C7C.A0 RTAVR/S1_EA_4
CTOF_DEL --- 0.199 R3C7C.A0 to R3C7C.F0 RTAVR/IOR/IOR_PS0/SLICE_498
ROUTE 33 1.223 R3C7C.F0 to EBR_R6C4.AD6 RTAVR/IOR_ADDRB_4 (to RTAVR/RAM/CLK_90_270)
--------
2.772 (16.5% logic, 83.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/S1/SLICE_370:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R2C11C.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/RAM/mem0:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 1.622 LPLL.CLKOS3 to R9C11D.C1 CLK270_OUT
CTOF_DEL --- 0.292 R9C11D.C1 to R9C11D.F1 RTAVR/SLICE_408
ROUTE 2 2.327 R9C11D.F1 to EBR_R6C4.CLK RTAVR/RAM/CLK_90_270
--------
-66.600 (110.8% logic, -10.8% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Error: The following path exceeds requirements by 4.286ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RTAVR/S1/s2_ea_i5 (from CLK0_OUT +)
Destination: SP8KC Port RTAVR/RAM/mem0(ASIC) (to RTAVR/RAM/CLK_90_270 +)
Delay: 2.873ns (15.9% logic, 84.1% route), 2 logic levels.
Constraint Details:
2.873ns physical path delay RTAVR/S1/SLICE_371 to RTAVR/RAM/mem0 exceeds
0.060ns ADDR_HLD and
0.000ns delay constraint less
-7.099ns skew less
0.000ns feedback compensation requirement (totaling 7.159ns) by 4.286ns
Physical Path Details:
Data path RTAVR/S1/SLICE_371 to RTAVR/RAM/mem0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 R4C11A.CLK to R4C11A.Q1 RTAVR/S1/SLICE_371 (from CLK0_OUT)
ROUTE 1 1.414 R4C11A.Q1 to R5C4C.A0 RTAVR/S1_EA_5
CTOF_DEL --- 0.199 R5C4C.A0 to R5C4C.F0 RTAVR/IOR/IOR_PS0/SLICE_497
ROUTE 33 1.003 R5C4C.F0 to EBR_R6C4.AD7 RTAVR/IOR_ADDRB_5 (to RTAVR/RAM/CLK_90_270)
--------
2.873 (15.9% logic, 84.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path osc_internal to RTAVR/S1/SLICE_371:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OP_DE --- -78.009 LPLL.CLKI to LPLL.CLKOP pll
ROUTE 113 1.077 LPLL.CLKOP to R4C11A.CLK CLK0_OUT
--------
-73.699 (105.8% logic, -5.8% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
Destination Clock Path osc_internal to RTAVR/RAM/mem0:
Name Fanout Delay (ns) Site Resource
ROUTE 1 2.515 OSC.OSC to DCM6.CLK0 CLK_INT
MUX_DEL --- 0.000 DCM6.CLK0 to DCM6.DCMOUT clk_selector
ROUTE 1 0.718 DCM6.DCMOUT to LPLL.CLKI CLK_IN0
CLKI2OS3_D --- -74.074 LPLL.CLKI to LPLL.CLKOS3 pll
ROUTE 46 1.622 LPLL.CLKOS3 to R9C11D.C1 CLK270_OUT
CTOF_DEL --- 0.292 R9C11D.C1 to R9C11D.F1 RTAVR/SLICE_408
ROUTE 2 2.327 R9C11D.F1 to EBR_R6C4.CLK RTAVR/RAM/CLK_90_270
--------
-66.600 (110.8% logic, -10.8% route), 3 logic levels.
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- -78.009 LPLL.CLKFB to LPLL.CLKOP pll
ROUTE 113 1.172 LPLL.CLKOP to LPLL.CLKFB CLK0_OUT
--------
-76.837 (101.5% logic, -1.5% route), 1 logic levels.
================================================================================
Preference: FREQUENCY PORT "EXTOSC" 24.000000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: PERIOD PORT "TOP_TCK" 0.100000 nS ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "CLK180_OUT" 12.000000 | | |
MHz ; | -| -| 2 *
| | |
FREQUENCY NET "CLK_INT" 2.080000 MHz ; | -| -| 0
| | |
FREQUENCY NET "CLK_IN0" 12.000000 MHz ; | -| -| 0
| | |
FREQUENCY NET "CLK0_OUT" 12.000000 MHz | | |
; | -| -| 2
| | |
FREQUENCY NET "CLK90_OUT" 12.000000 MHz | | |
; | -| -| 2 *
| | |
FREQUENCY NET "CLK270_OUT" 12.000000 | | |
MHz ; | -| -| 2 *
| | |
FREQUENCY PORT "EXTOSC" 24.000000 MHz ; | -| -| 0
| | |
PERIOD PORT "TOP_TCK" 0.100000 nS ; | -| -| 0
| | |
----------------------------------------------------------------------------
3 preferences(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
RTAVR/GPR/GPR_PREDEC | 58| 321| 16.33%
| | |
RTAVR/IOR/IOR_PS0/i_timer0/n1990 | 16| 203| 10.33%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 9 clocks:
Clock Domain: CLK180_OUT Source: pll.CLKOS2 Loads: 149
Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ;
Data transfers from:
Clock Domain: CLK0_OUT Source: pll.CLKOP
Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; Transfers: 50
Clock Domain: CLK90_OUT Source: pll.CLKOS
Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; Transfers: 14
Clock Domain: CLK270_OUT Source: pll.CLKOS3
Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; Transfers: 16
Clock Domain: RTAVR/CLK_B Source: RTAVR/SLICE_570.F0
Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; Transfers: 17
Clock Domain: RTAVR/RAM/CLK_90_270 Source: RTAVR/SLICE_408.F1
Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; Transfers: 8
Clock Domain: CLK_IN0 Source: clk_selector.DCMOUT Loads: 1
No transfer within this clock domain is found
Clock Domain: CLK0_OUT Source: pll.CLKOP Loads: 113
Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ;
Data transfers from:
Clock Domain: CLK180_OUT Source: pll.CLKOS2
Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; Transfers: 65
Clock Domain: CLK90_OUT Source: pll.CLKOS
Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; Transfers: 8
Clock Domain: CLK270_OUT Source: pll.CLKOS3
Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; Transfers: 70
Clock Domain: RTAVR/CLK_L Source: RTAVR/SLICE_644.F1
Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; Transfers: 16
Clock Domain: RTAVR/CLK_B Source: RTAVR/SLICE_570.F0
Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; Transfers: 17
Clock Domain: RTAVR/RAM/CLK_90_270 Source: RTAVR/SLICE_408.F1
Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; Transfers: 8
Clock Domain: CLK90_OUT Source: pll.CLKOS Loads: 16
No transfer within this clock domain is found
Data transfers from:
Clock Domain: CLK180_OUT Source: pll.CLKOS2
Covered under: FREQUENCY NET "CLK90_OUT" 12.000000 MHz ; Transfers: 83
Clock Domain: CLK0_OUT Source: pll.CLKOP
Covered under: FREQUENCY NET "CLK90_OUT" 12.000000 MHz ; Transfers: 36
Clock Domain: CLK270_OUT Source: pll.CLKOS3
Covered under: FREQUENCY NET "CLK90_OUT" 12.000000 MHz ; Transfers: 18
Clock Domain: RTAVR/CLK_L Source: RTAVR/SLICE_644.F1
Covered under: FREQUENCY NET "CLK90_OUT" 12.000000 MHz ; Transfers: 13
Clock Domain: CLK270_OUT Source: pll.CLKOS3 Loads: 46
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ;
Data transfers from:
Clock Domain: CLK180_OUT Source: pll.CLKOS2
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 37
Clock Domain: CLK0_OUT Source: pll.CLKOP
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 92
Clock Domain: CLK90_OUT Source: pll.CLKOS
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 15
Clock Domain: RTAVR/CLK_B Source: RTAVR/SLICE_570.F0
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 17
Clock Domain: RTAVR/RAM/CLK_90_270 Source: RTAVR/SLICE_408.F1
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 8
Clock Domain: TOP_TCK_c Source: TOP_TCK.PAD Loads: 1
No transfer within this clock domain is found
Data transfers from:
Clock Domain: CLK180_OUT Source: pll.CLKOS2
Not reported because source and destination domains are unrelated.
Clock Domain: RTAVR/CLK_L Source: RTAVR/SLICE_644.F1 Loads: 8
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RTAVR/CLK_B Source: RTAVR/SLICE_570.F0
Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; Transfers: 16
Clock Domain: RTAVR/CLK_B Source: RTAVR/SLICE_570.F0 Loads: 9
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ;
Data transfers from:
Clock Domain: CLK180_OUT Source: pll.CLKOS2
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 26
Clock Domain: CLK0_OUT Source: pll.CLKOP
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 50
Clock Domain: CLK90_OUT Source: pll.CLKOS
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 8
Clock Domain: RTAVR/RAM/CLK_90_270 Source: RTAVR/SLICE_408.F1 Loads: 2
No transfer within this clock domain is found
Data transfers from:
Clock Domain: CLK180_OUT Source: pll.CLKOS2
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 24
Clock Domain: CLK0_OUT Source: pll.CLKOP
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 39
Clock Domain: CLK90_OUT Source: pll.CLKOS
Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Transfers: 8
Timing summary (Hold):
---------------
Timing errors: 1966 Score: 2313305
Cumulative negative slack: 2313305
Constraints cover 672627 paths, 27 nets, and 5032 connections (94.5% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 1 (setup), 1966 (hold)
Score: 0 (setup), 2313305 (hold)
Cumulative negative slack: 2326481 (13176+2313305)
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