PAR: Place And Route Diamond_1.4_Production (87). Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Thu Feb 23 17:39:39 2012 Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f MachXO_Breakout_rtavr_xo.p2t MachXO_Breakout_rtavr_xo_map.ncd MachXO_Breakout_rtavr_xo.dir MachXO_Breakout_rtavr_xo.prf Preference file: MachXO_Breakout_rtavr_xo.prf. Cost Table Summary Level/ Number Timing Run NCD Cost [ncd] Unrouted Score Time Status ---------- -------- -------- ----- ------------ 5_1 * 0 0 01:16 Complete * : Design saved. par done! Lattice Place and Route Report for Design "MachXO_Breakout_rtavr_xo_map.ncd" Thu Feb 23 17:39:39 2012 Best Par Run PAR: Place And Route Diamond_1.4_Production (87). Command Line: Y:/Program_Files/lscc/diamond/1.4/ispfpga\bin\nt\par -f MachXO_Breakout_rtavr_xo.p2t MachXO_Breakout_rtavr_xo_map.ncd MachXO_Breakout_rtavr_xo.dir MachXO_Breakout_rtavr_xo.prf Preference file: MachXO_Breakout_rtavr_xo.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file MachXO_Breakout_rtavr_xo_map.ncd. Design name: xo2_isp NCD version: 3.2 Vendor: LATTICE Device: LCMXO2280C Package: FTBGA256 Performance: 3 Loading device for application par from file 'mj5g21x17.nph' in environment Y:/Program_Files/lscc/diamond/1.4/ispfpga. Package Status: Final Version 1.26 Performance Hardware Data Status: Version 1.69 License checked out. Ignore Preference Error(s): True Device utilization summary: OSC 1/1 100% used PIO (prelim) 8/271 2% used 8/211 3% bonded JTAG 1/1 100% used TCK 1/1 100% used TDI 1/1 100% used TMS 1/1 100% used EBR 3/3 100% used TDO 1/1 100% used SLICE 585/1140 51% used Number of Signals: 1482 Number of Connections: 5091 Pin Constraint Summary: 8 out of 8 pins locked (100% locked). The following 1 signal is selected to use the primary clock routing resources: CLK_INT_inferred_clock (driver: osc_internal, clk load #: 270) The following 3 signals are selected to use the secondary clock routing resources: BSCAN_RESET (driver: bscan, clk load #: 0, sr load #: 153, ce load #: 0) CLK_OUT (driver: RTAVR/SLICE_538, clk load #: 8, sr load #: 0, ce load #: 109) RTAVR/r_pse_0_i (driver: RTAVR/SLICE_574, clk load #: 0, sr load #: 0, ce load #: 23) No signal is selected as Global Set/Reset. Starting Placer Phase 0. .......... Finished Placer Phase 0. REAL time: 23 secs Starting Placer Phase 1. ..................... Placer score = 276327. Finished Placer Phase 1. REAL time: 47 secs Starting Placer Phase 2. . Placer score = 273673 Finished Placer Phase 2. REAL time: 48 secs Clock Report Global Clock Resources: CLK_PIN : 0 out of 4 (0%) PLL : 0 out of 2 (0%) Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY "CLK_INT_inferred_clock" from comp "osc_internal" on site "OSC", clk load = 270 SECONDARY "BSCAN_RESET" from JRST on comp "bscan" on site "JTAG", clk load = 0, ce load = 0, sr load = 153 SECONDARY "CLK_OUT" from Q0 on comp "RTAVR/SLICE_538" on site "R14C2C", clk load = 8, ce load = 109, sr load = 0 SECONDARY "RTAVR/r_pse_0_i" from F1 on comp "RTAVR/SLICE_574" on site "R12C2D", clk load = 0, ce load = 23, sr load = 0 PRIMARY : 1 out of 4 (25%) SECONDARY: 3 out of 4 (75%) I/O Usage Summary (final): 8 out of 271 (3.0%) PIO sites used. 8 out of 211 (3.8%) bonded PIO sites used. Number of PIO comps: 8; differential: 0 Number of Vref pins used: 0 I/O Bank Usage Summary: +----------+---------------+------------+------------+------------+ | I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | +----------+---------------+------------+------------+------------+ | 0 | 0 / 24 ( 0%) | - | - | - | | 1 | 0 / 30 ( 0%) | - | - | - | | 2 | 0 / 26 ( 0%) | - | - | - | | 3 | 0 / 28 ( 0%) | - | - | - | | 4 | 8 / 29 ( 27%) | 2.5V | - | - | | 5 | 0 / 20 ( 0%) | - | - | - | | 6 | 0 / 28 ( 0%) | - | - | - | | 7 | 0 / 26 ( 0%) | - | - | - | +----------+---------------+------------+------------+------------+ Total placer CPU time: 25 secs Dumping design to file MachXO_Breakout_rtavr_xo.dir/5_1.ncd. 0 connections routed; 5091 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 55 secs Starting iterative routing. For each routing iteration the number inside the parenthesis is the total time (in picoseconds) the design is failing the timing constraints. For each routing iteration the router will attempt to reduce this number until the number of routing iterations is completed or the value is 0 meaning the design has fully met the timing constraints. End of iteration 1 5091 successful; 0 unrouted; (0) real time: 1 mins 1 secs Dumping design to file MachXO_Breakout_rtavr_xo.dir/5_1.ncd. Total CPU time 34 secs Total REAL time: 1 mins 2 secs Completely routed. End of route. 5091 routed (100.00%); 0 unrouted. Checking DRC ... No errors found. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Total REAL time to completion: 1 mins 16 secs Dumping design to file MachXO_Breakout_rtavr_xo.dir/5_1.ncd. All signals are completely routed. par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.