Lattice Mapping Report File for Design Module 'tool_test'


Design Information

Command line:   map -a MachXO2 -p LCMXO2-1200ZE -t TQFP144 -s 1 -oc Commercial
     MachXO2_Breakout_test_hdl_xo2.ngd -o MachXO2_Breakout_test_hdl_xo2_map.ncd
     -pr MachXO2_Breakout_test_hdl_xo2.prf -mp MachXO2_Breakout_test_hdl_xo2.mrp
     C:/Documents and Settings/suz/My
     Documents/rtavr_diamond/MachXO2_Breakout.lpf -c 0
Target Vendor:  LATTICE
Target Device:  LCMXO2-1200ZETQFP144
Target Performance:   1
Mapper:  xo2c00,  version:  Diamond_1.4_Production (87)
Mapped on:  02/25/12  15:45:42


Design Summary
   Number of registers:    207
      PFU registers:    207
      PIO registers:    0
   Number of SLICEs:           126 out of   640 (20%)
      SLICEs(logic/ROM):       126 out of   160 (79%)
      SLICEs(logic/ROM/RAM):     0 out of   480 (0%)
          As RAM:            0 out of   480 (0%)
          As Logic/ROM:      0 out of   480 (0%)
   Number of logic LUT4s:      76
   Number of distributed RAM:   0 (0 LUT4s)
   Number of ripple logic:     87 (174 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:     250
   Number of PIO sites used: 14 out of 108 (13%)
   Number of block RAMs:  1 out of 7 (14%)
   Number of GSRs:  0 out of 1 (0%)
   EFB used :       No
   JTAG used :      Yes
   Readback used :  No
   Oscillator used :  Yes
   Startup used :   No
   POR :            On
   Bandgap :        On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  1 out of 2 (50%)
   Number of PLLs:  1 out of 1 (100%)
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of CLKDIVC:  0 out of 4 (0%)
   Number of ECLKSYNCA:  0 out of 4 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  6
     Net CLK: 53 loads, 20 rising, 33 falling (Driver: osc_internal )
     Net CLK_IN0: 14 loads, 14 rising, 0 falling (Driver: clk_selector )

     Net CLK0_OUT: 14 loads, 14 rising, 0 falling (Driver: pll )
     Net CLK90_OUT: 13 loads, 13 rising, 0 falling (Driver: pll )
     Net CLK180_OUT: 13 loads, 13 rising, 0 falling (Driver: pll )
     Net CLK270_OUT: 13 loads, 13 rising, 0 falling (Driver: pll )
   Number of Clock Enables:  12
     Net n1: 1 loads, 1 LSLICEs
     Net n1580: 4 loads, 4 LSLICEs
     Net SPI_ECHO/n584: 1 loads, 1 LSLICEs
     Net n1582: 1 loads, 1 LSLICEs
     Net n1_adj_47: 1 loads, 1 LSLICEs
     Net n1_adj_48: 1 loads, 1 LSLICEs
     Net ISP/n1578: 5 loads, 5 LSLICEs
     Net ISP/n822: 4 loads, 4 LSLICEs
     Net ISP/n1576: 1 loads, 1 LSLICEs
     Net ISP/n1574: 4 loads, 4 LSLICEs
     Net ISP/ISP_LOAD: 1 loads, 0 LSLICEs
     Net ISP/n816: 4 loads, 4 LSLICEs
   Number of LSRs:  3
     Net ISP/n1574: 1 loads, 1 LSLICEs
     Net ISP/n856: 1 loads, 1 LSLICEs
     Net ISP/n853: 1 loads, 1 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net ISP/r_pr_inc: 18 loads
     Net r_count_3: 14 loads
     Net ISP/n1583: 11 loads
     Net n1582: 9 loads
     Net r_jtck: 9 loads
     Net ISP/n1578: 8 loads
     Net r_cs2: 8 loads
     Net ISP/ISP_STORE_DATA_6: 7 loads
     Net n1580: 7 loads
     Net r_sck: 7 loads




   Number of warnings:  24
   Number of errors:    0




Design Errors/Warnings

WARNING: Port RXD does not connect to any buffers
WARNING: C:/Documents and Settings/suz/My
     Documents/rtavr_diamond/MachXO2_Breakout.lpf (24): Error in IOBUF PORT
     "RXD" IO_TYPE=LVCMOS33 SLEWRATE=SLOW PULLMODE=NONE ;
: Port "RXD" does not exist in the design.. Disabled this preference.
WARNING: Port TXD does not connect to any buffers
WARNING: C:/Documents and Settings/suz/My
     Documents/rtavr_diamond/MachXO2_Breakout.lpf (25): Error in IOBUF PORT
     "TXD" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
: Port "TXD" does not exist in the design.. Disabled this preference.
WARNING: Preference parsing results:  2 semantic errors detected
WARNING: There are errors in the preference file, "C:/Documents and
     Settings/suz/My Documents/rtavr_diamond/MachXO2_Breakout.lpf".

WARNING: input pad net 'TXD' has no legal load
WARNING: input pad net 'RTS' has no legal load
WARNING: input pad net 'DTR' has no legal load
WARNING: input pad net 'RXD' has no legal load
WARNING: input pad net 'CTS' has no legal load
WARNING: logical net 'clk_count1_113_add_4_1/CI' has no driver
WARNING: logical net 'clk_count_111_add_4_1/CI' has no driver
WARNING: logical net 'clk_count0_112_add_4_1/CI' has no driver
WARNING: logical net 'clk_count3_115_add_4_1/CI' has no driver
WARNING: logical net 'clk_count4_116_add_4_1/CI' has no driver
WARNING: logical net 'clk_count2_114_add_4_1/CI' has no driver
WARNING: logical net 'ISP/r_pr_120_add_4_1/CI' has no driver
WARNING: OSCH 'osc_internal' has mismatching FREQUENCY preference value of 2.08
     MHz and NOM_FREQ value of 24.18 MHz.
WARNING: IO buffer missing for top level port TXD...logic will be discarded.
WARNING: IO buffer missing for top level port RTS...logic will be discarded.
WARNING: IO buffer missing for top level port DTR...logic will be discarded.
WARNING: IO buffer missing for top level port RXD...logic will be discarded.
WARNING: IO buffer missing for top level port CTS...logic will be discarded.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| EXTOSC_EN           | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| LED_0               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| LED_1               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| LED_2               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| LED_3               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| LED_4               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| LED_5               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| LED_6               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| LED_7               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| TOP_TDO             | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| TOP_TDI             | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| TOP_TCK             | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| TOP_TMS             | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| EXTOSC              | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+




Removed logic

Block m0_lut undriven or does not drive anything - clipped.
Block GSR_INST undriven or does not drive anything - clipped.
Signal ISP/n857 was merged into signal ISP/n1574
Signal n16_adj_46 was merged into signal CLK
Signal n1596 undriven or does not drive anything - clipped.
Signal GND_net undriven or does not drive anything - clipped.
Signal ISP/r_pr_120_add_4_17/S1 undriven or does not drive anything - clipped.
Signal ISP/r_pr_120_add_4_17/CO undriven or does not drive anything - clipped.
Signal ISP/r_pr_120_add_4_1/S0 undriven or does not drive anything - clipped.
Signal ISP/r_pr_120_add_4_1/CI undriven or does not drive anything - clipped.
Signal clk_count3_115_add_4_25/CO undriven or does not drive anything - clipped.
Signal clk_count2_114_add_4_1/S0 undriven or does not drive anything - clipped.
Signal clk_count2_114_add_4_1/CI undriven or does not drive anything - clipped.
Signal clk_count4_116_add_4_25/CO undriven or does not drive anything - clipped.
Signal clk_count4_116_add_4_1/S0 undriven or does not drive anything - clipped.
Signal clk_count4_116_add_4_1/CI undriven or does not drive anything - clipped.
Signal clk_count3_115_add_4_1/S0 undriven or does not drive anything - clipped.
Signal clk_count3_115_add_4_1/CI undriven or does not drive anything - clipped.
Signal clk_count1_113_add_4_25/CO undriven or does not drive anything - clipped.
Signal clk_count0_112_add_4_1/S0 undriven or does not drive anything - clipped.
Signal clk_count0_112_add_4_1/CI undriven or does not drive anything - clipped.
Signal clk_count0_112_add_4_25/CO undriven or does not drive anything - clipped.
Signal clk_count_111_add_4_1/S0 undriven or does not drive anything - clipped.
Signal clk_count_111_add_4_1/CI undriven or does not drive anything - clipped.
Signal clk_count_111_add_4_25/CO undriven or does not drive anything - clipped.
Signal clk_count2_114_add_4_25/CO undriven or does not drive anything - clipped.
Signal clk_count1_113_add_4_1/S0 undriven or does not drive anything - clipped.
Signal clk_count1_113_add_4_1/CI undriven or does not drive anything - clipped.
Block ISP/i358 was optimized away.
Block ISP/i4 was optimized away.
Block i1 was optimized away.



Memory Usage

/ISP:
    EBRs: 1
    RAM SLICEs: 0
    Logic SLICEs: 31
    PFU Registers: 34
    -Contains EBR mem0:  TYPE= SP8KC,  Width= 8,  Depth= 1024,  REGMODE= OUTREG,
         RESETMODE= SYNC,  ASYNC_RESET_RELEASE= SYNC,  WRITEMODE= WRITETHROUGH,
         GSR= DISABLED



PLL/DLL Summary
---------------

PLL 1:                                     Pin/Node Value
  PLL Instance Name:                                pll
  PLL Type:                                         EHXPLLJ
  Input Clock:                             NODE     CLK_IN0
  Output Clock(P):                         NODE     CLK0_OUT
  Output Clock(S):                         NODE     CLK90_OUT
  Output Clock(S2):                        NODE     CLK180_OUT

  Output Clock(S3):                        NODE     CLK270_OUT
  Feedback Signal:                         NODE     CLK0_OUT
  Reset Signal:                                     NONE
  M Divider Reset Signal:                           NONE
  C Divider Reset Signal:                           NONE
  D Divider Reset Signal:                           NONE
  Standby Signal:                                   NONE
  PLL LOCK signal:                                  NONE
  PLL Data bus CLK Signal:                          NONE
  PLL Data bus Strobe Signal:                       NONE
  PLL Data bus Reset Signal:                        NONE
  PLL Data bus Write Enable Signal:                 NONE
  PLL Data bus Address0:                            NONE
  PLL Data bus Address1:                            NONE
  PLL Data bus Address2:                            NONE
  PLL Data bus Address3:                            NONE
  PLL Data bus Address4:                            NONE
  PLL Data In bus Data0:                            NONE
  PLL Data In bus Data1:                            NONE
  PLL Data In bus Data2:                            NONE
  PLL Data In bus Data3:                            NONE
  PLL Data In bus Data4:                            NONE
  PLL Data In bus Data5:                            NONE
  PLL Data In bus Data6:                            NONE
  PLL Data In bus Data7:                            NONE
  PLL Data bus Acknowledge:                         NONE
  PLL Data Out bus Data0:                           NONE
  PLL Data Out bus Data1:                           NONE
  PLL Data Out bus Data2:                           NONE
  PLL Data Out bus Data3:                           NONE
  PLL Data Out bus Data4:                           NONE
  PLL Data Out bus Data5:                           NONE
  PLL Data Out bus Data6:                           NONE
  PLL Data Out bus Data7:                           NONE
  Input Clock Frequency (MHz):                      12.0000
  Output Clock(P) Frequency (MHz):                  NA
  Output Clock(S) Frequency (MHz):                  NA
  Output Clock(S2) Frequency (MHz):                 NA
  Output Clock(S3) Frequency (MHz):                 NA
  CLKOP Post Divider A Input:                       DIVA
  CLKOS Post Divider B Input:                       DIVB
  CLKOS2 Post Divider C Input:                      DIVC
  CLKOS3 Post Divider D Input:                      DIVD
  Pre Divider A Input:                              VCO_PHASE
  Pre Divider B Input:                              VCO_PHASE
  Pre Divider C Input:                              VCO_PHASE
  Pre Divider D Input:                              VCO_PHASE
  VCO Bypass A Input:                               VCO_PHASE
  VCO Bypass B Input:                               VCO_PHASE
  VCO Bypass C Input:                               VCO_PHASE
  VCO Bypass D Input:                               VCO_PHASE
  FB_MODE:                                          CLKOP
  CLKI Divider:                                     24
  CLKFB Divider:                                    24
  CLKOP Divider:                                    16
  CLKOS Divider:                                    16

  CLKOS2 Divider:                                   16
  CLKOS3 Divider:                                   16
  Fractional N Divider:                             0
  CLKOP Desired Phase Shift(degree):                -337
  CLKOP Trim Option Rising/Falling:                 RISING
  CLKOP Trim Option Delay:                          0
  CLKOS Desired Phase Shift(degree):                -331
  CLKOS Trim Option Rising/Falling:                 RISING
  CLKOS Trim Option Delay:                          0
  CLKOS2 Desired Phase Shift(degree):               -326
  CLKOS3 Desired Phase Shift(degree):               -320

OSC Summary
-----------

OSC 1:                                     Pin/Node Value
  OSC Instance Name:                                osc_internal
  OSC Type:                                         OSCH
  STDBY Input:                                      NONE
  OSC Output:                              NODE     CLK
  OSC Nominal Frequency (MHz):                      24.18

DCMA Summary
------------

DCMA 1:                                     Pin/Node Value
  DCMA Instance Name:                                clk_selector
  DCMA Type:                                         DCMA
  CLK0 Input:                              NODE     CLK
  CLK1 Input:                              PIN      EXTOSC_c
  SEL Input:                                        NONE
  DCMOUT Output:                           NODE     CLK_IN0



ASIC Components
---------------

Instance Name: osc_internal
         Type: OSCH
Instance Name: bscan
         Type: JTAGF
Instance Name: clk_selector
         Type: DCMA
Instance Name: pll
         Type: EHXPLLJ
Instance Name: ISP/mem0
         Type: SP8KC



Run Time and Memory Usage
-------------------------

   Total CPU Time: 2 secs
   Total REAL Time: 3 secs
   Peak Memory Usage: 33 MB






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