PAR: Place And Route Diamond_1.4_Production (87).
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.
Sat Feb 25 13:40:17 2012

C:/lscc/diamond/1.4/ispfpga\bin\nt\par -f MachXO2_Breakout_rtavr_xo2.p2t
MachXO2_Breakout_rtavr_xo2_map.ncd MachXO2_Breakout_rtavr_xo2.dir
MachXO2_Breakout_rtavr_xo2.prf

Preference file: MachXO2_Breakout_rtavr_xo2.prf.

Cost Table Summary
Level/      Number      Timing      Run         NCD
Cost [ncd]  Unrouted    Score       Time        Status
----------  --------    --------    -----       ------------
5_1   *     0           0           22:18       Complete        


* : Design saved.

par done!

Lattice Place and Route Report for Design "MachXO2_Breakout_rtavr_xo2_map.ncd"
Sat Feb 25 13:40:17 2012


Best Par Run
PAR: Place And Route Diamond_1.4_Production (87).
Command Line: C:/lscc/diamond/1.4/ispfpga\bin\nt\par -f MachXO2_Breakout_rtavr_xo2.p2t
MachXO2_Breakout_rtavr_xo2_map.ncd MachXO2_Breakout_rtavr_xo2.dir
MachXO2_Breakout_rtavr_xo2.prf
Preference file: MachXO2_Breakout_rtavr_xo2.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file MachXO2_Breakout_rtavr_xo2_map.ncd.
Design name: xo2_isp
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-1200ZE
Package:     TQFP144
Performance: 1
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/1.4/ispfpga.
Package Status:                     Final          Version 1.33
Performance Hardware Data Status:   Final          Version 22.4
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)      16/108          14% used
                     16/108          14% bonded

   SLICE            592/640          92% used

   OSC                1/1           100% used
   JTAG               1/1           100% used
   EBR                7/7           100% used
   PLL                1/1           100% used


WARNING - par: Input and feedback clock frequencies do not match their divider settings for pll 
WARNING - par: Output clock frequency on pin CLKOP of pll is   12.0 MHz, which with divider 16, requires internal VCO frequency to be   192.0 MHz (  12.0 MHz x 16), outside VCO valid range [400, 800] MHz. 
WARNING - par: Output clock frequency on pin CLKOP of pll is   12.0 MHz, which with divider 16, requires internal VCO frequency to be   192.0 MHz (  12.0 MHz x 16), outside VCO valid range [400, 800] MHz. 
WARNING - par: Output clock frequency on pin CLKOP of pll is   12.0 MHz, which with divider 16, requires internal VCO frequency to be   192.0 MHz (  12.0 MHz x 16), outside VCO valid range [400, 800] MHz. 
WARNING - par: Output clock frequency on pin CLKOP of pll is   12.0 MHz, which with divider 16, requires internal VCO frequency to be   192.0 MHz (  12.0 MHz x 16), outside VCO valid range [400, 800] MHz. 
Number of Signals: 1717
Number of Connections: 5326

Pin Constraint Summary:
   12 out of 16 pins locked (75% locked).

The following 5 signals are selected to use the primary clock routing resources:
    CLK_IN0 (driver: clk_selector, clk load #: 1)
    CLK0_OUT (driver: pll, clk load #: 110)
    CLK90_OUT (driver: pll, clk load #: 14)
    CLK180_OUT (driver: pll, clk load #: 146)
    CLK270_OUT (driver: pll, clk load #: 23)

The following 1 signal is selected to use the DCM clock routing resources:
    CLK_IN0 (driver: clk_selector, clk load #: 1)

The following 4 signals are selected to use the secondary clock routing resources:
    RTAVR/BSCAN_RESET_N (driver: RTAVR/IOR/i_port_c/bscan, clk load #: 0, sr load #: 171, ce load #: 0)
    RTAVR/CLK_B (driver: RTAVR/SLICE_570, clk load #: 9, sr load #: 0, ce load #: 0)
    RTAVR/CLK_L (driver: RTAVR/SLICE_644, clk load #: 8, sr load #: 0, ce load #: 0)
    RTAVR/S1/n1113 (driver: RTAVR/S1/SLICE_150, clk load #: 0, sr load #: 0, ce load #: 12)

No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
..........
Finished Placer Phase 0.  REAL time: 4 mins 9 secs 

Starting Placer Phase 1.
....................
Placer score = 353346.
Finished Placer Phase 1.  REAL time: 12 mins 17 secs 

Starting Placer Phase 2.
.
Placer score =  349872
Finished Placer Phase 2.  REAL time: 14 mins 6 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 1 out of 8 (12%)
  PLL        : 1 out of 1 (100%)
  DCM        : 1 out of 2 (50%)
  DCC        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "CLK0_OUT" from CLKOP on comp "pll" on PLL site "LPLL", clk load = 110
  PRIMARY "CLK90_OUT" from CLKOS on comp "pll" on PLL site "LPLL", clk load = 14
  PRIMARY "CLK180_OUT" from CLKOS2 on comp "pll" on PLL site "LPLL", clk load = 146
  PRIMARY "CLK270_OUT" from CLKOS3 on comp "pll" on PLL site "LPLL", clk load = 23
  PRIMARY DCM "CLK_IN0", total # of clk load = 1
    "CLK_IN0" from comp "clk_selector" on DCM site "DCM6"
     - DCM input "CLK_INT" from OSC on comp "osc_internal" on site "OSC"
     - DCM input "EXTOSC_c" from comp "EXTOSC" on CLK_PIN site "27 (PL9A)"
  SECONDARY "RTAVR/BSCAN_RESET_N" from JRSTN on comp "RTAVR/IOR/i_port_c/bscan" on site "JTAG", clk load = 0, ce load = 0, sr load = 171
  SECONDARY "RTAVR/S1/n1113" from F1 on comp "RTAVR/S1/SLICE_150" on site "R7C12C", clk load = 0, ce load = 12, sr load = 0
  SECONDARY "RTAVR/CLK_L" from F1 on comp "RTAVR/SLICE_644" on site "R7C12B", clk load = 8, ce load = 0, sr load = 0
  SECONDARY "RTAVR/CLK_B" from F0 on comp "RTAVR/SLICE_570" on site "R7C12D", clk load = 9, ce load = 0, sr load = 0

  PRIMARY  : 5 out of 8 (62%)
  SECONDARY: 4 out of 8 (50%)

Edge Clocks:
  No edge clock selected.




I/O Usage Summary (final):
   16 out of 108 (14.8%) PIO sites used.
   16 out of 108 (14.8%) bonded PIO sites used.
   Number of PIO comps: 16; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0        | 4 / 28 ( 14%)  | 2.5V       | -         |
| 1        | 10 / 26 ( 38%) | 3.3V       | -         |
| 2        | 0 / 28 (  0%)  | -          | -         |
| 3        | 2 / 26 (  7%)  | 3.3V       | -         |
+----------+----------------+------------+-----------+

Total placer CPU time: 12 mins 35 secs 

Dumping design to file MachXO2_Breakout_rtavr_xo2.dir/5_1.ncd.

WARNING - par: Input and feedback clock frequencies do not match their divider settings for pll 
WARNING - par: Output clock frequency on pin CLKOP of pll is   12.0 MHz, which with divider 16, requires internal VCO frequency to be   192.0 MHz (  12.0 MHz x 16), outside VCO valid range [400, 800] MHz. 
WARNING - par: Output clock frequency on pin CLKOP of pll is   12.0 MHz, which with divider 16, requires internal VCO frequency to be   192.0 MHz (  12.0 MHz x 16), outside VCO valid range [400, 800] MHz. 
WARNING - par: Output clock frequency on pin CLKOP of pll is   12.0 MHz, which with divider 16, requires internal VCO frequency to be   192.0 MHz (  12.0 MHz x 16), outside VCO valid range [400, 800] MHz. 
WARNING - par: Output clock frequency on pin CLKOP of pll is   12.0 MHz, which with divider 16, requires internal VCO frequency to be   192.0 MHz (  12.0 MHz x 16), outside VCO valid range [400, 800] MHz. 
0 connections routed; 5326 unrouted.
Starting router resource preassignment

WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
   Signal=RTAVR/RAM/CLK_90_270 loads=2 clock_loads=2

Completed router resource preassignment. Real time: 15 mins 56 secs 
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
5326 successful; 0 unrouted; (0) real time: 21 mins 43 secs 
Dumping design to file MachXO2_Breakout_rtavr_xo2.dir/5_1.ncd.
Total CPU time 19 mins 38 secs 
Total REAL time: 21 mins 43 secs 
Completely routed.
End of route.  5326 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.

WARNING - par: Input and feedback clock frequencies do not match their divider settings for pll 
WARNING - par: Output clock frequency on pin CLKOP of pll is   12.0 MHz, which with divider 16, requires internal VCO frequency to be   192.0 MHz (  12.0 MHz x 16), outside VCO valid range [400, 800] MHz. 
WARNING - par: Output clock frequency on pin CLKOP of pll is   12.0 MHz, which with divider 16, requires internal VCO frequency to be   192.0 MHz (  12.0 MHz x 16), outside VCO valid range [400, 800] MHz. 
WARNING - par: Output clock frequency on pin CLKOP of pll is   12.0 MHz, which with divider 16, requires internal VCO frequency to be   192.0 MHz (  12.0 MHz x 16), outside VCO valid range [400, 800] MHz. 
WARNING - par: Output clock frequency on pin CLKOP of pll is   12.0 MHz, which with divider 16, requires internal VCO frequency to be   192.0 MHz (  12.0 MHz x 16), outside VCO valid range [400, 800] MHz. 
Timing score: 0 

Total REAL time to completion: 22 mins 18 secs 

Dumping design to file MachXO2_Breakout_rtavr_xo2.dir/5_1.ncd.


All signals are completely routed.


par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.