I/O Timing Report WARNING - Input and feedback clock frequencies do not match their divider settings for pll WARNING - Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. // Design: xo2_isp // Package: TQFP144 // ncd File: machxo2_breakout_rtavr_xo2.ncd // Version: Diamond_1.4_Production (87) // Written on Sat Feb 25 14:04:16 2012 // M: Minimum Performance Grade // iotiming MachXO2_Breakout_rtavr_xo2.ncd MachXO2_Breakout_rtavr_xo2.prf I/O Timing Report (All units are in ns) Worst Case Results across Performance Grades (M, 3, 2, 1): // Input Setup and Hold Times Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- TOP_TCK EXTOSC R 47.384 1 8.039 1 TXD EXTOSC R 13.316 1 1.596 M // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ LED_0 EXTOSC R 24.917 1 8.907 M LED_1 EXTOSC R 24.378 1 8.655 M RXD EXTOSC R 27.291 1 8.503 M