Synthesis and Ngdbuild Report #Build: Synplify Pro F-2011.09L, Build 022R, Oct 19 2011 #install: C:\lscc\diamond\1.4\synpbase #OS: Windows XP 5.1 #Hostname: BANDIT $ Start of Compile #Fri Feb 24 19:24:50 2012 Synopsys Verilog Compiler, version comp560rcp1, Build 045R, built Oct 18 2011 @N|Running in 32-bit mode Copyright (C) 1994-2011 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. @I::"C:\lscc\diamond\1.4\synpbase\lib\lucent\machxo2.v" @I::"C:\lscc\diamond\1.4\synpbase\lib\vlog\scemi_objects.v" @I::"C:\lscc\diamond\1.4\synpbase\lib\vlog\hypermods.v" @I::"C:\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo2.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr_xo2\source\rtavr_defs.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr_xo2\source\rtavr_common.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_alu.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_cpi.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s0_fetch.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_smp.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\isp_sample\isp.v" @I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v" @I:"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\rtavr_defs.v" Verilog syntax check successful! File C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v changed - recompiling Selecting top level module xo2_isp @N: CG364 :"C:\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo2.v":1540:7:1540:11|Synthesizing module JTAGF @N: CG364 :"C:\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo2.v":1793:7:1793:10|Synthesizing module OSCH @N: CG364 :"C:\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo2.v":1520:7:1520:10|Synthesizing module DCMA @N: CG364 :"C:\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo2.v":1730:7:1730:13|Synthesizing module EHXPLLJ @N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\isp_sample\isp.v":83:7:83:9|Synthesizing module isp @N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":67:7:67:18|Synthesizing module rtavr_gpr_16 @N: CL134 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":427:0:427:5|Found RAM gpr_hi, depth=8, width=8 @N: CL134 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":427:0:427:5|Found RAM gpr_hi, depth=8, width=8 @N: CL134 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":427:0:427:5|Found RAM gpr_hi, depth=8, width=8 @N: CL134 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":427:0:427:5|Found RAM gpr_lo, depth=8, width=8 @N: CL134 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":427:0:427:5|Found RAM gpr_lo, depth=8, width=8 @N: CL134 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":427:0:427:5|Found RAM gpr_lo, depth=8, width=8 @N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":43:7:43:22|Synthesizing module rtavr_ior_timer0 BASE_ADDR=6'b010101 Generated name = rtavr_ior_timer0_21 @W: CL279 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":213:2:213:7|Pruning register bits 9 to 6 of r_prescaler[9:0] @N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":37:7:37:18|Synthesizing module rtavr_ior_ps CPUID=32'b00000000000000000000000000000000 Generated name = rtavr_ior_ps_0s @W: CL189 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":403:4:403:9|Register bit r_sph[2] is always 0, optimizing ... @W: CL189 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":403:4:403:9|Register bit r_sph[3] is always 0, optimizing ... @W: CL189 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":403:4:403:9|Register bit r_sph[4] is always 0, optimizing ... @W: CL189 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":403:4:403:9|Register bit r_sph[5] is always 0, optimizing ... @W: CL189 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":403:4:403:9|Register bit r_sph[6] is always 0, optimizing ... @W: CL189 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":403:4:403:9|Register bit r_sph[7] is always 0, optimizing ... @W: CL279 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":403:4:403:9|Pruning register bits 7 to 2 of r_sph[7:0] @N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":80:7:80:19|Synthesizing module rtavr_ior_spi BASE_ADDR=6'b101110 Generated name = rtavr_ior_spi_46 @W: CL169 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Pruning register r_ps[6:0] @W: CL169 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Pruning register r_count_en @N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":66:7:66:21|Synthesizing module rtavr_ior_usart BASE_ADDR=6'b001110 Generated name = rtavr_ior_usart_14 @W: CL169 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Pruning register rx_parity @W: CL265 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Pruning bit 9 of tx_data[9:0] -- not in use ... @W: CL271 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Pruning bits 10 to 9 of rx_data[10:0] -- not in use ... @W: CL265 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Pruning bit 3 of tx_ps[3:0] -- not in use ... @W: CL265 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Pruning bit 3 of rx_ps[3:0] -- not in use ... @N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":51:7:51:20|Synthesizing module rtavr_ior_port BASE_ADDR=6'b011011 Generated name = rtavr_ior_port_27 @N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":47:7:47:15|Synthesizing module rtavr_ior CPUID=32'b00000000000000000000000000000000 Generated name = rtavr_ior_0s @N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":43:7:43:16|Synthesizing module rtavr_sram SIZE=32'b00000000000000000000100000000000 Generated name = rtavr_sram_2048s @N: CL134 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":104:4:104:9|Found RAM mem, depth=2048, width=8 @W: CL271 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":104:4:104:9|Pruning bits 12 to 11 of r_addrb[12:0] -- not in use ... @N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":60:7:60:15|Synthesizing module rtavr_rom SIZE=32'b00000000000000000000100000000000 Generated name = rtavr_rom_2048s @W: CG532 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":283:2:283:8|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored @N: CL134 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Found RAM rom, depth=2048, width=16 @W: CL265 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Pruning bit 11 of r_addrb[11:0] -- not in use ... @W: CL118 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":163:1:163:2|Latch generated from always block for signal r_doa[15:0]; possible missing assignment in an if or case statement. @N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s0_fetch.v":30:7:30:20|Synthesizing module rtavr_s0_fetch @N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v":42:7:42:21|Synthesizing module rtavr_s1_decode @W: CL169 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v":736:2:736:7|Pruning register r_wdr @N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_alu.v":40:7:40:15|Synthesizing module rtavr_alu @N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr.v":76:7:76:11|Synthesizing module rtavr @N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":23:7:23:13|Synthesizing module xo2_isp @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input CLKFB on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PHASESEL1 on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PHASESEL0 on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PHASEDIR on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PHASESTEP on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input LOADREG on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input STDBY on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLWAKESYNC on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input RST on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input RESETM on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input RESETC on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input RESETD on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input ENCLKOP on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLCLK on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLRST on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLSTB on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLWE on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLDATI7 on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLDATI6 on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLDATI5 on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLDATI4 on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLDATI3 on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLDATI2 on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLDATI1 on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLDATI0 on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLADDR4 on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLADDR3 on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLADDR2 on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLADDR1 on instance pll, tying to 0 @W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Undriven input PLLADDR0 on instance pll, tying to 0 @W: CL246 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":31:17:31:19|Input port bits 1 to 0 of LED[7:0] are unused @W: CL156 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":205:16:205:18|*Input PIN[23:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible. @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":34:15:34:17|Input RTS is unused @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":34:20:34:22|Input DTR is unused @W: CL158 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":35:15:35:17|Inout CTS is unused @W: CL247 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":66:15:66:19|Input port bit 11 of ADDRA[11:0] is unused @W: CL247 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":72:17:72:21|Input port bit 12 of ADDRB[12:0] is unused @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":69:10:69:12|Input OEA is unused @W: CL246 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":49:15:49:19|Input port bits 12 to 11 of ADDRB[12:0] are unused @W: CL246 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":73:18:73:20|Input port bits 15 to 0 of PIN[23:0] are unused @W: CL157 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":71:18:71:20|*Output DDR has undriven bits -- simulation mismatch possible. @W: CL157 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|*Output PORT has undriven bits -- simulation mismatch possible. @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":62:10:62:15|Input WE_pin is unused @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":68:16:68:21|Input DI_pin is unused @W: CL138 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing register 'RXB8' because it is only assigned 0 or its original value. @W: CL138 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing register 'TXB8' because it is only assigned 0 or its original value. @W: CL189 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Register bit UPE is always 0, optimizing ... @W: CL189 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Register bit r_count_max_x[1] is always 0, optimizing ... @W: CL260 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Pruning register bit 1 of r_count_max_x[1:0] @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":76:10:76:17|Input WE_ubrrl is unused @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":77:10:77:17|Input WE_ubrrh is unused @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":78:10:78:17|Input WE_ucsrc is unused @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":97:10:97:15|Input XCK_IN is unused @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":98:10:98:16|Input XCK_DDR is unused @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":92:10:92:16|Input WE_spsr is unused @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":105:10:105:15|Input SS_DDR is unused @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":109:10:109:16|Input MISO_IN is unused @W: CL246 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":56:18:56:22|Input port bits 15 to 10 of SP_IN[15:0] are unused @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":55:10:55:17|Input WE_ocr0b is unused @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":56:10:56:17|Input WE_ocr0a is unused @W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":59:10:59:18|Input WE_tccr0a is unused @END Premap Report (contents appended below) @N:"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr_xo2\synlog\MachXO2_Breakout_rtavr_xo2_premap.srr" Synopsys Lattice Technology Pre-mapping, Version maplat, Build 239R, Built Oct 19 2011 10:56:21 Copyright (C) 1994-2011, Synopsys Inc. All Rights Reserved Product Version F-2011.09L Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N: MF249 |Running in 32-bit mode. @N: MF257 |Gated clock conversion enabled @N: MF546 |Generated clock conversion enabled Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB) Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB) @W: FX474 |User specified initial value found in some of the sequential elements in the design. Applying an initial value to a register may not deliver the best synthesis results. For example, registers with initial values may be preserved and retiming/pipelining may not be performed. To improve synthesis results you may want to remove the register initialization from the RTL code @W: FX469 :|Found undriven nets tri0_inst ..., mapper will optimize them. @W: FX469 :|Found undriven nets tri1_inst ..., mapper will optimize them. @W: FX469 :|Found undriven nets tri2_inst ..., mapper will optimize them. @W: FX469 :|Found undriven nets tri3_inst ..., mapper will optimize them. @W: FX469 :|Found undriven nets tri4_inst ..., mapper will optimize them. @W: FX469 :|Found undriven nets tri5_inst ..., mapper will optimize them. @W: MT462 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":110:16:110:67|Net RTAVR.ROM.CLK_B appears to be an unidentified clock source. Assuming default frequency. @W: MT462 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":156:18:156:31|Net RTAVR.ROM.CLK_L appears to be an unidentified clock source. Assuming default frequency. @W: MT462 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":80:20:80:57|Net RTAVR.RAM.CLK_90_270 appears to be an unidentified clock source. Assuming default frequency. syn_allowed_resources : blockrams=7 set on top level netlist xo2_isp Finished Pre Mapping Phase. (Time elapsed 0h:00m:02s; Memory used current: 76MB peak: 78MB) Pre Mapping successful! At Mapper Exit (Time elapsed 0h:00m:02s; Memory used current: 44MB peak: 78MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Fri Feb 24 19:24:59 2012 ###########################################################] Map & Optimize Report (contents appended below) @N:"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr_xo2\synlog\MachXO2_Breakout_rtavr_xo2_fpga_mapper.srr" Synopsys Lattice Technology Mapper, Version maplat, Build 239R, Built Oct 19 2011 10:56:21 Copyright (C) 1994-2011, Synopsys Inc. All Rights Reserved Product Version F-2011.09L Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N: MF249 |Running in 32-bit mode. @N: MF257 |Gated clock conversion enabled @N: MF546 |Generated clock conversion enabled Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N: MF203 |Set autoconstraint_io Starting Optimization and Mapping (Time elapsed 0h:00m:01s; Memory used current: 76MB peak: 78MB) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_1 on net PORT_1 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_2 on net PORT_2 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_3 on net PORT_3 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_4 on net PORT_4 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_5 on net PORT_5 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_6 on net PORT_6 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_7 on net PORT_7 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_8 on net PORT_8 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_9 on net PORT_9 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_10 on net PORT_10 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_11 on net PORT_11 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_12 on net PORT_12 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_13 on net PORT_13 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_14 on net PORT_14 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_15 on net PORT_15 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_16 on net PORT_16 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_1 on net DDR_1 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_2 on net DDR_2 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_3 on net DDR_3 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_4 on net DDR_4 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_5 on net DDR_5 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_6 on net DDR_6 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_7 on net DDR_7 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_8 on net DDR_8 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_9 on net DDR_9 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_10 on net DDR_10 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_11 on net DDR_11 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_12 on net DDR_12 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_13 on net DDR_13 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_14 on net DDR_14 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_15 on net DDR_15 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_16 on net DDR_16 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :|Tristate driver DDR_t[0] on net DDR[0] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[1] on net DDR[1] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[2] on net DDR[2] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[3] on net DDR[3] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[4] on net DDR[4] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[5] on net DDR[5] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[6] on net DDR[6] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[7] on net DDR[7] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[8] on net DDR[8] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[9] on net DDR[9] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[10] on net DDR[10] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[11] on net DDR[11] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[12] on net DDR[12] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[13] on net DDR[13] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[14] on net DDR[14] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[15] on net DDR[15] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[0] on net PORT[0] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[1] on net PORT[1] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[2] on net PORT[2] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[3] on net PORT[3] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[4] on net PORT[4] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[5] on net PORT[5] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[6] on net PORT[6] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[7] on net PORT[7] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[8] on net PORT[8] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[9] on net PORT[9] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[10] on net PORT[10] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[11] on net PORT[11] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[12] on net PORT[12] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[13] on net PORT[13] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[14] on net PORT[14] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[15] on net PORT[15] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver tri0_inst on net LED[7] has its enable tied to GND (module xo2_isp) @W: MO111 :|Tristate driver tri1_inst on net LED[6] has its enable tied to GND (module xo2_isp) @W: MO111 :|Tristate driver tri2_inst on net LED[5] has its enable tied to GND (module xo2_isp) @W: MO111 :|Tristate driver tri3_inst on net LED[4] has its enable tied to GND (module xo2_isp) @W: MO111 :|Tristate driver tri4_inst on net LED[3] has its enable tied to GND (module xo2_isp) @W: MO111 :|Tristate driver tri5_inst on net LED[2] has its enable tied to GND (module xo2_isp) @N: BN362 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Removing sequential instance i_spi.r_spi_mclk of view:PrimLib.sdffre(prim) in hierarchy view:work.rtavr_ior_0s(verilog) because there are no references to its outputs Available hyper_sources - for debug and ip models None Found @N: FX493 |Applying Initial value "00000000" on instance: ISP.r_data[7:0] @N: FX493 |Applying Initial value "00000000" on instance: ISP.r_spi[7:0] Finished RTL optimizations (Time elapsed 0h:00m:02s; Memory used current: 76MB peak: 78MB) @N:"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\isp_sample\isp.v":165:4:165:9|Found counter in view:work.isp(verilog) inst r_pr[15:0] @N:"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\isp_sample\isp.v":165:4:165:9|Found counter in view:work.isp(verilog) inst r_count[3:0] @N: FX702 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Found startup values on ram instance ROM.rom[15:0] @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_00 = 1DA221DA221DA221DCE91329C19AF0072CE1DCF00729C1DCEE1D6BE1D62C198CC198CC198CC198CC @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_01 = 1DAED1DAEE1BCED1DCDE1DAEE1BCED1DCDE1DAEE1BCED1DCDE1DA221DCD205CED044EE1A42E1DA22 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_02 = 05CD205CDE1DCED1DAED044EE1A42E1DA221DCD205CEE1DAED1DAEE1BCED1DCDE1DAEE1BCED1DCDE @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_03 = 134AA15AEE1DC88110BB1DCEE1BAAA08AAA1BCE40A429014A40B4AD1C42E1D0BB1D2D205CD205CD2 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_04 = 0242B172990F08F04497112F205299132EE13ADD1BADE1BAED1DAEA154AD1DCEE154AA1BCEE1D299 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_05 = 1285205E011102204498100221302212A0902090012201240904097012990F081044BB1329912E89 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_06 = 1BA991308D1DC221329811AE8044D003CE91E42217699130F003E9913C950E4C2052790F29205089 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_07 = 08A2204499132991329913A451129908A451329908ABB1BA4408A881104408A451129908A22044BB @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_08 = 08A891324511088176DD052F20444504488110291E42208A22176DD1329D08A2208A220449D08A22 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_09 = 1349B172BB1DC991242D1DC22176991329913A2204488110BB1BAEE08AEE0444513299132991329D @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_0A = 044221E0451F2991221100211018F204428132940B6B9044F40B29F00210020CF0449F1F2291FE92 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_0B = 022CE02292088491329F124440929913E1D1BAFD044F8132940B6B90929F128991E4DD1BED205E92 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_0C = 124220442204499132F902211000011E00002211038220222E1129908ABB124220529F1221003E01 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_0D = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF000C9 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_0E = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_0F = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_10 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_11 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_12 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_13 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_14 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_15 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_16 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_17 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_18 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_19 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_1A = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_1B = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_1C = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_1D = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_1E = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_3.INITVAL_1F = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_00 = 000FF1E0FF000FF1E0630663F060770E6000C0770C6100900601EF007E7000000000000000000000 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_01 = 1E0001E0000000000000000000000000000000000000000000000FF0000F1E0001FE0001EF0000FF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_02 = 1E00F1FE000C2500A0501FE0001EF0000FF0000F1E0000C0001E080010F0100081E080010F010008 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_03 = 038CC18000026330667700057000CC1B24400C0F1FEF1018CD1284001EF3186770660F1E00F1FE0F @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_04 = 07EF70E6350063D1FE50066DF1EA11022000A21102218022811028E1DCE100605198CC0207012211 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_05 = 07EFF1E877022FF1FE5107EFF0A2FF0B0F517E5F1EA7F0B6F507E581EA11006331FE770665102033 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_06 = 000330A630000FF0A213060011FE1B160151AEFF0EE330A6770EE550A03D01E0F1EA0500A5F1E633 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_07 = 000FF1FE51022110221102000022111FE00066331FE7700000000770EE0000000022111FEFF1FE77 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_08 = 00011022FF066330EE001EAD71FE001FE33066F51AEFF000FF0EE0006650000FF000FF1FE50000FF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_09 = 0BC53176DB00E5103EF0000FF0EE330A211020FF1FE330667700000000001FE000A2110221102210 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_0A = 1FEFF0EE000EA550BEFF1FEFF1E0F70EE710221F1EE751FE7000A500EEFF1FE0F0EE5B13075172A7 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_0B = 1FE01176571FEF50AA570AEFF1EA550A8F0000D00FEB10221F1EE751EA570BE550860001A071F657 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_0C = 0AEFF1FEFF1FE550AA751FEFF176BB00E770FEFF1E0FF176F2022111FE770BEFF1EA570BEFB16077 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_0D = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF000F4 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_0E = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_0F = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_10 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_11 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_12 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_13 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_14 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_15 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_16 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_17 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_18 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_19 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_1A = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_1B = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_1C = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_1D = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_1E = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_2.INITVAL_1F = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_00 = 11E7611E7611E7611ACD1820D020EB1460B142DB144201FCBA038DD1821102211044220442204421 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_01 = 11A8D11C681CC8E0D0E611C681CC8F0D0F611E681EC8F0D0F611C540D0F508C8E0A8681EA4611C76 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_02 = 0D0A70D0D70D28D11A8C0EC9818E6911876130D70D2810188C1186818C8C0D0D611A681AC8D0D0D6 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_03 = 052870D8980ECBA130FE1749800089130981B2870CE62010991128C08E69110FE104A70D0A70D0A7 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_04 = 11EED198D0106881FC080708F1C00119A9810C650CA580CA8510A8910E600EC981307608E6910422 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_05 = 1128910654130FE0A808110FE010FE0108011008100880108011008100DC106881FCDC19A0D19038 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_06 = 000CD0109D0ECFE01AC813A76130170CE6508AFE1B8CD006A911C48128440880F1C0801100910639 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_07 = 0EC760A80D1842204422054DC130761B8BA0EC54174BA000760A8BA130BA130DC174981B8760A8DC @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_08 = 1B8980ECDC174981FC001749A130540A8760A8760AC54174BA1B80019A07130980EC760A80813098 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_09 = 0060811E450A80D192860A8321B8CD0042204667112BA130FE000BA130760A87601AC20442204425 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_0A = 0CE890CE9810C7812A4305EEB1406A17CF50862F1DEE011299110920EC760A40804A081028011018 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_0B = 1740517403130760F09E00654064340A62004050044950862F1DEE01309F00E670240300E0205203 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_0C = 006980EC54064980EC63130761FCBA05EEB15EEB140FE1743A0A8321FCFE012870D28A0B28B142BA @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_0D = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF000FF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_0E = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_0F = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_10 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_11 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_12 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_13 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_14 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_15 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_16 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_17 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_18 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_19 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_1A = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_1B = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_1C = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_1D = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_1E = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_1F = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_00 = 006DC1E0DC008DC1E04F1FEF3084110BA100809109A120C80001AE11FE1B19AEF0022308A67112A0 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_01 = 1E8F61E20008217020A0034001A21002030026000C219020C003EDC0424D1821C1B82103AC103EDC @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_02 = 19EAD18010104640C661020040C200056100020100000014FC1F60F1C0FE01E101E20F080F101E40 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_03 = 1F6A91020004843042ED000680002315C320101F1C20F0001A1C2070020B142ED0BE2D19E6D1806D @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_04 = 0CA4E1BEF8022000EC81002070D0FF1FE001043F01E800560D03E1304201004041FCDC0806011EFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_05 = 03EF50829802076130810707610676100880D0861106810C880D080110FF022060A8ED1FE8F1E201 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_06 = 000FF100110067611EF00360D0EC85080000EA761DAFF10013062A70C8101F0970D0F81E48508011 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_07 = 002980EC8F1FEFF1FEFF1FC0C112991EE0419ADD1FEED00000002CB152000020C112991EE980ECED @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_08 = 00889132FF086211DA001407A0A801130CB152600ECBA002761DA001FE8900254002980EC8500254 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_09 = 1088F1FE0E0088F1EE64000541DAFF11EFF1F4450CE43042ED00000002000EC0111EFF1FEFF1FEFC @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_0A = 156EF12C0012E770CA4304A430480A17CF00221F1BCD804A1000E69066760EC2004A8101C88020F8 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_0B = 17471174831FEF10000E106FF1E2000102B1887F0B2700221F1BCD81E20611E101446108EA712E83 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_0C = 106FE174980EC000009A130760A83200A4305EEB15ABA174A1002111FAED116A910009152870C076 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_0D = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF002F8 @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_0E = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_0F = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_10 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_11 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_12 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_13 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_14 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_15 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_16 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_17 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_18 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_19 = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_1A = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_1B = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_1C = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_1D = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_1E = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @N: FX276 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_1F = 1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF1FEFF @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Boundary register ROM.r_addrb[10] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Boundary register ROM.r_addrb[9] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Boundary register ROM.r_addrb[8] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Boundary register ROM.r_addrb[7] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Boundary register ROM.r_addrb[6] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Boundary register ROM.r_addrb[5] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Boundary register ROM.r_addrb[4] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Boundary register ROM.r_addrb[3] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Boundary register ROM.r_addrb[2] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Boundary register ROM.r_addrb[1] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Boundary register ROM.r_addrb[0] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":104:4:104:9|Boundary register RAM.r_addrb[10] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":104:4:104:9|Boundary register RAM.r_addrb[9] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":104:4:104:9|Boundary register RAM.r_addrb[8] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":104:4:104:9|Boundary register RAM.r_addrb[7] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":104:4:104:9|Boundary register RAM.r_addrb[6] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":104:4:104:9|Boundary register RAM.r_addrb[5] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":104:4:104:9|Boundary register RAM.r_addrb[4] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":104:4:104:9|Boundary register RAM.r_addrb[3] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":104:4:104:9|Boundary register RAM.r_addrb[2] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":104:4:104:9|Boundary register RAM.r_addrb[1] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":104:4:104:9|Boundary register RAM.r_addrb[0] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N: MF179 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr.v":1052:12:1052:26|Found 8 bit by 8 bit '==' comparator, 'un4_SBIX_BIT_OUT' @N:"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Found counter in view:work.rtavr_ior_0s(verilog) inst i_spi.r_count[3:0] @N: BN362 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":126:2:126:7|Removing sequential instance i_port_c.r_pin[2] of view:UNILIB.FDR(PRIM) in hierarchy view:work.rtavr_ior_0s(verilog) because there are no references to its outputs @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":126:2:126:7|Boundary register i_port_c.r_pin[2] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Found counter in view:work.rtavr_ior_usart_14(verilog) inst rx_count[4:0] @N:"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Found counter in view:work.rtavr_ior_usart_14(verilog) inst tx_count[4:0] @N:"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Found counter in view:work.rtavr_ior_usart_14(verilog) inst r_ps[11:0] @N: BN362 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v":736:2:736:7|Removing sequential instance S1.r_pc_rd of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.rtavr(verilog) because there are no references to its outputs @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v":736:2:736:7|Boundary register S1.r_pc_rd packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N: BN362 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance IOR.i_usart.tx_mclk of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr(verilog) because there are no references to its outputs Finished factoring (Time elapsed 0h:00m:09s; Memory used current: 85MB peak: 86MB) #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[ ====================================================================================== Instance:Pin Generated Clock Optimization Status ====================================================================================== r_cs1_prev:C Not Done RTAVR.ROM.r_dobh:C Not Done RTAVR.C_in_l:C Not Done RTAVR.IOR.r_do[7]:C Not Done RTAVR.IOR.IOR_PS0.r_sreg[7]:C Not Done ISP.r_spi[3]:C Not Done ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################] Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:09s; Memory used current: 82MB peak: 86MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:12s; Memory used current: 81MB peak: 86MB) @N: FX404 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v":667:21:669:22|Found addmux in view:work.xo2_isp(verilog) inst RTAVR.S1.r_pc_4_2[11:0] from RTAVR.S1.un1_r_pc[11:0] @N: FX404 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":364:23:364:47|Found addmux in view:work.xo2_isp(verilog) inst RTAVR.GPR.DI2_AL_i_m2[15:0] from RTAVR.GPR.un1_gpr_lo_1[15:0] Starting Early Timing Optimization (Time elapsed 0h:00m:14s; Memory used current: 82MB peak: 86MB) Finished Early Timing Optimization (Time elapsed 0h:00m:15s; Memory used current: 82MB peak: 86MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:16s; Memory used current: 81MB peak: 86MB) Finished preparing to map (Time elapsed 0h:00m:22s; Memory used current: 82MB peak: 86MB) Finished technology mapping (Time elapsed 0h:00m:33s; Memory used current: 110MB peak: 123MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ ------------------------------------------------------------ Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:36s; Memory used current: 111MB peak: 123MB) @N: FX164 |The option to pack flops in the IOB has not been specified @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":31:17:31:19|Tristate driver LED_obuft_2_.un1[0] on net LED[2] has its enable tied to GND (module xo2_isp) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":31:17:31:19|Tristate driver LED_obuft_3_.un1[0] on net LED[3] has its enable tied to GND (module xo2_isp) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":31:17:31:19|Tristate driver LED_obuft_4_.un1[0] on net LED[4] has its enable tied to GND (module xo2_isp) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":31:17:31:19|Tristate driver LED_obuft_5_.un1[0] on net LED[5] has its enable tied to GND (module xo2_isp) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":31:17:31:19|Tristate driver LED_obuft_6_.un1[0] on net LED[6] has its enable tied to GND (module xo2_isp) @W: MO111 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":31:17:31:19|Tristate driver LED_obuft_7_.un1[0] on net LED[7] has its enable tied to GND (module xo2_isp) @N: FO126 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":427:0:427:5|Generating RAM RTAVR.GPR.gpr_lo_2[7:0] @N: FO126 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":427:0:427:5|Generating RAM RTAVR.GPR.gpr_lo_1[7:0] @N: FO126 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":427:0:427:5|Generating RAM RTAVR.GPR.gpr_lo[7:0] @N: FO126 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":427:0:427:5|Generating RAM RTAVR.GPR.gpr_hi_2[7:0] @N: FO126 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":427:0:427:5|Generating RAM RTAVR.GPR.gpr_hi_1[7:0] @N: FO126 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":427:0:427:5|Generating RAM RTAVR.GPR.gpr_hi[7:0] @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":221:2:221:7|Boundary register RTAVR.IOR.IOR_PS0.i_timer0.r_tcnt0_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":221:2:221:7|Boundary register RTAVR.IOR.IOR_PS0.i_timer0.r_tcnt0_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":221:2:221:7|Boundary register RTAVR.IOR.IOR_PS0.i_timer0.r_tcnt0_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr.v":1313:2:1313:7|Boundary register RTAVR.r_int_vec_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr.v":1313:2:1313:7|Boundary register RTAVR.r_int_vec_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr.v":1313:2:1313:7|Boundary register RTAVR.r_int_vec_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr.v":1313:2:1313:7|Boundary register RTAVR.r_int_vec_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v":736:2:736:7|Boundary register RTAVR.S1.r_pc_11_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v":736:2:736:7|Boundary register RTAVR.S1.r_pc_10_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v":736:2:736:7|Boundary register RTAVR.S1.r_pc_9_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v":736:2:736:7|Boundary register RTAVR.S1.r_pc_8_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v":736:2:736:7|Boundary register RTAVR.S1.r_pc_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v":736:2:736:7|Boundary register RTAVR.S1.r_pc_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v":736:2:736:7|Boundary register RTAVR.S1.r_pc_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":221:2:221:7|Boundary register RTAVR.IOR.IOR_PS0.i_timer0.r_tcnt0_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":221:2:221:7|Boundary register RTAVR.IOR.IOR_PS0.i_timer0.r_tcnt0_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":221:2:221:7|Boundary register RTAVR.IOR.IOR_PS0.i_timer0.r_tcnt0_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":221:2:221:7|Boundary register RTAVR.IOR.IOR_PS0.i_timer0.r_tcnt0_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":221:2:221:7|Boundary register RTAVR.IOR.IOR_PS0.i_timer0.r_tcnt0_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":221:2:221:7|Boundary register RTAVR.IOR.IOR_PS0.i_timer0.r_tim0_compb.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":221:2:221:7|Boundary register RTAVR.IOR.IOR_PS0.i_timer0.r_tim0_compa.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":221:2:221:7|Boundary register RTAVR.IOR.IOR_PS0.i_timer0.r_tim0_ovf.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr.v":1313:2:1313:7|Boundary register RTAVR.r_int_vec_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Boundary register RTAVR.IOR.i_spi.SPE.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Boundary register RTAVR.IOR.i_spi.SPIE.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Boundary register RTAVR.IOR.i_spi.r_spsr_lck.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Boundary register RTAVR.IOR.i_spi.c.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Boundary register RTAVR.IOR.i_spi.r_spif.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Boundary register RTAVR.IOR.i_spi.r_spdr_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Boundary register RTAVR.IOR.i_spi.r_spdr_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Boundary register RTAVR.IOR.i_spi.r_spdr_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Boundary register RTAVR.IOR.i_spi.r_spdr_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Boundary register RTAVR.IOR.i_spi.r_spdr_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Boundary register RTAVR.IOR.i_spi.r_spdr_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Boundary register RTAVR.IOR.i_spi.r_spdr_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Boundary register RTAVR.IOR.i_spi.r_spdr_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_ddr_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_ddr_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_ddr_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_ddr_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_ddr_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_ddr_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_ddr_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_ddr_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_port_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_port_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_port_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_port_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_port_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_port_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_port_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":137:2:137:7|Boundary register RTAVR.IOR.i_port_c.r_port_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.RXCIE.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.TXCIE.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.UDRIE.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_tx_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_tx_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_tx_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_tx_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_tx_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_tx_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_tx_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_tx_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.rx_en.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.tx_en.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.tx_data_load.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.RXC.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.DOR.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.rx_data_8_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.rx_data_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.rx_data_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.rx_data_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.rx_data_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.rx_data_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.rx_data_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.rx_data_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.rx_data_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.TXC.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_rx_7_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_rx_6_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_rx_5_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_rx_4_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_rx_3_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_rx_2_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_rx_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_udr_rx_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.r_txd.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.rx_count_en.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.rx_data_rdy.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.FE.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Boundary register RTAVR.IOR.i_usart.rx_udr_rdy.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":221:2:221:7|Boundary register RTAVR.IOR.IOR_PS0.i_timer0.tsm.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":221:2:221:7|Boundary register RTAVR.IOR.IOR_PS0.i_timer0.r_cs0.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":436:2:436:7|Boundary register RTAVR.IOR.IOR_PS0.gi_int0_ie.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":436:2:436:7|Boundary register RTAVR.IOR.IOR_PS0.mcucr_isc_1_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":436:2:436:7|Boundary register RTAVR.IOR.IOR_PS0.mcucr_isc_0_.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":436:2:436:7|Boundary register RTAVR.IOR.IOR_PS0.t0_compa_ie.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":436:2:436:7|Boundary register RTAVR.IOR.IOR_PS0.t0_compb_ie.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":436:2:436:7|Boundary register RTAVR.IOR.IOR_PS0.t0_ovf_ie.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":436:2:436:7|Boundary register RTAVR.IOR.IOR_PS0.t0_compa.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":436:2:436:7|Boundary register RTAVR.IOR.IOR_PS0.t0_compb.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":436:2:436:7|Boundary register RTAVR.IOR.IOR_PS0.t0_ovf.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @A: BN291 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":436:2:436:7|Boundary register RTAVR.IOR.IOR_PS0.gi_int0.fb packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. Finished restoring hierarchy (Time elapsed 0h:00m:39s; Memory used current: 111MB peak: 123MB) Writing Analyst data base C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr_xo2\MachXO2_Breakout_rtavr_xo2.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:42s; Memory used current: 112MB peak: 123MB) Writing EDIF Netlist and constraint files F-2011.09L Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:45s; Memory used current: 116MB peak: 123MB) Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:46s; Memory used current: 113MB peak: 123MB) ================= Gated clock report ================= The following instances have NOT been converted Seq Inst Instance Port Clock Reason for not converting ----------------------------------------------------------------------------------------------------------------------------------------------------------- RTAVR.RAM.mem_mem_0_1 CLK RTAVR.RAM.CLK_90_270_0_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.RAM.mem_mem_0_0 CLK RTAVR.RAM.CLK_90_270_0_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.rom_rom_0_3 CLK RTAVR.ROM.CLK_B_0_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.rom_rom_0_2 CLK RTAVR.ROM.CLK_B_0_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.rom_rom_0_1 CLK RTAVR.ROM.CLK_B_0_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.rom_rom_0_0 CLK RTAVR.ROM.CLK_B_0_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[15] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[14] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[13] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[12] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[11] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[10] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[9] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[8] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[7] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[6] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[5] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[4] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[3] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[2] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[1] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.DOA[0] CK RTAVR.ROM.r_doa3 Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.r_dobh CK RTAVR.ROM.CLK_B_0_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.r_tmpb[7] CK RTAVR.ROM.CLK_B_0_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.r_tmpb[6] CK RTAVR.ROM.CLK_B_0_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.r_tmpb[5] CK RTAVR.ROM.CLK_B_0_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.r_tmpb[4] CK RTAVR.ROM.CLK_B_0_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.r_tmpb[3] CK RTAVR.ROM.CLK_B_0_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.r_tmpb[2] CK RTAVR.ROM.CLK_B_0_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.r_tmpb[1] CK RTAVR.ROM.CLK_B_0_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. RTAVR.ROM.r_tmpb[0] CK RTAVR.ROM.CLK_B_0_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. =========================================================================================================================================================== ================= End gated clock report ================= Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:46s; Memory used current: 113MB peak: 123MB) Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:46s; Memory used current: 113MB peak: 123MB) @N: MF333 |Generated clock conversion enabled, but no generated clocks found in design Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:46s; Memory used current: 113MB peak: 123MB) @W: MT246 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":117:3:117:5|Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":100:7:100:18|Blackbox DCMA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":78:30:78:41|Blackbox OSCH is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr-0.9.5\xo2_sample\xo2_isp.v":42:14:42:18|Blackbox JTAGF is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT420 |Found inferred clock xo2_isp|CLK270_OUT_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:CLK270_OUT" @W: MT420 |Found inferred clock xo2_isp|CLK90_OUT_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:CLK90_OUT" @W: MT420 |Found inferred clock xo2_isp|CLK0_OUT_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:CLK0_OUT" @W: MT420 |Found inferred clock xo2_isp|CLK180_OUT_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:CLK180_OUT" ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Feb 24 19:25:52 2012 # Top view: xo2_isp Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 3 Constraint File(s): @N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing. Performance Summary ******************* Worst slack in design: 488.051 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------ xo2_isp|CLK0_OUT_inferred_clock 1.0 MHz 46.2 MHz 1000.000 21.647 978.353 inferred Inferred_clkgroup_1 xo2_isp|CLK90_OUT_inferred_clock 1.0 MHz 183.4 MHz 1000.000 5.452 994.548 inferred Inferred_clkgroup_2 xo2_isp|CLK180_OUT_inferred_clock 1.0 MHz 41.8 MHz 1000.000 23.898 488.051 inferred Inferred_clkgroup_0 xo2_isp|CLK270_OUT_inferred_clock 1.0 MHz 57.6 MHz 1000.000 17.368 982.632 inferred Inferred_clkgroup_3 System 1.0 MHz 153.8 MHz 1000.000 6.504 993.496 system system_clkgroup ========================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 1000.000 993.496 | No paths - | No paths - | No paths - System xo2_isp|CLK180_OUT_inferred_clock | 1000.000 992.857 | No paths - | 1000.000 996.286 | No paths - System xo2_isp|CLK0_OUT_inferred_clock | 1000.000 988.267 | No paths - | No paths - | No paths - System xo2_isp|CLK90_OUT_inferred_clock | 1000.000 984.551 | No paths - | No paths - | No paths - System xo2_isp|CLK270_OUT_inferred_clock | 1000.000 988.805 | No paths - | No paths - | No paths - xo2_isp|CLK180_OUT_inferred_clock System | 1000.000 993.919 | No paths - | No paths - | 1000.000 998.956 xo2_isp|CLK180_OUT_inferred_clock xo2_isp|CLK180_OUT_inferred_clock | 1000.000 986.684 | 1000.000 991.522 | 500.000 488.051 | 500.000 491.750 xo2_isp|CLK180_OUT_inferred_clock xo2_isp|CLK0_OUT_inferred_clock | Diff grp - | No paths - | No paths - | Diff grp - xo2_isp|CLK180_OUT_inferred_clock xo2_isp|CLK90_OUT_inferred_clock | Diff grp - | No paths - | No paths - | Diff grp - xo2_isp|CLK180_OUT_inferred_clock xo2_isp|CLK270_OUT_inferred_clock | Diff grp - | No paths - | No paths - | Diff grp - xo2_isp|CLK0_OUT_inferred_clock xo2_isp|CLK180_OUT_inferred_clock | Diff grp - | No paths - | Diff grp - | No paths - xo2_isp|CLK0_OUT_inferred_clock xo2_isp|CLK0_OUT_inferred_clock | 1000.000 978.353 | No paths - | No paths - | No paths - xo2_isp|CLK0_OUT_inferred_clock xo2_isp|CLK90_OUT_inferred_clock | Diff grp - | No paths - | No paths - | No paths - xo2_isp|CLK0_OUT_inferred_clock xo2_isp|CLK270_OUT_inferred_clock | Diff grp - | No paths - | No paths - | No paths - xo2_isp|CLK90_OUT_inferred_clock xo2_isp|CLK180_OUT_inferred_clock | Diff grp - | No paths - | Diff grp - | No paths - xo2_isp|CLK90_OUT_inferred_clock xo2_isp|CLK0_OUT_inferred_clock | Diff grp - | No paths - | No paths - | No paths - xo2_isp|CLK90_OUT_inferred_clock xo2_isp|CLK90_OUT_inferred_clock | 1000.000 994.548 | No paths - | No paths - | No paths - xo2_isp|CLK90_OUT_inferred_clock xo2_isp|CLK270_OUT_inferred_clock | Diff grp - | No paths - | No paths - | No paths - xo2_isp|CLK270_OUT_inferred_clock xo2_isp|CLK180_OUT_inferred_clock | Diff grp - | No paths - | Diff grp - | No paths - xo2_isp|CLK270_OUT_inferred_clock xo2_isp|CLK0_OUT_inferred_clock | Diff grp - | No paths - | No paths - | No paths - xo2_isp|CLK270_OUT_inferred_clock xo2_isp|CLK90_OUT_inferred_clock | Diff grp - | No paths - | No paths - | No paths - xo2_isp|CLK270_OUT_inferred_clock xo2_isp|CLK270_OUT_inferred_clock | 1000.000 982.632 | No paths - | No paths - | No paths - ==================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* Input Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock ----------------------------------------------------------------------------- CTS NA NA NA NA NA DTR NA NA NA NA NA EXTOSC System (rising) NA 0.000 993.496 RTS NA NA NA NA NA TOP_TCK System (rising) NA 0.000 998.020 TOP_TDI System (rising) NA 0.000 998.020 TOP_TMS System (rising) NA 0.000 998.020 TXD System (rising) NA 0.000 994.867 ============================================================================= Output Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock ---------------------------------------------------------------------------------------------------------- EXTOSC_EN System (rising) NA 6.504 1000.000 LED[0] xo2_isp|CLK180_OUT_inferred_clock (rising) NA 6.017 1000.000 LED[1] xo2_isp|CLK180_OUT_inferred_clock (rising) NA 6.017 1000.000 LED[2] NA NA NA NA NA LED[3] NA NA NA NA NA LED[4] NA NA NA NA NA LED[5] NA NA NA NA NA LED[6] NA NA NA NA NA LED[7] NA NA NA NA NA RXD xo2_isp|CLK180_OUT_inferred_clock (rising) NA 6.081 1000.000 TOP_TDO System (rising) NA 3.884 1000.000 ========================================================================================================== ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report Part: lcmxo2_1200ze-1 Register bits: 419 of 1280 (33%) Latch bits: 16 PIC Latch: 0 I/O cells: 16 Details: CCU2D: 89 DPR16X4C: 10 FD1P3AX: 64 FD1P3IX: 104 FD1P3JX: 10 FD1S1AY: 16 FD1S3AX: 36 FD1S3IX: 201 FD1S3JX: 3 GSR: 1 IB: 5 IFS1P3IX: 1 INV: 8 L6MUX21: 4 OB: 11 ORCALUT4: 981 PFUMX: 77 PUR: 1 SP8KC: 6 SPR16X4C: 2 VHI: 1 VLO: 1 false: 15 true: 15 Mapper successful! At Mapper Exit (Time elapsed 0h:00m:47s; Memory used current: 28MB peak: 123MB) Process took 0h:00m:53s realtime, 0h:00m:47s cputime # Fri Feb 24 19:25:53 2012 ###########################################################]