Synthesis and Ngdbuild Report synthesis: version Diamond_1.4_Production (87) Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Sat Feb 25 15:45:34 2012 Command Line: synthesis -f MachXO2_Breakout_test_hdl_xo2_lattice.synproj -- all messages logged in file synthesis.log Synthesis Options INFO: Synthesis Options: (LSE-1022) INFO: -a option is = MachXO2 INFO: -s option is = 1 INFO: -t option is = TQFP144 INFO: -d option is = LCMXO2-1200ZE INFO: Using package TQFP144 INFO: Using performance grade 1 INFO: INFO: ########################################################## INFO: ### Lattice Family : MachXO2A INFO: ### Device : LCMXO2-1200ZE INFO: ### Package : TQFP144 INFO: ### Speed : 1 INFO: ########################################################## INFO: INFO: Optimization Goal = Balanced INFO: -top option is not used INFO: Target Frequency = 200.000000 MHz INFO: Max Fanout = 1000 INFO: Timing Path count = 3 INFO: bram Utilization = 100.000000 % INFO: dsp usage = TRUE (default) INFO: dsp utilization = 100 (default) INFO: fsm_encoding_style = auto INFO: Mux style = Auto INFO: Use Carry Chain = TRUE INFO: carry_chain_length = 0 INFO: Use IO Insertion = TRUE INFO: Use IO Reg = TRUE INFO: Resource Sharing = TRUE INFO: Propagate Constants = TRUE INFO: Remove Duplicate Registers = TRUE INFO: force_gsr = auto INFO: ROM style = auto INFO: RAM style = auto INFO: -comp option is FALSE INFO: -syn option is FALSE INFO: -p C:/Documents and Settings/suz/My Documents/rtavr_diamond/test_hdl_xo2/source (searchpath added) INFO: -p C:/Documents and Settings/suz/My Documents/rtavr_diamond (searchpath added) INFO: -p C:/lscc/diamond/1.4/ispfpga/xo2c00/data (searchpath added) INFO: -p C:/Documents and Settings/suz/My Documents/rtavr_diamond/test_hdl_xo2 (searchpath added) INFO: -p C:/Documents and Settings/suz/My Documents/rtavr_diamond (searchpath added) INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/test_hdl_xo2/source/tool_test.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr_tools-0.6/test_hdl/isp.v INFO: Verilog design file = C:/Documents and Settings/suz/My Documents/rtavr_diamond/rtavr_tools-0.6/test_hdl/spi_echo.v INFO: Ngd file = MachXO2_Breakout_test_hdl_xo2.ngd INFO: -sdc option: sdc file input not used INFO: -lpf option: output file option is OFF INFO: hardtimer checking is enabled (default); -dt option not used INFO: -r option is OFF [ Remove LOC Properties is OFF ] -- Technology check ok...MachXO, MachXO2... INFO: The default vhdl library search path is now "c:/lscc/diamond/1.4/cae_library/vhdl_packages/vdbs" (VHDL-1504) INFO: ######## Converting i/o port : RXD to INPUT ... (LSE-1068) INFO: ######## Converting i/o port : CTS to INPUT ... (LSE-1068) INFO: ######## Converting i/o port : EXTOSC_EN to OUTPUT ... (LSE-1067) INFO: ######## Found 1 RAM Nets in design (LSE-1115) INFO: ######## Mapping RAM Net \ISP/mem to 1 EBR blocks in SINGLE_PORT Mode INFO: GSR Instance connected to net: \ISP/n1 (LSE-1148) INFO: GSR will not be inferred since no asynchronous signal was found in netlist (LSE-1147) WARNING: No lpf file will be written because -lpf option is not used or set to 0 INFO: Applying 200.000000 MHz constraint to all clocks (LSE-5000) INFO: Results of ngd drc checks are available in tool_test_drc.log INFO: All blocks are expanded and NGD expansion is successful INFO: Writing ngd file MachXO2_Breakout_test_hdl_xo2.ngd ################### Begin Area Report (tool_test)###################### Number of register bits => 207 of 5444 (3 % ) CCU2D => 87 DCMA => 1 EHXPLLJ => 1 FD1P3AX => 42 FD1P3IX => 2 FD1S3AX => 161 FD1S3IX => 1 FD1S3JX => 1 GSR => 1 IB => 4 INV => 12 JTAGF => 1 LUT4 => 66 OB => 10 OSCH => 1 PFUMX => 3 SP8KC => 1 ################### End Area Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 7 Net : CLK, loads : 35 Net : CLK_IN0, loads : 26 Net : CLK90_OUT, loads : 25 Net : CLK0_OUT, loads : 25 Net : CLK180_OUT, loads : 25 Net : CLK270_OUT, loads : 25 Net : n16, loads : 14 Clock Enable Nets Number of Clock Enables: 11 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : r_pr_inc, loads : 18 Net : r_count_3, loads : 13 Net : n1578, loads : 11 Net : n1583, loads : 11 Net : n1580, loads : 10 Net : n1582, loads : 9 Net : r_jtck, loads : 8 Net : r_cs2, loads : 8 Net : n822, loads : 8 Net : n816, loads : 8 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk5 [get_nets CLK_IN0] | 200.000 MHz| 84.012 MHz| 14 * | | | create_clock -period 5.000000 -name | | | clk4 [get_nets CLK0_OUT] | -| -| 0 | | | create_clock -period 5.000000 -name | | | clk3 [get_nets CLK90_OUT] | -| -| 0 | | | create_clock -period 5.000000 -name | | | clk2 [get_nets CLK180_OUT] | -| -| 0 | | | create_clock -period 5.000000 -name | | | clk1 [get_nets CLK270_OUT] | 200.000 MHz| 84.012 MHz| 14 * | | | create_clock -period 5.000000 -name | | | clk0 [get_nets CLK] | 200.000 MHz| 28.198 MHz| 4 * | | | -------------------------------------------------------------------------------- 3 constraints not met. Peak Memory Usage: 44.266 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 6.266 secs --------------------------------------------------------------