Place & Route TRACE Report

Loading design for application trce from file machxo2_breakout_test_hdl_xo2.ncd.
Design name: tool_test
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-1200ZE
Package:     TQFP144
Performance: 1
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/1.4/ispfpga.
Package Status:                     Final          Version 1.33
Performance Hardware Data Status:   Final          Version 22.4
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond_1.4_Production (87)
Sat Feb 25 15:47:55 2012

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 1 -sphld m -o MachXO2_Breakout_test_hdl_xo2.twr MachXO2_Breakout_test_hdl_xo2.ncd MachXO2_Breakout_test_hdl_xo2.prf 
Design file:     machxo2_breakout_test_hdl_xo2.ncd
Preference file: machxo2_breakout_test_hdl_xo2.prf
Device,speed:    LCMXO2-1200ZE,1
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "CLK" 2.080000 MHz (0 errors)
  • 843 items scored, 0 timing errors detected. Report: 31.636MHz is the maximum frequency for this preference.
  • FREQUENCY NET "CLK_IN0" 12.000000 MHz (0 errors)
  • 325 items scored, 0 timing errors detected. Report: 105.652MHz is the maximum frequency for this preference.
  • FREQUENCY NET "CLK0_OUT" 12.000000 MHz (0 errors)
  • 325 items scored, 0 timing errors detected. Report: 105.652MHz is the maximum frequency for this preference.
  • FREQUENCY NET "CLK90_OUT" 12.000000 MHz (0 errors)
  • 325 items scored, 0 timing errors detected. Report: 105.652MHz is the maximum frequency for this preference.
  • FREQUENCY NET "CLK180_OUT" 12.000000 MHz (0 errors)
  • 325 items scored, 0 timing errors detected. Report: 105.652MHz is the maximum frequency for this preference.
  • FREQUENCY NET "CLK270_OUT" 12.000000 MHz (0 errors)
  • 325 items scored, 0 timing errors detected. Report: 105.652MHz is the maximum frequency for this preference.
  • FREQUENCY PORT "EXTOSC" 24.000000 MHz (0 errors)
  • 0 items scored, 0 timing errors detected. Report: 150.150MHz is the maximum frequency for this preference.
  • PERIOD PORT "TOP_TCK" 0.100000 nS (1 errors)
  • 0 items scored, 1 timing error detected. WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "CLK" 2.080000 MHz ; 843 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 224.579ns (weighted slack = 449.158ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_jtck_50 (from CLK +) Destination: FF Data in ISP/r_sstpr_hi_114 (to CLK -) Delay: 15.186ns (18.4% logic, 81.6% route), 3 logic levels. Constraint Details: 15.186ns physical path delay SLICE_124 to ISP/SLICE_105 meets 240.384ns delay constraint less 0.000ns skew and 0.619ns CE_SET requirement (totaling 239.765ns) by 224.579ns Physical Path Details: Data path SLICE_124 to ISP/SLICE_105: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C10C.CLK to R4C10C.Q0 SLICE_124 (from CLK) ROUTE 9 1.581 R4C10C.Q0 to R4C10B.D1 r_jtck CTOF_DEL --- 0.923 R4C10B.D1 to R4C10B.F1 SLICE_112 ROUTE 9 5.167 R4C10B.F1 to R5C8A.B1 n1582 CTOF_DEL --- 0.923 R5C8A.B1 to R5C8A.F1 ISP/SLICE_101 ROUTE 5 5.637 R5C8A.F1 to R5C8D.CE ISP/n1574 (to CLK) -------- 15.186 (18.4% logic, 81.6% route), 3 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_124: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R4C10C.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to ISP/SLICE_105: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R5C8D.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 224.579ns (weighted slack = 449.158ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_jtck_50 (from CLK +) Destination: FF Data in ISP/r_store_113 (to CLK -) Delay: 15.186ns (18.4% logic, 81.6% route), 3 logic levels. Constraint Details: 15.186ns physical path delay SLICE_124 to ISP/SLICE_107 meets 240.384ns delay constraint less 0.000ns skew and 0.619ns CE_SET requirement (totaling 239.765ns) by 224.579ns Physical Path Details: Data path SLICE_124 to ISP/SLICE_107: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C10C.CLK to R4C10C.Q0 SLICE_124 (from CLK) ROUTE 9 1.581 R4C10C.Q0 to R4C10B.D1 r_jtck CTOF_DEL --- 0.923 R4C10B.D1 to R4C10B.F1 SLICE_112 ROUTE 9 5.167 R4C10B.F1 to R5C8A.B1 n1582 CTOF_DEL --- 0.923 R5C8A.B1 to R5C8A.F1 ISP/SLICE_101 ROUTE 5 5.637 R5C8A.F1 to R5C8B.CE ISP/n1574 (to CLK) -------- 15.186 (18.4% logic, 81.6% route), 3 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_124: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R4C10C.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to ISP/SLICE_107: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R5C8B.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 224.579ns (weighted slack = 449.158ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_jtck_50 (from CLK +) Destination: FF Data in ISP/r_sstpr_lo_115 (to CLK -) Delay: 15.186ns (18.4% logic, 81.6% route), 3 logic levels. Constraint Details: 15.186ns physical path delay SLICE_124 to ISP/SLICE_130 meets 240.384ns delay constraint less 0.000ns skew and 0.619ns CE_SET requirement (totaling 239.765ns) by 224.579ns Physical Path Details: Data path SLICE_124 to ISP/SLICE_130: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C10C.CLK to R4C10C.Q0 SLICE_124 (from CLK) ROUTE 9 1.581 R4C10C.Q0 to R4C10B.D1 r_jtck CTOF_DEL --- 0.923 R4C10B.D1 to R4C10B.F1 SLICE_112 ROUTE 9 5.167 R4C10B.F1 to R5C8A.B1 n1582 CTOF_DEL --- 0.923 R5C8A.B1 to R5C8A.F1 ISP/SLICE_101 ROUTE 5 5.637 R5C8A.F1 to R5C8C.CE ISP/n1574 (to CLK) -------- 15.186 (18.4% logic, 81.6% route), 3 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_124: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R4C10C.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to ISP/SLICE_130: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R5C8C.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 225.964ns (weighted slack = 451.928ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_pr_120__i11 (from CLK -) Destination: SP8KC Port ISP/mem0(ASIC) (to CLK +) Delay: 14.368ns (19.5% logic, 80.5% route), 3 logic levels. Constraint Details: 14.368ns physical path delay ISP/SLICE_92 to ISP/mem0 meets 240.384ns delay constraint less -0.274ns skew and 0.326ns WE_SET requirement (totaling 240.332ns) by 225.964ns Physical Path Details: Data path ISP/SLICE_92 to ISP/mem0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R7C9A.CLK to R7C9A.Q1 ISP/SLICE_92 (from CLK) ROUTE 2 3.486 R7C9A.Q1 to R4C10A.B1 ISP/ISP_ADDR_11 CTOF_DEL --- 0.923 R4C10A.B1 to R4C10A.F1 SLICE_127 ROUTE 1 2.301 R4C10A.F1 to R5C10D.B1 ISP/n1546 CTOF_DEL --- 0.923 R5C10D.B1 to R5C10D.F1 SLICE_132 ROUTE 1 5.780 R5C10D.F1 to EBR_R6C7.WE ISP/n1534 (to CLK) -------- 14.368 (19.5% logic, 80.5% route), 3 logic levels. Clock Skew Details: Source Clock Path osc_internal to ISP/SLICE_92: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R7C9A.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to ISP/mem0: Name Fanout Delay (ns) Site Resource ROUTE 55 8.152 OSC.OSC to EBR_R6C7.CLK CLK -------- 8.152 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 226.044ns (weighted slack = 452.088ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_pr_120__i15 (from CLK -) Destination: SP8KC Port ISP/mem0(ASIC) (to CLK +) Delay: 14.288ns (19.6% logic, 80.4% route), 3 logic levels. Constraint Details: 14.288ns physical path delay ISP/SLICE_94 to ISP/mem0 meets 240.384ns delay constraint less -0.274ns skew and 0.326ns WE_SET requirement (totaling 240.332ns) by 226.044ns Physical Path Details: Data path ISP/SLICE_94 to ISP/mem0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R7C9C.CLK to R7C9C.Q1 ISP/SLICE_94 (from CLK) ROUTE 2 3.406 R7C9C.Q1 to R4C10A.A1 ISP/ISP_ADDR_15 CTOF_DEL --- 0.923 R4C10A.A1 to R4C10A.F1 SLICE_127 ROUTE 1 2.301 R4C10A.F1 to R5C10D.B1 ISP/n1546 CTOF_DEL --- 0.923 R5C10D.B1 to R5C10D.F1 SLICE_132 ROUTE 1 5.780 R5C10D.F1 to EBR_R6C7.WE ISP/n1534 (to CLK) -------- 14.288 (19.6% logic, 80.4% route), 3 logic levels. Clock Skew Details: Source Clock Path osc_internal to ISP/SLICE_94: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R7C9C.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to ISP/mem0: Name Fanout Delay (ns) Site Resource ROUTE 55 8.152 OSC.OSC to EBR_R6C7.CLK CLK -------- 8.152 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 226.136ns (weighted slack = 452.272ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_pr_120__i13 (from CLK -) Destination: SP8KC Port ISP/mem0(ASIC) (to CLK +) Delay: 14.196ns (19.7% logic, 80.3% route), 3 logic levels. Constraint Details: 14.196ns physical path delay ISP/SLICE_93 to ISP/mem0 meets 240.384ns delay constraint less -0.274ns skew and 0.326ns WE_SET requirement (totaling 240.332ns) by 226.136ns Physical Path Details: Data path ISP/SLICE_93 to ISP/mem0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R7C9B.CLK to R7C9B.Q1 ISP/SLICE_93 (from CLK) ROUTE 2 4.613 R7C9B.Q1 to R5C10D.B0 ISP/ISP_ADDR_13 CTOF_DEL --- 0.923 R5C10D.B0 to R5C10D.F0 SLICE_132 ROUTE 1 1.002 R5C10D.F0 to R5C10D.C1 ISP/n10 CTOF_DEL --- 0.923 R5C10D.C1 to R5C10D.F1 SLICE_132 ROUTE 1 5.780 R5C10D.F1 to EBR_R6C7.WE ISP/n1534 (to CLK) -------- 14.196 (19.7% logic, 80.3% route), 3 logic levels. Clock Skew Details: Source Clock Path osc_internal to ISP/SLICE_93: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R7C9B.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to ISP/mem0: Name Fanout Delay (ns) Site Resource ROUTE 55 8.152 OSC.OSC to EBR_R6C7.CLK CLK -------- 8.152 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 226.522ns (weighted slack = 453.044ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_jtck_50 (from CLK +) Destination: FF Data in ISP/r_pr_120__i7 (to CLK -) FF ISP/r_pr_120__i6 Delay: 13.243ns (21.2% logic, 78.8% route), 3 logic levels. Constraint Details: 13.243ns physical path delay SLICE_124 to ISP/SLICE_90 meets 240.384ns delay constraint less 0.000ns skew and 0.619ns CE_SET requirement (totaling 239.765ns) by 226.522ns Physical Path Details: Data path SLICE_124 to ISP/SLICE_90: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C10C.CLK to R4C10C.Q0 SLICE_124 (from CLK) ROUTE 9 3.205 R4C10C.Q0 to R4C8B.A1 r_jtck CTOF_DEL --- 0.923 R4C8B.A1 to R4C8B.F1 SLICE_129 ROUTE 8 2.396 R4C8B.F1 to R4C8B.A0 ISP/n1578 CTOF_DEL --- 0.923 R4C8B.A0 to R4C8B.F0 SLICE_129 ROUTE 4 4.841 R4C8B.F0 to R7C8A.CE ISP/n822 (to CLK) -------- 13.243 (21.2% logic, 78.8% route), 3 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_124: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R4C10C.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to ISP/SLICE_90: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R7C8A.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 226.522ns (weighted slack = 453.044ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_jtck_50 (from CLK +) Destination: FF Data in ISP/r_pr_120__i1 (to CLK -) FF ISP/r_pr_120__i0 Delay: 13.243ns (21.2% logic, 78.8% route), 3 logic levels. Constraint Details: 13.243ns physical path delay SLICE_124 to ISP/SLICE_87 meets 240.384ns delay constraint less 0.000ns skew and 0.619ns CE_SET requirement (totaling 239.765ns) by 226.522ns Physical Path Details: Data path SLICE_124 to ISP/SLICE_87: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C10C.CLK to R4C10C.Q0 SLICE_124 (from CLK) ROUTE 9 3.205 R4C10C.Q0 to R4C8B.A1 r_jtck CTOF_DEL --- 0.923 R4C8B.A1 to R4C8B.F1 SLICE_129 ROUTE 8 2.396 R4C8B.F1 to R4C8B.A0 ISP/n1578 CTOF_DEL --- 0.923 R4C8B.A0 to R4C8B.F0 SLICE_129 ROUTE 4 4.841 R4C8B.F0 to R7C8B.CE ISP/n822 (to CLK) -------- 13.243 (21.2% logic, 78.8% route), 3 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_124: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R4C10C.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to ISP/SLICE_87: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R7C8B.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 226.522ns (weighted slack = 453.044ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_jtck_50 (from CLK +) Destination: FF Data in ISP/r_pr_120__i3 (to CLK -) FF ISP/r_pr_120__i2 Delay: 13.243ns (21.2% logic, 78.8% route), 3 logic levels. Constraint Details: 13.243ns physical path delay SLICE_124 to ISP/SLICE_88 meets 240.384ns delay constraint less 0.000ns skew and 0.619ns CE_SET requirement (totaling 239.765ns) by 226.522ns Physical Path Details: Data path SLICE_124 to ISP/SLICE_88: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C10C.CLK to R4C10C.Q0 SLICE_124 (from CLK) ROUTE 9 3.205 R4C10C.Q0 to R4C8B.A1 r_jtck CTOF_DEL --- 0.923 R4C8B.A1 to R4C8B.F1 SLICE_129 ROUTE 8 2.396 R4C8B.F1 to R4C8B.A0 ISP/n1578 CTOF_DEL --- 0.923 R4C8B.A0 to R4C8B.F0 SLICE_129 ROUTE 4 4.841 R4C8B.F0 to R7C8C.CE ISP/n822 (to CLK) -------- 13.243 (21.2% logic, 78.8% route), 3 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_124: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R4C10C.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to ISP/SLICE_88: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R7C8C.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 226.522ns (weighted slack = 453.044ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q ISP/r_jtck_50 (from CLK +) Destination: FF Data in ISP/r_pr_120__i5 (to CLK -) FF ISP/r_pr_120__i4 Delay: 13.243ns (21.2% logic, 78.8% route), 3 logic levels. Constraint Details: 13.243ns physical path delay SLICE_124 to ISP/SLICE_89 meets 240.384ns delay constraint less 0.000ns skew and 0.619ns CE_SET requirement (totaling 239.765ns) by 226.522ns Physical Path Details: Data path SLICE_124 to ISP/SLICE_89: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C10C.CLK to R4C10C.Q0 SLICE_124 (from CLK) ROUTE 9 3.205 R4C10C.Q0 to R4C8B.A1 r_jtck CTOF_DEL --- 0.923 R4C8B.A1 to R4C8B.F1 SLICE_129 ROUTE 8 2.396 R4C8B.F1 to R4C8B.A0 ISP/n1578 CTOF_DEL --- 0.923 R4C8B.A0 to R4C8B.F0 SLICE_129 ROUTE 4 4.841 R4C8B.F0 to R7C8D.CE ISP/n822 (to CLK) -------- 13.243 (21.2% logic, 78.8% route), 3 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_124: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R4C10C.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to ISP/SLICE_89: Name Fanout Delay (ns) Site Resource ROUTE 55 7.878 OSC.OSC to R7C8D.CLK CLK -------- 7.878 (0.0% logic, 100.0% route), 0 logic levels. Report: 31.636MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "CLK_IN0" 12.000000 MHz ; 325 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 73.868ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i0 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i24 (to CLK_IN0 +) Delay: 9.033ns (83.4% logic, 16.6% route), 14 logic levels. Constraint Details: 9.033ns physical path delay SLICE_50 to SLICE_38 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 73.868ns Physical Path Details: Data path SLICE_50 to SLICE_38: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C11A.CLK to R3C11A.Q1 SLICE_50 (from CLK_IN0) ROUTE 1 1.498 R3C11A.Q1 to R3C11A.A1 n27_adj_175 C1TOFCO_DE --- 1.795 R3C11A.A1 to R3C11A.FCO SLICE_50 ROUTE 1 0.000 R3C11A.FCO to R3C11B.FCI n1450 FCITOFCO_D --- 0.317 R3C11B.FCI to R3C11B.FCO SLICE_49 ROUTE 1 0.000 R3C11B.FCO to R3C11C.FCI n1451 FCITOFCO_D --- 0.317 R3C11C.FCI to R3C11C.FCO SLICE_48 ROUTE 1 0.000 R3C11C.FCO to R3C11D.FCI n1452 FCITOFCO_D --- 0.317 R3C11D.FCI to R3C11D.FCO SLICE_47 ROUTE 1 0.000 R3C11D.FCO to R3C12A.FCI n1453 FCITOFCO_D --- 0.317 R3C12A.FCI to R3C12A.FCO SLICE_46 ROUTE 1 0.000 R3C12A.FCO to R3C12B.FCI n1454 FCITOFCO_D --- 0.317 R3C12B.FCI to R3C12B.FCO SLICE_45 ROUTE 1 0.000 R3C12B.FCO to R3C12C.FCI n1455 FCITOFCO_D --- 0.317 R3C12C.FCI to R3C12C.FCO SLICE_44 ROUTE 1 0.000 R3C12C.FCO to R3C12D.FCI n1456 FCITOFCO_D --- 0.317 R3C12D.FCI to R3C12D.FCO SLICE_43 ROUTE 1 0.000 R3C12D.FCO to R3C13A.FCI n1457 FCITOFCO_D --- 0.317 R3C13A.FCI to R3C13A.FCO SLICE_42 ROUTE 1 0.000 R3C13A.FCO to R3C13B.FCI n1458 FCITOFCO_D --- 0.317 R3C13B.FCI to R3C13B.FCO SLICE_41 ROUTE 1 0.000 R3C13B.FCO to R3C13C.FCI n1459 FCITOFCO_D --- 0.317 R3C13C.FCI to R3C13C.FCO SLICE_40 ROUTE 1 0.000 R3C13C.FCO to R3C13D.FCI n1460 FCITOFCO_D --- 0.317 R3C13D.FCI to R3C13D.FCO SLICE_39 ROUTE 1 0.000 R3C13D.FCO to R3C14A.FCI n1461 FCITOF1_DE --- 1.298 R3C14A.FCI to R3C14A.F1 SLICE_38 ROUTE 1 0.000 R3C14A.F1 to R3C14A.DI1 n117_adj_176 (to CLK_IN0) -------- 9.033 (83.4% logic, 16.6% route), 14 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_50: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C11A.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_38: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C14A.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 73.916ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i1 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i24 (to CLK_IN0 +) Delay: 8.985ns (83.3% logic, 16.7% route), 13 logic levels. Constraint Details: 8.985ns physical path delay SLICE_49 to SLICE_38 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 73.916ns Physical Path Details: Data path SLICE_49 to SLICE_38: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C11B.CLK to R3C11B.Q0 SLICE_49 (from CLK_IN0) ROUTE 1 1.498 R3C11B.Q0 to R3C11B.A0 n26_adj_174 C0TOFCO_DE --- 2.064 R3C11B.A0 to R3C11B.FCO SLICE_49 ROUTE 1 0.000 R3C11B.FCO to R3C11C.FCI n1451 FCITOFCO_D --- 0.317 R3C11C.FCI to R3C11C.FCO SLICE_48 ROUTE 1 0.000 R3C11C.FCO to R3C11D.FCI n1452 FCITOFCO_D --- 0.317 R3C11D.FCI to R3C11D.FCO SLICE_47 ROUTE 1 0.000 R3C11D.FCO to R3C12A.FCI n1453 FCITOFCO_D --- 0.317 R3C12A.FCI to R3C12A.FCO SLICE_46 ROUTE 1 0.000 R3C12A.FCO to R3C12B.FCI n1454 FCITOFCO_D --- 0.317 R3C12B.FCI to R3C12B.FCO SLICE_45 ROUTE 1 0.000 R3C12B.FCO to R3C12C.FCI n1455 FCITOFCO_D --- 0.317 R3C12C.FCI to R3C12C.FCO SLICE_44 ROUTE 1 0.000 R3C12C.FCO to R3C12D.FCI n1456 FCITOFCO_D --- 0.317 R3C12D.FCI to R3C12D.FCO SLICE_43 ROUTE 1 0.000 R3C12D.FCO to R3C13A.FCI n1457 FCITOFCO_D --- 0.317 R3C13A.FCI to R3C13A.FCO SLICE_42 ROUTE 1 0.000 R3C13A.FCO to R3C13B.FCI n1458 FCITOFCO_D --- 0.317 R3C13B.FCI to R3C13B.FCO SLICE_41 ROUTE 1 0.000 R3C13B.FCO to R3C13C.FCI n1459 FCITOFCO_D --- 0.317 R3C13C.FCI to R3C13C.FCO SLICE_40 ROUTE 1 0.000 R3C13C.FCO to R3C13D.FCI n1460 FCITOFCO_D --- 0.317 R3C13D.FCI to R3C13D.FCO SLICE_39 ROUTE 1 0.000 R3C13D.FCO to R3C14A.FCI n1461 FCITOF1_DE --- 1.298 R3C14A.FCI to R3C14A.F1 SLICE_38 ROUTE 1 0.000 R3C14A.F1 to R3C14A.DI1 n117_adj_176 (to CLK_IN0) -------- 8.985 (83.3% logic, 16.7% route), 13 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_49: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C11B.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_38: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C14A.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 73.985ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i0 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i23 (to CLK_IN0 +) Delay: 8.916ns (83.2% logic, 16.8% route), 14 logic levels. Constraint Details: 8.916ns physical path delay SLICE_50 to SLICE_38 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 73.985ns Physical Path Details: Data path SLICE_50 to SLICE_38: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C11A.CLK to R3C11A.Q1 SLICE_50 (from CLK_IN0) ROUTE 1 1.498 R3C11A.Q1 to R3C11A.A1 n27_adj_175 C1TOFCO_DE --- 1.795 R3C11A.A1 to R3C11A.FCO SLICE_50 ROUTE 1 0.000 R3C11A.FCO to R3C11B.FCI n1450 FCITOFCO_D --- 0.317 R3C11B.FCI to R3C11B.FCO SLICE_49 ROUTE 1 0.000 R3C11B.FCO to R3C11C.FCI n1451 FCITOFCO_D --- 0.317 R3C11C.FCI to R3C11C.FCO SLICE_48 ROUTE 1 0.000 R3C11C.FCO to R3C11D.FCI n1452 FCITOFCO_D --- 0.317 R3C11D.FCI to R3C11D.FCO SLICE_47 ROUTE 1 0.000 R3C11D.FCO to R3C12A.FCI n1453 FCITOFCO_D --- 0.317 R3C12A.FCI to R3C12A.FCO SLICE_46 ROUTE 1 0.000 R3C12A.FCO to R3C12B.FCI n1454 FCITOFCO_D --- 0.317 R3C12B.FCI to R3C12B.FCO SLICE_45 ROUTE 1 0.000 R3C12B.FCO to R3C12C.FCI n1455 FCITOFCO_D --- 0.317 R3C12C.FCI to R3C12C.FCO SLICE_44 ROUTE 1 0.000 R3C12C.FCO to R3C12D.FCI n1456 FCITOFCO_D --- 0.317 R3C12D.FCI to R3C12D.FCO SLICE_43 ROUTE 1 0.000 R3C12D.FCO to R3C13A.FCI n1457 FCITOFCO_D --- 0.317 R3C13A.FCI to R3C13A.FCO SLICE_42 ROUTE 1 0.000 R3C13A.FCO to R3C13B.FCI n1458 FCITOFCO_D --- 0.317 R3C13B.FCI to R3C13B.FCO SLICE_41 ROUTE 1 0.000 R3C13B.FCO to R3C13C.FCI n1459 FCITOFCO_D --- 0.317 R3C13C.FCI to R3C13C.FCO SLICE_40 ROUTE 1 0.000 R3C13C.FCO to R3C13D.FCI n1460 FCITOFCO_D --- 0.317 R3C13D.FCI to R3C13D.FCO SLICE_39 ROUTE 1 0.000 R3C13D.FCO to R3C14A.FCI n1461 FCITOF0_DE --- 1.181 R3C14A.FCI to R3C14A.F0 SLICE_38 ROUTE 1 0.000 R3C14A.F0 to R3C14A.DI0 n118_adj_177 (to CLK_IN0) -------- 8.916 (83.2% logic, 16.8% route), 14 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_50: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C11A.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_38: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C14A.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.033ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i1 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i23 (to CLK_IN0 +) Delay: 8.868ns (83.1% logic, 16.9% route), 13 logic levels. Constraint Details: 8.868ns physical path delay SLICE_49 to SLICE_38 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.033ns Physical Path Details: Data path SLICE_49 to SLICE_38: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C11B.CLK to R3C11B.Q0 SLICE_49 (from CLK_IN0) ROUTE 1 1.498 R3C11B.Q0 to R3C11B.A0 n26_adj_174 C0TOFCO_DE --- 2.064 R3C11B.A0 to R3C11B.FCO SLICE_49 ROUTE 1 0.000 R3C11B.FCO to R3C11C.FCI n1451 FCITOFCO_D --- 0.317 R3C11C.FCI to R3C11C.FCO SLICE_48 ROUTE 1 0.000 R3C11C.FCO to R3C11D.FCI n1452 FCITOFCO_D --- 0.317 R3C11D.FCI to R3C11D.FCO SLICE_47 ROUTE 1 0.000 R3C11D.FCO to R3C12A.FCI n1453 FCITOFCO_D --- 0.317 R3C12A.FCI to R3C12A.FCO SLICE_46 ROUTE 1 0.000 R3C12A.FCO to R3C12B.FCI n1454 FCITOFCO_D --- 0.317 R3C12B.FCI to R3C12B.FCO SLICE_45 ROUTE 1 0.000 R3C12B.FCO to R3C12C.FCI n1455 FCITOFCO_D --- 0.317 R3C12C.FCI to R3C12C.FCO SLICE_44 ROUTE 1 0.000 R3C12C.FCO to R3C12D.FCI n1456 FCITOFCO_D --- 0.317 R3C12D.FCI to R3C12D.FCO SLICE_43 ROUTE 1 0.000 R3C12D.FCO to R3C13A.FCI n1457 FCITOFCO_D --- 0.317 R3C13A.FCI to R3C13A.FCO SLICE_42 ROUTE 1 0.000 R3C13A.FCO to R3C13B.FCI n1458 FCITOFCO_D --- 0.317 R3C13B.FCI to R3C13B.FCO SLICE_41 ROUTE 1 0.000 R3C13B.FCO to R3C13C.FCI n1459 FCITOFCO_D --- 0.317 R3C13C.FCI to R3C13C.FCO SLICE_40 ROUTE 1 0.000 R3C13C.FCO to R3C13D.FCI n1460 FCITOFCO_D --- 0.317 R3C13D.FCI to R3C13D.FCO SLICE_39 ROUTE 1 0.000 R3C13D.FCO to R3C14A.FCI n1461 FCITOF0_DE --- 1.181 R3C14A.FCI to R3C14A.F0 SLICE_38 ROUTE 1 0.000 R3C14A.F0 to R3C14A.DI0 n118_adj_177 (to CLK_IN0) -------- 8.868 (83.1% logic, 16.9% route), 13 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_49: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C11B.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_38: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C14A.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.185ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i2 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i24 (to CLK_IN0 +) Delay: 8.716ns (82.8% logic, 17.2% route), 13 logic levels. Constraint Details: 8.716ns physical path delay SLICE_49 to SLICE_38 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.185ns Physical Path Details: Data path SLICE_49 to SLICE_38: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C11B.CLK to R3C11B.Q1 SLICE_49 (from CLK_IN0) ROUTE 1 1.498 R3C11B.Q1 to R3C11B.A1 n25_adj_173 C1TOFCO_DE --- 1.795 R3C11B.A1 to R3C11B.FCO SLICE_49 ROUTE 1 0.000 R3C11B.FCO to R3C11C.FCI n1451 FCITOFCO_D --- 0.317 R3C11C.FCI to R3C11C.FCO SLICE_48 ROUTE 1 0.000 R3C11C.FCO to R3C11D.FCI n1452 FCITOFCO_D --- 0.317 R3C11D.FCI to R3C11D.FCO SLICE_47 ROUTE 1 0.000 R3C11D.FCO to R3C12A.FCI n1453 FCITOFCO_D --- 0.317 R3C12A.FCI to R3C12A.FCO SLICE_46 ROUTE 1 0.000 R3C12A.FCO to R3C12B.FCI n1454 FCITOFCO_D --- 0.317 R3C12B.FCI to R3C12B.FCO SLICE_45 ROUTE 1 0.000 R3C12B.FCO to R3C12C.FCI n1455 FCITOFCO_D --- 0.317 R3C12C.FCI to R3C12C.FCO SLICE_44 ROUTE 1 0.000 R3C12C.FCO to R3C12D.FCI n1456 FCITOFCO_D --- 0.317 R3C12D.FCI to R3C12D.FCO SLICE_43 ROUTE 1 0.000 R3C12D.FCO to R3C13A.FCI n1457 FCITOFCO_D --- 0.317 R3C13A.FCI to R3C13A.FCO SLICE_42 ROUTE 1 0.000 R3C13A.FCO to R3C13B.FCI n1458 FCITOFCO_D --- 0.317 R3C13B.FCI to R3C13B.FCO SLICE_41 ROUTE 1 0.000 R3C13B.FCO to R3C13C.FCI n1459 FCITOFCO_D --- 0.317 R3C13C.FCI to R3C13C.FCO SLICE_40 ROUTE 1 0.000 R3C13C.FCO to R3C13D.FCI n1460 FCITOFCO_D --- 0.317 R3C13D.FCI to R3C13D.FCO SLICE_39 ROUTE 1 0.000 R3C13D.FCO to R3C14A.FCI n1461 FCITOF1_DE --- 1.298 R3C14A.FCI to R3C14A.F1 SLICE_38 ROUTE 1 0.000 R3C14A.F1 to R3C14A.DI1 n117_adj_176 (to CLK_IN0) -------- 8.716 (82.8% logic, 17.2% route), 13 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_49: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C11B.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_38: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C14A.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.185ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i0 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i22 (to CLK_IN0 +) Delay: 8.716ns (82.8% logic, 17.2% route), 13 logic levels. Constraint Details: 8.716ns physical path delay SLICE_50 to SLICE_39 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.185ns Physical Path Details: Data path SLICE_50 to SLICE_39: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C11A.CLK to R3C11A.Q1 SLICE_50 (from CLK_IN0) ROUTE 1 1.498 R3C11A.Q1 to R3C11A.A1 n27_adj_175 C1TOFCO_DE --- 1.795 R3C11A.A1 to R3C11A.FCO SLICE_50 ROUTE 1 0.000 R3C11A.FCO to R3C11B.FCI n1450 FCITOFCO_D --- 0.317 R3C11B.FCI to R3C11B.FCO SLICE_49 ROUTE 1 0.000 R3C11B.FCO to R3C11C.FCI n1451 FCITOFCO_D --- 0.317 R3C11C.FCI to R3C11C.FCO SLICE_48 ROUTE 1 0.000 R3C11C.FCO to R3C11D.FCI n1452 FCITOFCO_D --- 0.317 R3C11D.FCI to R3C11D.FCO SLICE_47 ROUTE 1 0.000 R3C11D.FCO to R3C12A.FCI n1453 FCITOFCO_D --- 0.317 R3C12A.FCI to R3C12A.FCO SLICE_46 ROUTE 1 0.000 R3C12A.FCO to R3C12B.FCI n1454 FCITOFCO_D --- 0.317 R3C12B.FCI to R3C12B.FCO SLICE_45 ROUTE 1 0.000 R3C12B.FCO to R3C12C.FCI n1455 FCITOFCO_D --- 0.317 R3C12C.FCI to R3C12C.FCO SLICE_44 ROUTE 1 0.000 R3C12C.FCO to R3C12D.FCI n1456 FCITOFCO_D --- 0.317 R3C12D.FCI to R3C12D.FCO SLICE_43 ROUTE 1 0.000 R3C12D.FCO to R3C13A.FCI n1457 FCITOFCO_D --- 0.317 R3C13A.FCI to R3C13A.FCO SLICE_42 ROUTE 1 0.000 R3C13A.FCO to R3C13B.FCI n1458 FCITOFCO_D --- 0.317 R3C13B.FCI to R3C13B.FCO SLICE_41 ROUTE 1 0.000 R3C13B.FCO to R3C13C.FCI n1459 FCITOFCO_D --- 0.317 R3C13C.FCI to R3C13C.FCO SLICE_40 ROUTE 1 0.000 R3C13C.FCO to R3C13D.FCI n1460 FCITOF1_DE --- 1.298 R3C13D.FCI to R3C13D.F1 SLICE_39 ROUTE 1 0.000 R3C13D.F1 to R3C13D.DI1 n119_adj_178 (to CLK_IN0) -------- 8.716 (82.8% logic, 17.2% route), 13 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_50: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C11A.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C13D.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.233ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i3 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i24 (to CLK_IN0 +) Delay: 8.668ns (82.7% logic, 17.3% route), 12 logic levels. Constraint Details: 8.668ns physical path delay SLICE_48 to SLICE_38 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.233ns Physical Path Details: Data path SLICE_48 to SLICE_38: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C11C.CLK to R3C11C.Q0 SLICE_48 (from CLK_IN0) ROUTE 1 1.498 R3C11C.Q0 to R3C11C.A0 n24_adj_172 C0TOFCO_DE --- 2.064 R3C11C.A0 to R3C11C.FCO SLICE_48 ROUTE 1 0.000 R3C11C.FCO to R3C11D.FCI n1452 FCITOFCO_D --- 0.317 R3C11D.FCI to R3C11D.FCO SLICE_47 ROUTE 1 0.000 R3C11D.FCO to R3C12A.FCI n1453 FCITOFCO_D --- 0.317 R3C12A.FCI to R3C12A.FCO SLICE_46 ROUTE 1 0.000 R3C12A.FCO to R3C12B.FCI n1454 FCITOFCO_D --- 0.317 R3C12B.FCI to R3C12B.FCO SLICE_45 ROUTE 1 0.000 R3C12B.FCO to R3C12C.FCI n1455 FCITOFCO_D --- 0.317 R3C12C.FCI to R3C12C.FCO SLICE_44 ROUTE 1 0.000 R3C12C.FCO to R3C12D.FCI n1456 FCITOFCO_D --- 0.317 R3C12D.FCI to R3C12D.FCO SLICE_43 ROUTE 1 0.000 R3C12D.FCO to R3C13A.FCI n1457 FCITOFCO_D --- 0.317 R3C13A.FCI to R3C13A.FCO SLICE_42 ROUTE 1 0.000 R3C13A.FCO to R3C13B.FCI n1458 FCITOFCO_D --- 0.317 R3C13B.FCI to R3C13B.FCO SLICE_41 ROUTE 1 0.000 R3C13B.FCO to R3C13C.FCI n1459 FCITOFCO_D --- 0.317 R3C13C.FCI to R3C13C.FCO SLICE_40 ROUTE 1 0.000 R3C13C.FCO to R3C13D.FCI n1460 FCITOFCO_D --- 0.317 R3C13D.FCI to R3C13D.FCO SLICE_39 ROUTE 1 0.000 R3C13D.FCO to R3C14A.FCI n1461 FCITOF1_DE --- 1.298 R3C14A.FCI to R3C14A.F1 SLICE_38 ROUTE 1 0.000 R3C14A.F1 to R3C14A.DI1 n117_adj_176 (to CLK_IN0) -------- 8.668 (82.7% logic, 17.3% route), 12 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_48: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C11C.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_38: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C14A.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.233ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i1 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i22 (to CLK_IN0 +) Delay: 8.668ns (82.7% logic, 17.3% route), 12 logic levels. Constraint Details: 8.668ns physical path delay SLICE_49 to SLICE_39 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.233ns Physical Path Details: Data path SLICE_49 to SLICE_39: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C11B.CLK to R3C11B.Q0 SLICE_49 (from CLK_IN0) ROUTE 1 1.498 R3C11B.Q0 to R3C11B.A0 n26_adj_174 C0TOFCO_DE --- 2.064 R3C11B.A0 to R3C11B.FCO SLICE_49 ROUTE 1 0.000 R3C11B.FCO to R3C11C.FCI n1451 FCITOFCO_D --- 0.317 R3C11C.FCI to R3C11C.FCO SLICE_48 ROUTE 1 0.000 R3C11C.FCO to R3C11D.FCI n1452 FCITOFCO_D --- 0.317 R3C11D.FCI to R3C11D.FCO SLICE_47 ROUTE 1 0.000 R3C11D.FCO to R3C12A.FCI n1453 FCITOFCO_D --- 0.317 R3C12A.FCI to R3C12A.FCO SLICE_46 ROUTE 1 0.000 R3C12A.FCO to R3C12B.FCI n1454 FCITOFCO_D --- 0.317 R3C12B.FCI to R3C12B.FCO SLICE_45 ROUTE 1 0.000 R3C12B.FCO to R3C12C.FCI n1455 FCITOFCO_D --- 0.317 R3C12C.FCI to R3C12C.FCO SLICE_44 ROUTE 1 0.000 R3C12C.FCO to R3C12D.FCI n1456 FCITOFCO_D --- 0.317 R3C12D.FCI to R3C12D.FCO SLICE_43 ROUTE 1 0.000 R3C12D.FCO to R3C13A.FCI n1457 FCITOFCO_D --- 0.317 R3C13A.FCI to R3C13A.FCO SLICE_42 ROUTE 1 0.000 R3C13A.FCO to R3C13B.FCI n1458 FCITOFCO_D --- 0.317 R3C13B.FCI to R3C13B.FCO SLICE_41 ROUTE 1 0.000 R3C13B.FCO to R3C13C.FCI n1459 FCITOFCO_D --- 0.317 R3C13C.FCI to R3C13C.FCO SLICE_40 ROUTE 1 0.000 R3C13C.FCO to R3C13D.FCI n1460 FCITOF1_DE --- 1.298 R3C13D.FCI to R3C13D.F1 SLICE_39 ROUTE 1 0.000 R3C13D.F1 to R3C13D.DI1 n119_adj_178 (to CLK_IN0) -------- 8.668 (82.7% logic, 17.3% route), 12 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_49: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C11B.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C13D.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.302ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i2 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i23 (to CLK_IN0 +) Delay: 8.599ns (82.6% logic, 17.4% route), 13 logic levels. Constraint Details: 8.599ns physical path delay SLICE_49 to SLICE_38 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.302ns Physical Path Details: Data path SLICE_49 to SLICE_38: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C11B.CLK to R3C11B.Q1 SLICE_49 (from CLK_IN0) ROUTE 1 1.498 R3C11B.Q1 to R3C11B.A1 n25_adj_173 C1TOFCO_DE --- 1.795 R3C11B.A1 to R3C11B.FCO SLICE_49 ROUTE 1 0.000 R3C11B.FCO to R3C11C.FCI n1451 FCITOFCO_D --- 0.317 R3C11C.FCI to R3C11C.FCO SLICE_48 ROUTE 1 0.000 R3C11C.FCO to R3C11D.FCI n1452 FCITOFCO_D --- 0.317 R3C11D.FCI to R3C11D.FCO SLICE_47 ROUTE 1 0.000 R3C11D.FCO to R3C12A.FCI n1453 FCITOFCO_D --- 0.317 R3C12A.FCI to R3C12A.FCO SLICE_46 ROUTE 1 0.000 R3C12A.FCO to R3C12B.FCI n1454 FCITOFCO_D --- 0.317 R3C12B.FCI to R3C12B.FCO SLICE_45 ROUTE 1 0.000 R3C12B.FCO to R3C12C.FCI n1455 FCITOFCO_D --- 0.317 R3C12C.FCI to R3C12C.FCO SLICE_44 ROUTE 1 0.000 R3C12C.FCO to R3C12D.FCI n1456 FCITOFCO_D --- 0.317 R3C12D.FCI to R3C12D.FCO SLICE_43 ROUTE 1 0.000 R3C12D.FCO to R3C13A.FCI n1457 FCITOFCO_D --- 0.317 R3C13A.FCI to R3C13A.FCO SLICE_42 ROUTE 1 0.000 R3C13A.FCO to R3C13B.FCI n1458 FCITOFCO_D --- 0.317 R3C13B.FCI to R3C13B.FCO SLICE_41 ROUTE 1 0.000 R3C13B.FCO to R3C13C.FCI n1459 FCITOFCO_D --- 0.317 R3C13C.FCI to R3C13C.FCO SLICE_40 ROUTE 1 0.000 R3C13C.FCO to R3C13D.FCI n1460 FCITOFCO_D --- 0.317 R3C13D.FCI to R3C13D.FCO SLICE_39 ROUTE 1 0.000 R3C13D.FCO to R3C14A.FCI n1461 FCITOF0_DE --- 1.181 R3C14A.FCI to R3C14A.F0 SLICE_38 ROUTE 1 0.000 R3C14A.F0 to R3C14A.DI0 n118_adj_177 (to CLK_IN0) -------- 8.599 (82.6% logic, 17.4% route), 13 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_49: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C11B.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_38: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C14A.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.302ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i0 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i21 (to CLK_IN0 +) Delay: 8.599ns (82.6% logic, 17.4% route), 13 logic levels. Constraint Details: 8.599ns physical path delay SLICE_50 to SLICE_39 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.302ns Physical Path Details: Data path SLICE_50 to SLICE_39: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C11A.CLK to R3C11A.Q1 SLICE_50 (from CLK_IN0) ROUTE 1 1.498 R3C11A.Q1 to R3C11A.A1 n27_adj_175 C1TOFCO_DE --- 1.795 R3C11A.A1 to R3C11A.FCO SLICE_50 ROUTE 1 0.000 R3C11A.FCO to R3C11B.FCI n1450 FCITOFCO_D --- 0.317 R3C11B.FCI to R3C11B.FCO SLICE_49 ROUTE 1 0.000 R3C11B.FCO to R3C11C.FCI n1451 FCITOFCO_D --- 0.317 R3C11C.FCI to R3C11C.FCO SLICE_48 ROUTE 1 0.000 R3C11C.FCO to R3C11D.FCI n1452 FCITOFCO_D --- 0.317 R3C11D.FCI to R3C11D.FCO SLICE_47 ROUTE 1 0.000 R3C11D.FCO to R3C12A.FCI n1453 FCITOFCO_D --- 0.317 R3C12A.FCI to R3C12A.FCO SLICE_46 ROUTE 1 0.000 R3C12A.FCO to R3C12B.FCI n1454 FCITOFCO_D --- 0.317 R3C12B.FCI to R3C12B.FCO SLICE_45 ROUTE 1 0.000 R3C12B.FCO to R3C12C.FCI n1455 FCITOFCO_D --- 0.317 R3C12C.FCI to R3C12C.FCO SLICE_44 ROUTE 1 0.000 R3C12C.FCO to R3C12D.FCI n1456 FCITOFCO_D --- 0.317 R3C12D.FCI to R3C12D.FCO SLICE_43 ROUTE 1 0.000 R3C12D.FCO to R3C13A.FCI n1457 FCITOFCO_D --- 0.317 R3C13A.FCI to R3C13A.FCO SLICE_42 ROUTE 1 0.000 R3C13A.FCO to R3C13B.FCI n1458 FCITOFCO_D --- 0.317 R3C13B.FCI to R3C13B.FCO SLICE_41 ROUTE 1 0.000 R3C13B.FCO to R3C13C.FCI n1459 FCITOFCO_D --- 0.317 R3C13C.FCI to R3C13C.FCO SLICE_40 ROUTE 1 0.000 R3C13C.FCO to R3C13D.FCI n1460 FCITOF0_DE --- 1.181 R3C13D.FCI to R3C13D.F0 SLICE_39 ROUTE 1 0.000 R3C13D.F0 to R3C13D.DI0 n120_adj_179 (to CLK_IN0) -------- 8.599 (82.6% logic, 17.4% route), 13 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_50: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C11A.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 14 2.224 DCM6.DCMOUT to R3C13D.CLK CLK_IN0 -------- 2.224 (0.0% logic, 100.0% route), 0 logic levels. Report: 105.652MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; 325 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 73.868ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i0 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i24 (to CLK0_OUT +) Delay: 9.033ns (83.4% logic, 16.6% route), 14 logic levels. Constraint Details: 9.033ns physical path delay SLICE_12 to SLICE_51 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 73.868ns Physical Path Details: Data path SLICE_12 to SLICE_51: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C11A.CLK to R4C11A.Q1 SLICE_12 (from CLK0_OUT) ROUTE 1 1.498 R4C11A.Q1 to R4C11A.A1 n27_adj_126 C1TOFCO_DE --- 1.795 R4C11A.A1 to R4C11A.FCO SLICE_12 ROUTE 1 0.000 R4C11A.FCO to R4C11B.FCI n1436 FCITOFCO_D --- 0.317 R4C11B.FCI to R4C11B.FCO SLICE_7 ROUTE 1 0.000 R4C11B.FCO to R4C11C.FCI n1437 FCITOFCO_D --- 0.317 R4C11C.FCI to R4C11C.FCO SLICE_6 ROUTE 1 0.000 R4C11C.FCO to R4C11D.FCI n1438 FCITOFCO_D --- 0.317 R4C11D.FCI to R4C11D.FCO SLICE_3 ROUTE 1 0.000 R4C11D.FCO to R4C12A.FCI n1439 FCITOFCO_D --- 0.317 R4C12A.FCI to R4C12A.FCO SLICE_2 ROUTE 1 0.000 R4C12A.FCO to R4C12B.FCI n1440 FCITOFCO_D --- 0.317 R4C12B.FCI to R4C12B.FCO SLICE_1 ROUTE 1 0.000 R4C12B.FCO to R4C12C.FCI n1441 FCITOFCO_D --- 0.317 R4C12C.FCI to R4C12C.FCO SLICE_59 ROUTE 1 0.000 R4C12C.FCO to R4C12D.FCI n1442 FCITOFCO_D --- 0.317 R4C12D.FCI to R4C12D.FCO SLICE_57 ROUTE 1 0.000 R4C12D.FCO to R4C13A.FCI n1443 FCITOFCO_D --- 0.317 R4C13A.FCI to R4C13A.FCO SLICE_55 ROUTE 1 0.000 R4C13A.FCO to R4C13B.FCI n1444 FCITOFCO_D --- 0.317 R4C13B.FCI to R4C13B.FCO SLICE_54 ROUTE 1 0.000 R4C13B.FCO to R4C13C.FCI n1445 FCITOFCO_D --- 0.317 R4C13C.FCI to R4C13C.FCO SLICE_53 ROUTE 1 0.000 R4C13C.FCO to R4C13D.FCI n1446 FCITOFCO_D --- 0.317 R4C13D.FCI to R4C13D.FCO SLICE_52 ROUTE 1 0.000 R4C13D.FCO to R4C14A.FCI n1447 FCITOF1_DE --- 1.298 R4C14A.FCI to R4C14A.F1 SLICE_51 ROUTE 1 0.000 R4C14A.F1 to R4C14A.DI1 n117_adj_127 (to CLK0_OUT) -------- 9.033 (83.4% logic, 16.6% route), 14 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C11A.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_51: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C14A.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 73.916ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i1 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i24 (to CLK0_OUT +) Delay: 8.985ns (83.3% logic, 16.7% route), 13 logic levels. Constraint Details: 8.985ns physical path delay SLICE_7 to SLICE_51 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 73.916ns Physical Path Details: Data path SLICE_7 to SLICE_51: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C11B.CLK to R4C11B.Q0 SLICE_7 (from CLK0_OUT) ROUTE 1 1.498 R4C11B.Q0 to R4C11B.A0 n26_adj_125 C0TOFCO_DE --- 2.064 R4C11B.A0 to R4C11B.FCO SLICE_7 ROUTE 1 0.000 R4C11B.FCO to R4C11C.FCI n1437 FCITOFCO_D --- 0.317 R4C11C.FCI to R4C11C.FCO SLICE_6 ROUTE 1 0.000 R4C11C.FCO to R4C11D.FCI n1438 FCITOFCO_D --- 0.317 R4C11D.FCI to R4C11D.FCO SLICE_3 ROUTE 1 0.000 R4C11D.FCO to R4C12A.FCI n1439 FCITOFCO_D --- 0.317 R4C12A.FCI to R4C12A.FCO SLICE_2 ROUTE 1 0.000 R4C12A.FCO to R4C12B.FCI n1440 FCITOFCO_D --- 0.317 R4C12B.FCI to R4C12B.FCO SLICE_1 ROUTE 1 0.000 R4C12B.FCO to R4C12C.FCI n1441 FCITOFCO_D --- 0.317 R4C12C.FCI to R4C12C.FCO SLICE_59 ROUTE 1 0.000 R4C12C.FCO to R4C12D.FCI n1442 FCITOFCO_D --- 0.317 R4C12D.FCI to R4C12D.FCO SLICE_57 ROUTE 1 0.000 R4C12D.FCO to R4C13A.FCI n1443 FCITOFCO_D --- 0.317 R4C13A.FCI to R4C13A.FCO SLICE_55 ROUTE 1 0.000 R4C13A.FCO to R4C13B.FCI n1444 FCITOFCO_D --- 0.317 R4C13B.FCI to R4C13B.FCO SLICE_54 ROUTE 1 0.000 R4C13B.FCO to R4C13C.FCI n1445 FCITOFCO_D --- 0.317 R4C13C.FCI to R4C13C.FCO SLICE_53 ROUTE 1 0.000 R4C13C.FCO to R4C13D.FCI n1446 FCITOFCO_D --- 0.317 R4C13D.FCI to R4C13D.FCO SLICE_52 ROUTE 1 0.000 R4C13D.FCO to R4C14A.FCI n1447 FCITOF1_DE --- 1.298 R4C14A.FCI to R4C14A.F1 SLICE_51 ROUTE 1 0.000 R4C14A.F1 to R4C14A.DI1 n117_adj_127 (to CLK0_OUT) -------- 8.985 (83.3% logic, 16.7% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C11B.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_51: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C14A.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 73.985ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i0 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i23 (to CLK0_OUT +) Delay: 8.916ns (83.2% logic, 16.8% route), 14 logic levels. Constraint Details: 8.916ns physical path delay SLICE_12 to SLICE_51 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 73.985ns Physical Path Details: Data path SLICE_12 to SLICE_51: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C11A.CLK to R4C11A.Q1 SLICE_12 (from CLK0_OUT) ROUTE 1 1.498 R4C11A.Q1 to R4C11A.A1 n27_adj_126 C1TOFCO_DE --- 1.795 R4C11A.A1 to R4C11A.FCO SLICE_12 ROUTE 1 0.000 R4C11A.FCO to R4C11B.FCI n1436 FCITOFCO_D --- 0.317 R4C11B.FCI to R4C11B.FCO SLICE_7 ROUTE 1 0.000 R4C11B.FCO to R4C11C.FCI n1437 FCITOFCO_D --- 0.317 R4C11C.FCI to R4C11C.FCO SLICE_6 ROUTE 1 0.000 R4C11C.FCO to R4C11D.FCI n1438 FCITOFCO_D --- 0.317 R4C11D.FCI to R4C11D.FCO SLICE_3 ROUTE 1 0.000 R4C11D.FCO to R4C12A.FCI n1439 FCITOFCO_D --- 0.317 R4C12A.FCI to R4C12A.FCO SLICE_2 ROUTE 1 0.000 R4C12A.FCO to R4C12B.FCI n1440 FCITOFCO_D --- 0.317 R4C12B.FCI to R4C12B.FCO SLICE_1 ROUTE 1 0.000 R4C12B.FCO to R4C12C.FCI n1441 FCITOFCO_D --- 0.317 R4C12C.FCI to R4C12C.FCO SLICE_59 ROUTE 1 0.000 R4C12C.FCO to R4C12D.FCI n1442 FCITOFCO_D --- 0.317 R4C12D.FCI to R4C12D.FCO SLICE_57 ROUTE 1 0.000 R4C12D.FCO to R4C13A.FCI n1443 FCITOFCO_D --- 0.317 R4C13A.FCI to R4C13A.FCO SLICE_55 ROUTE 1 0.000 R4C13A.FCO to R4C13B.FCI n1444 FCITOFCO_D --- 0.317 R4C13B.FCI to R4C13B.FCO SLICE_54 ROUTE 1 0.000 R4C13B.FCO to R4C13C.FCI n1445 FCITOFCO_D --- 0.317 R4C13C.FCI to R4C13C.FCO SLICE_53 ROUTE 1 0.000 R4C13C.FCO to R4C13D.FCI n1446 FCITOFCO_D --- 0.317 R4C13D.FCI to R4C13D.FCO SLICE_52 ROUTE 1 0.000 R4C13D.FCO to R4C14A.FCI n1447 FCITOF0_DE --- 1.181 R4C14A.FCI to R4C14A.F0 SLICE_51 ROUTE 1 0.000 R4C14A.F0 to R4C14A.DI0 n118_adj_128 (to CLK0_OUT) -------- 8.916 (83.2% logic, 16.8% route), 14 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C11A.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_51: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C14A.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.033ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i1 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i23 (to CLK0_OUT +) Delay: 8.868ns (83.1% logic, 16.9% route), 13 logic levels. Constraint Details: 8.868ns physical path delay SLICE_7 to SLICE_51 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.033ns Physical Path Details: Data path SLICE_7 to SLICE_51: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C11B.CLK to R4C11B.Q0 SLICE_7 (from CLK0_OUT) ROUTE 1 1.498 R4C11B.Q0 to R4C11B.A0 n26_adj_125 C0TOFCO_DE --- 2.064 R4C11B.A0 to R4C11B.FCO SLICE_7 ROUTE 1 0.000 R4C11B.FCO to R4C11C.FCI n1437 FCITOFCO_D --- 0.317 R4C11C.FCI to R4C11C.FCO SLICE_6 ROUTE 1 0.000 R4C11C.FCO to R4C11D.FCI n1438 FCITOFCO_D --- 0.317 R4C11D.FCI to R4C11D.FCO SLICE_3 ROUTE 1 0.000 R4C11D.FCO to R4C12A.FCI n1439 FCITOFCO_D --- 0.317 R4C12A.FCI to R4C12A.FCO SLICE_2 ROUTE 1 0.000 R4C12A.FCO to R4C12B.FCI n1440 FCITOFCO_D --- 0.317 R4C12B.FCI to R4C12B.FCO SLICE_1 ROUTE 1 0.000 R4C12B.FCO to R4C12C.FCI n1441 FCITOFCO_D --- 0.317 R4C12C.FCI to R4C12C.FCO SLICE_59 ROUTE 1 0.000 R4C12C.FCO to R4C12D.FCI n1442 FCITOFCO_D --- 0.317 R4C12D.FCI to R4C12D.FCO SLICE_57 ROUTE 1 0.000 R4C12D.FCO to R4C13A.FCI n1443 FCITOFCO_D --- 0.317 R4C13A.FCI to R4C13A.FCO SLICE_55 ROUTE 1 0.000 R4C13A.FCO to R4C13B.FCI n1444 FCITOFCO_D --- 0.317 R4C13B.FCI to R4C13B.FCO SLICE_54 ROUTE 1 0.000 R4C13B.FCO to R4C13C.FCI n1445 FCITOFCO_D --- 0.317 R4C13C.FCI to R4C13C.FCO SLICE_53 ROUTE 1 0.000 R4C13C.FCO to R4C13D.FCI n1446 FCITOFCO_D --- 0.317 R4C13D.FCI to R4C13D.FCO SLICE_52 ROUTE 1 0.000 R4C13D.FCO to R4C14A.FCI n1447 FCITOF0_DE --- 1.181 R4C14A.FCI to R4C14A.F0 SLICE_51 ROUTE 1 0.000 R4C14A.F0 to R4C14A.DI0 n118_adj_128 (to CLK0_OUT) -------- 8.868 (83.1% logic, 16.9% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C11B.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_51: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C14A.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.185ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i0 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i22 (to CLK0_OUT +) Delay: 8.716ns (82.8% logic, 17.2% route), 13 logic levels. Constraint Details: 8.716ns physical path delay SLICE_12 to SLICE_52 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.185ns Physical Path Details: Data path SLICE_12 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C11A.CLK to R4C11A.Q1 SLICE_12 (from CLK0_OUT) ROUTE 1 1.498 R4C11A.Q1 to R4C11A.A1 n27_adj_126 C1TOFCO_DE --- 1.795 R4C11A.A1 to R4C11A.FCO SLICE_12 ROUTE 1 0.000 R4C11A.FCO to R4C11B.FCI n1436 FCITOFCO_D --- 0.317 R4C11B.FCI to R4C11B.FCO SLICE_7 ROUTE 1 0.000 R4C11B.FCO to R4C11C.FCI n1437 FCITOFCO_D --- 0.317 R4C11C.FCI to R4C11C.FCO SLICE_6 ROUTE 1 0.000 R4C11C.FCO to R4C11D.FCI n1438 FCITOFCO_D --- 0.317 R4C11D.FCI to R4C11D.FCO SLICE_3 ROUTE 1 0.000 R4C11D.FCO to R4C12A.FCI n1439 FCITOFCO_D --- 0.317 R4C12A.FCI to R4C12A.FCO SLICE_2 ROUTE 1 0.000 R4C12A.FCO to R4C12B.FCI n1440 FCITOFCO_D --- 0.317 R4C12B.FCI to R4C12B.FCO SLICE_1 ROUTE 1 0.000 R4C12B.FCO to R4C12C.FCI n1441 FCITOFCO_D --- 0.317 R4C12C.FCI to R4C12C.FCO SLICE_59 ROUTE 1 0.000 R4C12C.FCO to R4C12D.FCI n1442 FCITOFCO_D --- 0.317 R4C12D.FCI to R4C12D.FCO SLICE_57 ROUTE 1 0.000 R4C12D.FCO to R4C13A.FCI n1443 FCITOFCO_D --- 0.317 R4C13A.FCI to R4C13A.FCO SLICE_55 ROUTE 1 0.000 R4C13A.FCO to R4C13B.FCI n1444 FCITOFCO_D --- 0.317 R4C13B.FCI to R4C13B.FCO SLICE_54 ROUTE 1 0.000 R4C13B.FCO to R4C13C.FCI n1445 FCITOFCO_D --- 0.317 R4C13C.FCI to R4C13C.FCO SLICE_53 ROUTE 1 0.000 R4C13C.FCO to R4C13D.FCI n1446 FCITOF1_DE --- 1.298 R4C13D.FCI to R4C13D.F1 SLICE_52 ROUTE 1 0.000 R4C13D.F1 to R4C13D.DI1 n119_adj_129 (to CLK0_OUT) -------- 8.716 (82.8% logic, 17.2% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C11A.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_52: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C13D.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.185ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i2 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i24 (to CLK0_OUT +) Delay: 8.716ns (82.8% logic, 17.2% route), 13 logic levels. Constraint Details: 8.716ns physical path delay SLICE_7 to SLICE_51 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.185ns Physical Path Details: Data path SLICE_7 to SLICE_51: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C11B.CLK to R4C11B.Q1 SLICE_7 (from CLK0_OUT) ROUTE 1 1.498 R4C11B.Q1 to R4C11B.A1 n25_adj_124 C1TOFCO_DE --- 1.795 R4C11B.A1 to R4C11B.FCO SLICE_7 ROUTE 1 0.000 R4C11B.FCO to R4C11C.FCI n1437 FCITOFCO_D --- 0.317 R4C11C.FCI to R4C11C.FCO SLICE_6 ROUTE 1 0.000 R4C11C.FCO to R4C11D.FCI n1438 FCITOFCO_D --- 0.317 R4C11D.FCI to R4C11D.FCO SLICE_3 ROUTE 1 0.000 R4C11D.FCO to R4C12A.FCI n1439 FCITOFCO_D --- 0.317 R4C12A.FCI to R4C12A.FCO SLICE_2 ROUTE 1 0.000 R4C12A.FCO to R4C12B.FCI n1440 FCITOFCO_D --- 0.317 R4C12B.FCI to R4C12B.FCO SLICE_1 ROUTE 1 0.000 R4C12B.FCO to R4C12C.FCI n1441 FCITOFCO_D --- 0.317 R4C12C.FCI to R4C12C.FCO SLICE_59 ROUTE 1 0.000 R4C12C.FCO to R4C12D.FCI n1442 FCITOFCO_D --- 0.317 R4C12D.FCI to R4C12D.FCO SLICE_57 ROUTE 1 0.000 R4C12D.FCO to R4C13A.FCI n1443 FCITOFCO_D --- 0.317 R4C13A.FCI to R4C13A.FCO SLICE_55 ROUTE 1 0.000 R4C13A.FCO to R4C13B.FCI n1444 FCITOFCO_D --- 0.317 R4C13B.FCI to R4C13B.FCO SLICE_54 ROUTE 1 0.000 R4C13B.FCO to R4C13C.FCI n1445 FCITOFCO_D --- 0.317 R4C13C.FCI to R4C13C.FCO SLICE_53 ROUTE 1 0.000 R4C13C.FCO to R4C13D.FCI n1446 FCITOFCO_D --- 0.317 R4C13D.FCI to R4C13D.FCO SLICE_52 ROUTE 1 0.000 R4C13D.FCO to R4C14A.FCI n1447 FCITOF1_DE --- 1.298 R4C14A.FCI to R4C14A.F1 SLICE_51 ROUTE 1 0.000 R4C14A.F1 to R4C14A.DI1 n117_adj_127 (to CLK0_OUT) -------- 8.716 (82.8% logic, 17.2% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C11B.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_51: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C14A.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.233ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i3 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i24 (to CLK0_OUT +) Delay: 8.668ns (82.7% logic, 17.3% route), 12 logic levels. Constraint Details: 8.668ns physical path delay SLICE_6 to SLICE_51 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.233ns Physical Path Details: Data path SLICE_6 to SLICE_51: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C11C.CLK to R4C11C.Q0 SLICE_6 (from CLK0_OUT) ROUTE 1 1.498 R4C11C.Q0 to R4C11C.A0 n24_adj_123 C0TOFCO_DE --- 2.064 R4C11C.A0 to R4C11C.FCO SLICE_6 ROUTE 1 0.000 R4C11C.FCO to R4C11D.FCI n1438 FCITOFCO_D --- 0.317 R4C11D.FCI to R4C11D.FCO SLICE_3 ROUTE 1 0.000 R4C11D.FCO to R4C12A.FCI n1439 FCITOFCO_D --- 0.317 R4C12A.FCI to R4C12A.FCO SLICE_2 ROUTE 1 0.000 R4C12A.FCO to R4C12B.FCI n1440 FCITOFCO_D --- 0.317 R4C12B.FCI to R4C12B.FCO SLICE_1 ROUTE 1 0.000 R4C12B.FCO to R4C12C.FCI n1441 FCITOFCO_D --- 0.317 R4C12C.FCI to R4C12C.FCO SLICE_59 ROUTE 1 0.000 R4C12C.FCO to R4C12D.FCI n1442 FCITOFCO_D --- 0.317 R4C12D.FCI to R4C12D.FCO SLICE_57 ROUTE 1 0.000 R4C12D.FCO to R4C13A.FCI n1443 FCITOFCO_D --- 0.317 R4C13A.FCI to R4C13A.FCO SLICE_55 ROUTE 1 0.000 R4C13A.FCO to R4C13B.FCI n1444 FCITOFCO_D --- 0.317 R4C13B.FCI to R4C13B.FCO SLICE_54 ROUTE 1 0.000 R4C13B.FCO to R4C13C.FCI n1445 FCITOFCO_D --- 0.317 R4C13C.FCI to R4C13C.FCO SLICE_53 ROUTE 1 0.000 R4C13C.FCO to R4C13D.FCI n1446 FCITOFCO_D --- 0.317 R4C13D.FCI to R4C13D.FCO SLICE_52 ROUTE 1 0.000 R4C13D.FCO to R4C14A.FCI n1447 FCITOF1_DE --- 1.298 R4C14A.FCI to R4C14A.F1 SLICE_51 ROUTE 1 0.000 R4C14A.F1 to R4C14A.DI1 n117_adj_127 (to CLK0_OUT) -------- 8.668 (82.7% logic, 17.3% route), 12 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C11C.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_51: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C14A.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.233ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i1 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i22 (to CLK0_OUT +) Delay: 8.668ns (82.7% logic, 17.3% route), 12 logic levels. Constraint Details: 8.668ns physical path delay SLICE_7 to SLICE_52 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.233ns Physical Path Details: Data path SLICE_7 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C11B.CLK to R4C11B.Q0 SLICE_7 (from CLK0_OUT) ROUTE 1 1.498 R4C11B.Q0 to R4C11B.A0 n26_adj_125 C0TOFCO_DE --- 2.064 R4C11B.A0 to R4C11B.FCO SLICE_7 ROUTE 1 0.000 R4C11B.FCO to R4C11C.FCI n1437 FCITOFCO_D --- 0.317 R4C11C.FCI to R4C11C.FCO SLICE_6 ROUTE 1 0.000 R4C11C.FCO to R4C11D.FCI n1438 FCITOFCO_D --- 0.317 R4C11D.FCI to R4C11D.FCO SLICE_3 ROUTE 1 0.000 R4C11D.FCO to R4C12A.FCI n1439 FCITOFCO_D --- 0.317 R4C12A.FCI to R4C12A.FCO SLICE_2 ROUTE 1 0.000 R4C12A.FCO to R4C12B.FCI n1440 FCITOFCO_D --- 0.317 R4C12B.FCI to R4C12B.FCO SLICE_1 ROUTE 1 0.000 R4C12B.FCO to R4C12C.FCI n1441 FCITOFCO_D --- 0.317 R4C12C.FCI to R4C12C.FCO SLICE_59 ROUTE 1 0.000 R4C12C.FCO to R4C12D.FCI n1442 FCITOFCO_D --- 0.317 R4C12D.FCI to R4C12D.FCO SLICE_57 ROUTE 1 0.000 R4C12D.FCO to R4C13A.FCI n1443 FCITOFCO_D --- 0.317 R4C13A.FCI to R4C13A.FCO SLICE_55 ROUTE 1 0.000 R4C13A.FCO to R4C13B.FCI n1444 FCITOFCO_D --- 0.317 R4C13B.FCI to R4C13B.FCO SLICE_54 ROUTE 1 0.000 R4C13B.FCO to R4C13C.FCI n1445 FCITOFCO_D --- 0.317 R4C13C.FCI to R4C13C.FCO SLICE_53 ROUTE 1 0.000 R4C13C.FCO to R4C13D.FCI n1446 FCITOF1_DE --- 1.298 R4C13D.FCI to R4C13D.F1 SLICE_52 ROUTE 1 0.000 R4C13D.F1 to R4C13D.DI1 n119_adj_129 (to CLK0_OUT) -------- 8.668 (82.7% logic, 17.3% route), 12 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C11B.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_52: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C13D.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.302ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i0 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i21 (to CLK0_OUT +) Delay: 8.599ns (82.6% logic, 17.4% route), 13 logic levels. Constraint Details: 8.599ns physical path delay SLICE_12 to SLICE_52 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.302ns Physical Path Details: Data path SLICE_12 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C11A.CLK to R4C11A.Q1 SLICE_12 (from CLK0_OUT) ROUTE 1 1.498 R4C11A.Q1 to R4C11A.A1 n27_adj_126 C1TOFCO_DE --- 1.795 R4C11A.A1 to R4C11A.FCO SLICE_12 ROUTE 1 0.000 R4C11A.FCO to R4C11B.FCI n1436 FCITOFCO_D --- 0.317 R4C11B.FCI to R4C11B.FCO SLICE_7 ROUTE 1 0.000 R4C11B.FCO to R4C11C.FCI n1437 FCITOFCO_D --- 0.317 R4C11C.FCI to R4C11C.FCO SLICE_6 ROUTE 1 0.000 R4C11C.FCO to R4C11D.FCI n1438 FCITOFCO_D --- 0.317 R4C11D.FCI to R4C11D.FCO SLICE_3 ROUTE 1 0.000 R4C11D.FCO to R4C12A.FCI n1439 FCITOFCO_D --- 0.317 R4C12A.FCI to R4C12A.FCO SLICE_2 ROUTE 1 0.000 R4C12A.FCO to R4C12B.FCI n1440 FCITOFCO_D --- 0.317 R4C12B.FCI to R4C12B.FCO SLICE_1 ROUTE 1 0.000 R4C12B.FCO to R4C12C.FCI n1441 FCITOFCO_D --- 0.317 R4C12C.FCI to R4C12C.FCO SLICE_59 ROUTE 1 0.000 R4C12C.FCO to R4C12D.FCI n1442 FCITOFCO_D --- 0.317 R4C12D.FCI to R4C12D.FCO SLICE_57 ROUTE 1 0.000 R4C12D.FCO to R4C13A.FCI n1443 FCITOFCO_D --- 0.317 R4C13A.FCI to R4C13A.FCO SLICE_55 ROUTE 1 0.000 R4C13A.FCO to R4C13B.FCI n1444 FCITOFCO_D --- 0.317 R4C13B.FCI to R4C13B.FCO SLICE_54 ROUTE 1 0.000 R4C13B.FCO to R4C13C.FCI n1445 FCITOFCO_D --- 0.317 R4C13C.FCI to R4C13C.FCO SLICE_53 ROUTE 1 0.000 R4C13C.FCO to R4C13D.FCI n1446 FCITOF0_DE --- 1.181 R4C13D.FCI to R4C13D.F0 SLICE_52 ROUTE 1 0.000 R4C13D.F0 to R4C13D.DI0 n120_adj_130 (to CLK0_OUT) -------- 8.599 (82.6% logic, 17.4% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C11A.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_52: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C13D.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.302ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i2 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i23 (to CLK0_OUT +) Delay: 8.599ns (82.6% logic, 17.4% route), 13 logic levels. Constraint Details: 8.599ns physical path delay SLICE_7 to SLICE_51 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.302ns Physical Path Details: Data path SLICE_7 to SLICE_51: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C11B.CLK to R4C11B.Q1 SLICE_7 (from CLK0_OUT) ROUTE 1 1.498 R4C11B.Q1 to R4C11B.A1 n25_adj_124 C1TOFCO_DE --- 1.795 R4C11B.A1 to R4C11B.FCO SLICE_7 ROUTE 1 0.000 R4C11B.FCO to R4C11C.FCI n1437 FCITOFCO_D --- 0.317 R4C11C.FCI to R4C11C.FCO SLICE_6 ROUTE 1 0.000 R4C11C.FCO to R4C11D.FCI n1438 FCITOFCO_D --- 0.317 R4C11D.FCI to R4C11D.FCO SLICE_3 ROUTE 1 0.000 R4C11D.FCO to R4C12A.FCI n1439 FCITOFCO_D --- 0.317 R4C12A.FCI to R4C12A.FCO SLICE_2 ROUTE 1 0.000 R4C12A.FCO to R4C12B.FCI n1440 FCITOFCO_D --- 0.317 R4C12B.FCI to R4C12B.FCO SLICE_1 ROUTE 1 0.000 R4C12B.FCO to R4C12C.FCI n1441 FCITOFCO_D --- 0.317 R4C12C.FCI to R4C12C.FCO SLICE_59 ROUTE 1 0.000 R4C12C.FCO to R4C12D.FCI n1442 FCITOFCO_D --- 0.317 R4C12D.FCI to R4C12D.FCO SLICE_57 ROUTE 1 0.000 R4C12D.FCO to R4C13A.FCI n1443 FCITOFCO_D --- 0.317 R4C13A.FCI to R4C13A.FCO SLICE_55 ROUTE 1 0.000 R4C13A.FCO to R4C13B.FCI n1444 FCITOFCO_D --- 0.317 R4C13B.FCI to R4C13B.FCO SLICE_54 ROUTE 1 0.000 R4C13B.FCO to R4C13C.FCI n1445 FCITOFCO_D --- 0.317 R4C13C.FCI to R4C13C.FCO SLICE_53 ROUTE 1 0.000 R4C13C.FCO to R4C13D.FCI n1446 FCITOFCO_D --- 0.317 R4C13D.FCI to R4C13D.FCO SLICE_52 ROUTE 1 0.000 R4C13D.FCO to R4C14A.FCI n1447 FCITOF0_DE --- 1.181 R4C14A.FCI to R4C14A.F0 SLICE_51 ROUTE 1 0.000 R4C14A.F0 to R4C14A.DI0 n118_adj_128 (to CLK0_OUT) -------- 8.599 (82.6% logic, 17.4% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C11B.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_51: Name Fanout Delay (ns) Site Resource ROUTE 14 3.680 LPLL.CLKOP to R4C14A.CLK CLK0_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Report: 105.652MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "CLK90_OUT" 12.000000 MHz ; 325 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 73.868ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i0 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i24 (to CLK90_OUT +) Delay: 9.033ns (83.4% logic, 16.6% route), 14 logic levels. Constraint Details: 9.033ns physical path delay SLICE_71 to SLICE_15 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 73.868ns Physical Path Details: Data path SLICE_71 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C5A.CLK to R3C5A.Q1 SLICE_71 (from CLK90_OUT) ROUTE 1 1.498 R3C5A.Q1 to R3C5A.A1 n27_adj_77 C1TOFCO_DE --- 1.795 R3C5A.A1 to R3C5A.FCO SLICE_71 ROUTE 1 0.000 R3C5A.FCO to R3C5B.FCI n1422 FCITOFCO_D --- 0.317 R3C5B.FCI to R3C5B.FCO SLICE_70 ROUTE 1 0.000 R3C5B.FCO to R3C5C.FCI n1423 FCITOFCO_D --- 0.317 R3C5C.FCI to R3C5C.FCO SLICE_68 ROUTE 1 0.000 R3C5C.FCO to R3C5D.FCI n1424 FCITOFCO_D --- 0.317 R3C5D.FCI to R3C5D.FCO SLICE_66 ROUTE 1 0.000 R3C5D.FCO to R3C6A.FCI n1425 FCITOFCO_D --- 0.317 R3C6A.FCI to R3C6A.FCO SLICE_63 ROUTE 1 0.000 R3C6A.FCO to R3C6B.FCI n1426 FCITOFCO_D --- 0.317 R3C6B.FCI to R3C6B.FCO SLICE_62 ROUTE 1 0.000 R3C6B.FCO to R3C6C.FCI n1427 FCITOFCO_D --- 0.317 R3C6C.FCI to R3C6C.FCO SLICE_61 ROUTE 1 0.000 R3C6C.FCO to R3C6D.FCI n1428 FCITOFCO_D --- 0.317 R3C6D.FCI to R3C6D.FCO SLICE_24 ROUTE 1 0.000 R3C6D.FCO to R3C7A.FCI n1429 FCITOFCO_D --- 0.317 R3C7A.FCI to R3C7A.FCO SLICE_23 ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI n1430 FCITOFCO_D --- 0.317 R3C7B.FCI to R3C7B.FCO SLICE_20 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI n1431 FCITOFCO_D --- 0.317 R3C7C.FCI to R3C7C.FCO SLICE_17 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI n1432 FCITOFCO_D --- 0.317 R3C7D.FCI to R3C7D.FCO SLICE_16 ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI n1433 FCITOF1_DE --- 1.298 R3C8A.FCI to R3C8A.F1 SLICE_15 ROUTE 1 0.000 R3C8A.F1 to R3C8A.DI1 n117_adj_78 (to CLK90_OUT) -------- 9.033 (83.4% logic, 16.6% route), 14 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_71: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C5A.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C8A.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 73.916ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i1 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i24 (to CLK90_OUT +) Delay: 8.985ns (83.3% logic, 16.7% route), 13 logic levels. Constraint Details: 8.985ns physical path delay SLICE_70 to SLICE_15 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 73.916ns Physical Path Details: Data path SLICE_70 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C5B.CLK to R3C5B.Q0 SLICE_70 (from CLK90_OUT) ROUTE 1 1.498 R3C5B.Q0 to R3C5B.A0 n26_adj_76 C0TOFCO_DE --- 2.064 R3C5B.A0 to R3C5B.FCO SLICE_70 ROUTE 1 0.000 R3C5B.FCO to R3C5C.FCI n1423 FCITOFCO_D --- 0.317 R3C5C.FCI to R3C5C.FCO SLICE_68 ROUTE 1 0.000 R3C5C.FCO to R3C5D.FCI n1424 FCITOFCO_D --- 0.317 R3C5D.FCI to R3C5D.FCO SLICE_66 ROUTE 1 0.000 R3C5D.FCO to R3C6A.FCI n1425 FCITOFCO_D --- 0.317 R3C6A.FCI to R3C6A.FCO SLICE_63 ROUTE 1 0.000 R3C6A.FCO to R3C6B.FCI n1426 FCITOFCO_D --- 0.317 R3C6B.FCI to R3C6B.FCO SLICE_62 ROUTE 1 0.000 R3C6B.FCO to R3C6C.FCI n1427 FCITOFCO_D --- 0.317 R3C6C.FCI to R3C6C.FCO SLICE_61 ROUTE 1 0.000 R3C6C.FCO to R3C6D.FCI n1428 FCITOFCO_D --- 0.317 R3C6D.FCI to R3C6D.FCO SLICE_24 ROUTE 1 0.000 R3C6D.FCO to R3C7A.FCI n1429 FCITOFCO_D --- 0.317 R3C7A.FCI to R3C7A.FCO SLICE_23 ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI n1430 FCITOFCO_D --- 0.317 R3C7B.FCI to R3C7B.FCO SLICE_20 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI n1431 FCITOFCO_D --- 0.317 R3C7C.FCI to R3C7C.FCO SLICE_17 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI n1432 FCITOFCO_D --- 0.317 R3C7D.FCI to R3C7D.FCO SLICE_16 ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI n1433 FCITOF1_DE --- 1.298 R3C8A.FCI to R3C8A.F1 SLICE_15 ROUTE 1 0.000 R3C8A.F1 to R3C8A.DI1 n117_adj_78 (to CLK90_OUT) -------- 8.985 (83.3% logic, 16.7% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_70: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C5B.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C8A.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 73.985ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i0 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i23 (to CLK90_OUT +) Delay: 8.916ns (83.2% logic, 16.8% route), 14 logic levels. Constraint Details: 8.916ns physical path delay SLICE_71 to SLICE_15 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 73.985ns Physical Path Details: Data path SLICE_71 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C5A.CLK to R3C5A.Q1 SLICE_71 (from CLK90_OUT) ROUTE 1 1.498 R3C5A.Q1 to R3C5A.A1 n27_adj_77 C1TOFCO_DE --- 1.795 R3C5A.A1 to R3C5A.FCO SLICE_71 ROUTE 1 0.000 R3C5A.FCO to R3C5B.FCI n1422 FCITOFCO_D --- 0.317 R3C5B.FCI to R3C5B.FCO SLICE_70 ROUTE 1 0.000 R3C5B.FCO to R3C5C.FCI n1423 FCITOFCO_D --- 0.317 R3C5C.FCI to R3C5C.FCO SLICE_68 ROUTE 1 0.000 R3C5C.FCO to R3C5D.FCI n1424 FCITOFCO_D --- 0.317 R3C5D.FCI to R3C5D.FCO SLICE_66 ROUTE 1 0.000 R3C5D.FCO to R3C6A.FCI n1425 FCITOFCO_D --- 0.317 R3C6A.FCI to R3C6A.FCO SLICE_63 ROUTE 1 0.000 R3C6A.FCO to R3C6B.FCI n1426 FCITOFCO_D --- 0.317 R3C6B.FCI to R3C6B.FCO SLICE_62 ROUTE 1 0.000 R3C6B.FCO to R3C6C.FCI n1427 FCITOFCO_D --- 0.317 R3C6C.FCI to R3C6C.FCO SLICE_61 ROUTE 1 0.000 R3C6C.FCO to R3C6D.FCI n1428 FCITOFCO_D --- 0.317 R3C6D.FCI to R3C6D.FCO SLICE_24 ROUTE 1 0.000 R3C6D.FCO to R3C7A.FCI n1429 FCITOFCO_D --- 0.317 R3C7A.FCI to R3C7A.FCO SLICE_23 ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI n1430 FCITOFCO_D --- 0.317 R3C7B.FCI to R3C7B.FCO SLICE_20 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI n1431 FCITOFCO_D --- 0.317 R3C7C.FCI to R3C7C.FCO SLICE_17 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI n1432 FCITOFCO_D --- 0.317 R3C7D.FCI to R3C7D.FCO SLICE_16 ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI n1433 FCITOF0_DE --- 1.181 R3C8A.FCI to R3C8A.F0 SLICE_15 ROUTE 1 0.000 R3C8A.F0 to R3C8A.DI0 n118_adj_79 (to CLK90_OUT) -------- 8.916 (83.2% logic, 16.8% route), 14 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_71: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C5A.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C8A.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.033ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i1 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i23 (to CLK90_OUT +) Delay: 8.868ns (83.1% logic, 16.9% route), 13 logic levels. Constraint Details: 8.868ns physical path delay SLICE_70 to SLICE_15 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.033ns Physical Path Details: Data path SLICE_70 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C5B.CLK to R3C5B.Q0 SLICE_70 (from CLK90_OUT) ROUTE 1 1.498 R3C5B.Q0 to R3C5B.A0 n26_adj_76 C0TOFCO_DE --- 2.064 R3C5B.A0 to R3C5B.FCO SLICE_70 ROUTE 1 0.000 R3C5B.FCO to R3C5C.FCI n1423 FCITOFCO_D --- 0.317 R3C5C.FCI to R3C5C.FCO SLICE_68 ROUTE 1 0.000 R3C5C.FCO to R3C5D.FCI n1424 FCITOFCO_D --- 0.317 R3C5D.FCI to R3C5D.FCO SLICE_66 ROUTE 1 0.000 R3C5D.FCO to R3C6A.FCI n1425 FCITOFCO_D --- 0.317 R3C6A.FCI to R3C6A.FCO SLICE_63 ROUTE 1 0.000 R3C6A.FCO to R3C6B.FCI n1426 FCITOFCO_D --- 0.317 R3C6B.FCI to R3C6B.FCO SLICE_62 ROUTE 1 0.000 R3C6B.FCO to R3C6C.FCI n1427 FCITOFCO_D --- 0.317 R3C6C.FCI to R3C6C.FCO SLICE_61 ROUTE 1 0.000 R3C6C.FCO to R3C6D.FCI n1428 FCITOFCO_D --- 0.317 R3C6D.FCI to R3C6D.FCO SLICE_24 ROUTE 1 0.000 R3C6D.FCO to R3C7A.FCI n1429 FCITOFCO_D --- 0.317 R3C7A.FCI to R3C7A.FCO SLICE_23 ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI n1430 FCITOFCO_D --- 0.317 R3C7B.FCI to R3C7B.FCO SLICE_20 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI n1431 FCITOFCO_D --- 0.317 R3C7C.FCI to R3C7C.FCO SLICE_17 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI n1432 FCITOFCO_D --- 0.317 R3C7D.FCI to R3C7D.FCO SLICE_16 ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI n1433 FCITOF0_DE --- 1.181 R3C8A.FCI to R3C8A.F0 SLICE_15 ROUTE 1 0.000 R3C8A.F0 to R3C8A.DI0 n118_adj_79 (to CLK90_OUT) -------- 8.868 (83.1% logic, 16.9% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_70: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C5B.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C8A.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.185ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i2 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i24 (to CLK90_OUT +) Delay: 8.716ns (82.8% logic, 17.2% route), 13 logic levels. Constraint Details: 8.716ns physical path delay SLICE_70 to SLICE_15 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.185ns Physical Path Details: Data path SLICE_70 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C5B.CLK to R3C5B.Q1 SLICE_70 (from CLK90_OUT) ROUTE 1 1.498 R3C5B.Q1 to R3C5B.A1 n25_adj_75 C1TOFCO_DE --- 1.795 R3C5B.A1 to R3C5B.FCO SLICE_70 ROUTE 1 0.000 R3C5B.FCO to R3C5C.FCI n1423 FCITOFCO_D --- 0.317 R3C5C.FCI to R3C5C.FCO SLICE_68 ROUTE 1 0.000 R3C5C.FCO to R3C5D.FCI n1424 FCITOFCO_D --- 0.317 R3C5D.FCI to R3C5D.FCO SLICE_66 ROUTE 1 0.000 R3C5D.FCO to R3C6A.FCI n1425 FCITOFCO_D --- 0.317 R3C6A.FCI to R3C6A.FCO SLICE_63 ROUTE 1 0.000 R3C6A.FCO to R3C6B.FCI n1426 FCITOFCO_D --- 0.317 R3C6B.FCI to R3C6B.FCO SLICE_62 ROUTE 1 0.000 R3C6B.FCO to R3C6C.FCI n1427 FCITOFCO_D --- 0.317 R3C6C.FCI to R3C6C.FCO SLICE_61 ROUTE 1 0.000 R3C6C.FCO to R3C6D.FCI n1428 FCITOFCO_D --- 0.317 R3C6D.FCI to R3C6D.FCO SLICE_24 ROUTE 1 0.000 R3C6D.FCO to R3C7A.FCI n1429 FCITOFCO_D --- 0.317 R3C7A.FCI to R3C7A.FCO SLICE_23 ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI n1430 FCITOFCO_D --- 0.317 R3C7B.FCI to R3C7B.FCO SLICE_20 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI n1431 FCITOFCO_D --- 0.317 R3C7C.FCI to R3C7C.FCO SLICE_17 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI n1432 FCITOFCO_D --- 0.317 R3C7D.FCI to R3C7D.FCO SLICE_16 ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI n1433 FCITOF1_DE --- 1.298 R3C8A.FCI to R3C8A.F1 SLICE_15 ROUTE 1 0.000 R3C8A.F1 to R3C8A.DI1 n117_adj_78 (to CLK90_OUT) -------- 8.716 (82.8% logic, 17.2% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_70: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C5B.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C8A.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.185ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i0 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i22 (to CLK90_OUT +) Delay: 8.716ns (82.8% logic, 17.2% route), 13 logic levels. Constraint Details: 8.716ns physical path delay SLICE_71 to SLICE_16 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.185ns Physical Path Details: Data path SLICE_71 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C5A.CLK to R3C5A.Q1 SLICE_71 (from CLK90_OUT) ROUTE 1 1.498 R3C5A.Q1 to R3C5A.A1 n27_adj_77 C1TOFCO_DE --- 1.795 R3C5A.A1 to R3C5A.FCO SLICE_71 ROUTE 1 0.000 R3C5A.FCO to R3C5B.FCI n1422 FCITOFCO_D --- 0.317 R3C5B.FCI to R3C5B.FCO SLICE_70 ROUTE 1 0.000 R3C5B.FCO to R3C5C.FCI n1423 FCITOFCO_D --- 0.317 R3C5C.FCI to R3C5C.FCO SLICE_68 ROUTE 1 0.000 R3C5C.FCO to R3C5D.FCI n1424 FCITOFCO_D --- 0.317 R3C5D.FCI to R3C5D.FCO SLICE_66 ROUTE 1 0.000 R3C5D.FCO to R3C6A.FCI n1425 FCITOFCO_D --- 0.317 R3C6A.FCI to R3C6A.FCO SLICE_63 ROUTE 1 0.000 R3C6A.FCO to R3C6B.FCI n1426 FCITOFCO_D --- 0.317 R3C6B.FCI to R3C6B.FCO SLICE_62 ROUTE 1 0.000 R3C6B.FCO to R3C6C.FCI n1427 FCITOFCO_D --- 0.317 R3C6C.FCI to R3C6C.FCO SLICE_61 ROUTE 1 0.000 R3C6C.FCO to R3C6D.FCI n1428 FCITOFCO_D --- 0.317 R3C6D.FCI to R3C6D.FCO SLICE_24 ROUTE 1 0.000 R3C6D.FCO to R3C7A.FCI n1429 FCITOFCO_D --- 0.317 R3C7A.FCI to R3C7A.FCO SLICE_23 ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI n1430 FCITOFCO_D --- 0.317 R3C7B.FCI to R3C7B.FCO SLICE_20 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI n1431 FCITOFCO_D --- 0.317 R3C7C.FCI to R3C7C.FCO SLICE_17 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI n1432 FCITOF1_DE --- 1.298 R3C7D.FCI to R3C7D.F1 SLICE_16 ROUTE 1 0.000 R3C7D.F1 to R3C7D.DI1 n119_adj_80 (to CLK90_OUT) -------- 8.716 (82.8% logic, 17.2% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_71: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C5A.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C7D.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.233ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i3 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i24 (to CLK90_OUT +) Delay: 8.668ns (82.7% logic, 17.3% route), 12 logic levels. Constraint Details: 8.668ns physical path delay SLICE_68 to SLICE_15 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.233ns Physical Path Details: Data path SLICE_68 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C5C.CLK to R3C5C.Q0 SLICE_68 (from CLK90_OUT) ROUTE 1 1.498 R3C5C.Q0 to R3C5C.A0 n24_adj_74 C0TOFCO_DE --- 2.064 R3C5C.A0 to R3C5C.FCO SLICE_68 ROUTE 1 0.000 R3C5C.FCO to R3C5D.FCI n1424 FCITOFCO_D --- 0.317 R3C5D.FCI to R3C5D.FCO SLICE_66 ROUTE 1 0.000 R3C5D.FCO to R3C6A.FCI n1425 FCITOFCO_D --- 0.317 R3C6A.FCI to R3C6A.FCO SLICE_63 ROUTE 1 0.000 R3C6A.FCO to R3C6B.FCI n1426 FCITOFCO_D --- 0.317 R3C6B.FCI to R3C6B.FCO SLICE_62 ROUTE 1 0.000 R3C6B.FCO to R3C6C.FCI n1427 FCITOFCO_D --- 0.317 R3C6C.FCI to R3C6C.FCO SLICE_61 ROUTE 1 0.000 R3C6C.FCO to R3C6D.FCI n1428 FCITOFCO_D --- 0.317 R3C6D.FCI to R3C6D.FCO SLICE_24 ROUTE 1 0.000 R3C6D.FCO to R3C7A.FCI n1429 FCITOFCO_D --- 0.317 R3C7A.FCI to R3C7A.FCO SLICE_23 ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI n1430 FCITOFCO_D --- 0.317 R3C7B.FCI to R3C7B.FCO SLICE_20 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI n1431 FCITOFCO_D --- 0.317 R3C7C.FCI to R3C7C.FCO SLICE_17 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI n1432 FCITOFCO_D --- 0.317 R3C7D.FCI to R3C7D.FCO SLICE_16 ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI n1433 FCITOF1_DE --- 1.298 R3C8A.FCI to R3C8A.F1 SLICE_15 ROUTE 1 0.000 R3C8A.F1 to R3C8A.DI1 n117_adj_78 (to CLK90_OUT) -------- 8.668 (82.7% logic, 17.3% route), 12 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_68: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C5C.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C8A.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.233ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i1 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i22 (to CLK90_OUT +) Delay: 8.668ns (82.7% logic, 17.3% route), 12 logic levels. Constraint Details: 8.668ns physical path delay SLICE_70 to SLICE_16 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.233ns Physical Path Details: Data path SLICE_70 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C5B.CLK to R3C5B.Q0 SLICE_70 (from CLK90_OUT) ROUTE 1 1.498 R3C5B.Q0 to R3C5B.A0 n26_adj_76 C0TOFCO_DE --- 2.064 R3C5B.A0 to R3C5B.FCO SLICE_70 ROUTE 1 0.000 R3C5B.FCO to R3C5C.FCI n1423 FCITOFCO_D --- 0.317 R3C5C.FCI to R3C5C.FCO SLICE_68 ROUTE 1 0.000 R3C5C.FCO to R3C5D.FCI n1424 FCITOFCO_D --- 0.317 R3C5D.FCI to R3C5D.FCO SLICE_66 ROUTE 1 0.000 R3C5D.FCO to R3C6A.FCI n1425 FCITOFCO_D --- 0.317 R3C6A.FCI to R3C6A.FCO SLICE_63 ROUTE 1 0.000 R3C6A.FCO to R3C6B.FCI n1426 FCITOFCO_D --- 0.317 R3C6B.FCI to R3C6B.FCO SLICE_62 ROUTE 1 0.000 R3C6B.FCO to R3C6C.FCI n1427 FCITOFCO_D --- 0.317 R3C6C.FCI to R3C6C.FCO SLICE_61 ROUTE 1 0.000 R3C6C.FCO to R3C6D.FCI n1428 FCITOFCO_D --- 0.317 R3C6D.FCI to R3C6D.FCO SLICE_24 ROUTE 1 0.000 R3C6D.FCO to R3C7A.FCI n1429 FCITOFCO_D --- 0.317 R3C7A.FCI to R3C7A.FCO SLICE_23 ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI n1430 FCITOFCO_D --- 0.317 R3C7B.FCI to R3C7B.FCO SLICE_20 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI n1431 FCITOFCO_D --- 0.317 R3C7C.FCI to R3C7C.FCO SLICE_17 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI n1432 FCITOF1_DE --- 1.298 R3C7D.FCI to R3C7D.F1 SLICE_16 ROUTE 1 0.000 R3C7D.F1 to R3C7D.DI1 n119_adj_80 (to CLK90_OUT) -------- 8.668 (82.7% logic, 17.3% route), 12 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_70: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C5B.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C7D.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.302ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i2 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i23 (to CLK90_OUT +) Delay: 8.599ns (82.6% logic, 17.4% route), 13 logic levels. Constraint Details: 8.599ns physical path delay SLICE_70 to SLICE_15 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.302ns Physical Path Details: Data path SLICE_70 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C5B.CLK to R3C5B.Q1 SLICE_70 (from CLK90_OUT) ROUTE 1 1.498 R3C5B.Q1 to R3C5B.A1 n25_adj_75 C1TOFCO_DE --- 1.795 R3C5B.A1 to R3C5B.FCO SLICE_70 ROUTE 1 0.000 R3C5B.FCO to R3C5C.FCI n1423 FCITOFCO_D --- 0.317 R3C5C.FCI to R3C5C.FCO SLICE_68 ROUTE 1 0.000 R3C5C.FCO to R3C5D.FCI n1424 FCITOFCO_D --- 0.317 R3C5D.FCI to R3C5D.FCO SLICE_66 ROUTE 1 0.000 R3C5D.FCO to R3C6A.FCI n1425 FCITOFCO_D --- 0.317 R3C6A.FCI to R3C6A.FCO SLICE_63 ROUTE 1 0.000 R3C6A.FCO to R3C6B.FCI n1426 FCITOFCO_D --- 0.317 R3C6B.FCI to R3C6B.FCO SLICE_62 ROUTE 1 0.000 R3C6B.FCO to R3C6C.FCI n1427 FCITOFCO_D --- 0.317 R3C6C.FCI to R3C6C.FCO SLICE_61 ROUTE 1 0.000 R3C6C.FCO to R3C6D.FCI n1428 FCITOFCO_D --- 0.317 R3C6D.FCI to R3C6D.FCO SLICE_24 ROUTE 1 0.000 R3C6D.FCO to R3C7A.FCI n1429 FCITOFCO_D --- 0.317 R3C7A.FCI to R3C7A.FCO SLICE_23 ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI n1430 FCITOFCO_D --- 0.317 R3C7B.FCI to R3C7B.FCO SLICE_20 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI n1431 FCITOFCO_D --- 0.317 R3C7C.FCI to R3C7C.FCO SLICE_17 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI n1432 FCITOFCO_D --- 0.317 R3C7D.FCI to R3C7D.FCO SLICE_16 ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI n1433 FCITOF0_DE --- 1.181 R3C8A.FCI to R3C8A.F0 SLICE_15 ROUTE 1 0.000 R3C8A.F0 to R3C8A.DI0 n118_adj_79 (to CLK90_OUT) -------- 8.599 (82.6% logic, 17.4% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_70: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C5B.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C8A.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.302ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i0 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i21 (to CLK90_OUT +) Delay: 8.599ns (82.6% logic, 17.4% route), 13 logic levels. Constraint Details: 8.599ns physical path delay SLICE_71 to SLICE_16 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.302ns Physical Path Details: Data path SLICE_71 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R3C5A.CLK to R3C5A.Q1 SLICE_71 (from CLK90_OUT) ROUTE 1 1.498 R3C5A.Q1 to R3C5A.A1 n27_adj_77 C1TOFCO_DE --- 1.795 R3C5A.A1 to R3C5A.FCO SLICE_71 ROUTE 1 0.000 R3C5A.FCO to R3C5B.FCI n1422 FCITOFCO_D --- 0.317 R3C5B.FCI to R3C5B.FCO SLICE_70 ROUTE 1 0.000 R3C5B.FCO to R3C5C.FCI n1423 FCITOFCO_D --- 0.317 R3C5C.FCI to R3C5C.FCO SLICE_68 ROUTE 1 0.000 R3C5C.FCO to R3C5D.FCI n1424 FCITOFCO_D --- 0.317 R3C5D.FCI to R3C5D.FCO SLICE_66 ROUTE 1 0.000 R3C5D.FCO to R3C6A.FCI n1425 FCITOFCO_D --- 0.317 R3C6A.FCI to R3C6A.FCO SLICE_63 ROUTE 1 0.000 R3C6A.FCO to R3C6B.FCI n1426 FCITOFCO_D --- 0.317 R3C6B.FCI to R3C6B.FCO SLICE_62 ROUTE 1 0.000 R3C6B.FCO to R3C6C.FCI n1427 FCITOFCO_D --- 0.317 R3C6C.FCI to R3C6C.FCO SLICE_61 ROUTE 1 0.000 R3C6C.FCO to R3C6D.FCI n1428 FCITOFCO_D --- 0.317 R3C6D.FCI to R3C6D.FCO SLICE_24 ROUTE 1 0.000 R3C6D.FCO to R3C7A.FCI n1429 FCITOFCO_D --- 0.317 R3C7A.FCI to R3C7A.FCO SLICE_23 ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI n1430 FCITOFCO_D --- 0.317 R3C7B.FCI to R3C7B.FCO SLICE_20 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI n1431 FCITOFCO_D --- 0.317 R3C7C.FCI to R3C7C.FCO SLICE_17 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI n1432 FCITOF0_DE --- 1.181 R3C7D.FCI to R3C7D.F0 SLICE_16 ROUTE 1 0.000 R3C7D.F0 to R3C7D.DI0 n120_adj_81 (to CLK90_OUT) -------- 8.599 (82.6% logic, 17.4% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_71: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C5A.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS to R3C7D.CLK CLK90_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Report: 105.652MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; 325 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 73.868ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i0 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i24 (to CLK180_OUT +) Delay: 9.033ns (83.4% logic, 16.6% route), 14 logic levels. Constraint Details: 9.033ns physical path delay SLICE_58 to SLICE_72 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 73.868ns Physical Path Details: Data path SLICE_58 to SLICE_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R2C5A.CLK to R2C5A.Q1 SLICE_58 (from CLK180_OUT) ROUTE 1 1.498 R2C5A.Q1 to R2C5A.A1 n27_adj_2 C1TOFCO_DE --- 1.795 R2C5A.A1 to R2C5A.FCO SLICE_58 ROUTE 1 0.000 R2C5A.FCO to R2C5B.FCI n1408 FCITOFCO_D --- 0.317 R2C5B.FCI to R2C5B.FCO SLICE_19 ROUTE 1 0.000 R2C5B.FCO to R2C5C.FCI n1409 FCITOFCO_D --- 0.317 R2C5C.FCI to R2C5C.FCO SLICE_18 ROUTE 1 0.000 R2C5C.FCO to R2C5D.FCI n1410 FCITOFCO_D --- 0.317 R2C5D.FCI to R2C5D.FCO SLICE_14 ROUTE 1 0.000 R2C5D.FCO to R2C6A.FCI n1411 FCITOFCO_D --- 0.317 R2C6A.FCI to R2C6A.FCO SLICE_11 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1412 FCITOFCO_D --- 0.317 R2C6B.FCI to R2C6B.FCO SLICE_10 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1413 FCITOFCO_D --- 0.317 R2C6C.FCI to R2C6C.FCO SLICE_5 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1414 FCITOFCO_D --- 0.317 R2C6D.FCI to R2C6D.FCO SLICE_4 ROUTE 1 0.000 R2C6D.FCO to R2C7A.FCI n1415 FCITOFCO_D --- 0.317 R2C7A.FCI to R2C7A.FCO SLICE_0 ROUTE 1 0.000 R2C7A.FCO to R2C7B.FCI n1416 FCITOFCO_D --- 0.317 R2C7B.FCI to R2C7B.FCO SLICE_86 ROUTE 1 0.000 R2C7B.FCO to R2C7C.FCI n1417 FCITOFCO_D --- 0.317 R2C7C.FCI to R2C7C.FCO SLICE_85 ROUTE 1 0.000 R2C7C.FCO to R2C7D.FCI n1418 FCITOFCO_D --- 0.317 R2C7D.FCI to R2C7D.FCO SLICE_73 ROUTE 1 0.000 R2C7D.FCO to R2C8A.FCI n1419 FCITOF1_DE --- 1.298 R2C8A.FCI to R2C8A.F1 SLICE_72 ROUTE 1 0.000 R2C8A.F1 to R2C8A.DI1 n117_adj_45 (to CLK180_OUT) -------- 9.033 (83.4% logic, 16.6% route), 14 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_58: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C5A.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_72: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C8A.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 73.916ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i1 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i24 (to CLK180_OUT +) Delay: 8.985ns (83.3% logic, 16.7% route), 13 logic levels. Constraint Details: 8.985ns physical path delay SLICE_19 to SLICE_72 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 73.916ns Physical Path Details: Data path SLICE_19 to SLICE_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R2C5B.CLK to R2C5B.Q0 SLICE_19 (from CLK180_OUT) ROUTE 1 1.498 R2C5B.Q0 to R2C5B.A0 n26_adj_3 C0TOFCO_DE --- 2.064 R2C5B.A0 to R2C5B.FCO SLICE_19 ROUTE 1 0.000 R2C5B.FCO to R2C5C.FCI n1409 FCITOFCO_D --- 0.317 R2C5C.FCI to R2C5C.FCO SLICE_18 ROUTE 1 0.000 R2C5C.FCO to R2C5D.FCI n1410 FCITOFCO_D --- 0.317 R2C5D.FCI to R2C5D.FCO SLICE_14 ROUTE 1 0.000 R2C5D.FCO to R2C6A.FCI n1411 FCITOFCO_D --- 0.317 R2C6A.FCI to R2C6A.FCO SLICE_11 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1412 FCITOFCO_D --- 0.317 R2C6B.FCI to R2C6B.FCO SLICE_10 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1413 FCITOFCO_D --- 0.317 R2C6C.FCI to R2C6C.FCO SLICE_5 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1414 FCITOFCO_D --- 0.317 R2C6D.FCI to R2C6D.FCO SLICE_4 ROUTE 1 0.000 R2C6D.FCO to R2C7A.FCI n1415 FCITOFCO_D --- 0.317 R2C7A.FCI to R2C7A.FCO SLICE_0 ROUTE 1 0.000 R2C7A.FCO to R2C7B.FCI n1416 FCITOFCO_D --- 0.317 R2C7B.FCI to R2C7B.FCO SLICE_86 ROUTE 1 0.000 R2C7B.FCO to R2C7C.FCI n1417 FCITOFCO_D --- 0.317 R2C7C.FCI to R2C7C.FCO SLICE_85 ROUTE 1 0.000 R2C7C.FCO to R2C7D.FCI n1418 FCITOFCO_D --- 0.317 R2C7D.FCI to R2C7D.FCO SLICE_73 ROUTE 1 0.000 R2C7D.FCO to R2C8A.FCI n1419 FCITOF1_DE --- 1.298 R2C8A.FCI to R2C8A.F1 SLICE_72 ROUTE 1 0.000 R2C8A.F1 to R2C8A.DI1 n117_adj_45 (to CLK180_OUT) -------- 8.985 (83.3% logic, 16.7% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C5B.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_72: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C8A.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 73.985ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i0 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i23 (to CLK180_OUT +) Delay: 8.916ns (83.2% logic, 16.8% route), 14 logic levels. Constraint Details: 8.916ns physical path delay SLICE_58 to SLICE_72 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 73.985ns Physical Path Details: Data path SLICE_58 to SLICE_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R2C5A.CLK to R2C5A.Q1 SLICE_58 (from CLK180_OUT) ROUTE 1 1.498 R2C5A.Q1 to R2C5A.A1 n27_adj_2 C1TOFCO_DE --- 1.795 R2C5A.A1 to R2C5A.FCO SLICE_58 ROUTE 1 0.000 R2C5A.FCO to R2C5B.FCI n1408 FCITOFCO_D --- 0.317 R2C5B.FCI to R2C5B.FCO SLICE_19 ROUTE 1 0.000 R2C5B.FCO to R2C5C.FCI n1409 FCITOFCO_D --- 0.317 R2C5C.FCI to R2C5C.FCO SLICE_18 ROUTE 1 0.000 R2C5C.FCO to R2C5D.FCI n1410 FCITOFCO_D --- 0.317 R2C5D.FCI to R2C5D.FCO SLICE_14 ROUTE 1 0.000 R2C5D.FCO to R2C6A.FCI n1411 FCITOFCO_D --- 0.317 R2C6A.FCI to R2C6A.FCO SLICE_11 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1412 FCITOFCO_D --- 0.317 R2C6B.FCI to R2C6B.FCO SLICE_10 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1413 FCITOFCO_D --- 0.317 R2C6C.FCI to R2C6C.FCO SLICE_5 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1414 FCITOFCO_D --- 0.317 R2C6D.FCI to R2C6D.FCO SLICE_4 ROUTE 1 0.000 R2C6D.FCO to R2C7A.FCI n1415 FCITOFCO_D --- 0.317 R2C7A.FCI to R2C7A.FCO SLICE_0 ROUTE 1 0.000 R2C7A.FCO to R2C7B.FCI n1416 FCITOFCO_D --- 0.317 R2C7B.FCI to R2C7B.FCO SLICE_86 ROUTE 1 0.000 R2C7B.FCO to R2C7C.FCI n1417 FCITOFCO_D --- 0.317 R2C7C.FCI to R2C7C.FCO SLICE_85 ROUTE 1 0.000 R2C7C.FCO to R2C7D.FCI n1418 FCITOFCO_D --- 0.317 R2C7D.FCI to R2C7D.FCO SLICE_73 ROUTE 1 0.000 R2C7D.FCO to R2C8A.FCI n1419 FCITOF0_DE --- 1.181 R2C8A.FCI to R2C8A.F0 SLICE_72 ROUTE 1 0.000 R2C8A.F0 to R2C8A.DI0 n118_adj_44 (to CLK180_OUT) -------- 8.916 (83.2% logic, 16.8% route), 14 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_58: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C5A.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_72: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C8A.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.033ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i1 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i23 (to CLK180_OUT +) Delay: 8.868ns (83.1% logic, 16.9% route), 13 logic levels. Constraint Details: 8.868ns physical path delay SLICE_19 to SLICE_72 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.033ns Physical Path Details: Data path SLICE_19 to SLICE_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R2C5B.CLK to R2C5B.Q0 SLICE_19 (from CLK180_OUT) ROUTE 1 1.498 R2C5B.Q0 to R2C5B.A0 n26_adj_3 C0TOFCO_DE --- 2.064 R2C5B.A0 to R2C5B.FCO SLICE_19 ROUTE 1 0.000 R2C5B.FCO to R2C5C.FCI n1409 FCITOFCO_D --- 0.317 R2C5C.FCI to R2C5C.FCO SLICE_18 ROUTE 1 0.000 R2C5C.FCO to R2C5D.FCI n1410 FCITOFCO_D --- 0.317 R2C5D.FCI to R2C5D.FCO SLICE_14 ROUTE 1 0.000 R2C5D.FCO to R2C6A.FCI n1411 FCITOFCO_D --- 0.317 R2C6A.FCI to R2C6A.FCO SLICE_11 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1412 FCITOFCO_D --- 0.317 R2C6B.FCI to R2C6B.FCO SLICE_10 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1413 FCITOFCO_D --- 0.317 R2C6C.FCI to R2C6C.FCO SLICE_5 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1414 FCITOFCO_D --- 0.317 R2C6D.FCI to R2C6D.FCO SLICE_4 ROUTE 1 0.000 R2C6D.FCO to R2C7A.FCI n1415 FCITOFCO_D --- 0.317 R2C7A.FCI to R2C7A.FCO SLICE_0 ROUTE 1 0.000 R2C7A.FCO to R2C7B.FCI n1416 FCITOFCO_D --- 0.317 R2C7B.FCI to R2C7B.FCO SLICE_86 ROUTE 1 0.000 R2C7B.FCO to R2C7C.FCI n1417 FCITOFCO_D --- 0.317 R2C7C.FCI to R2C7C.FCO SLICE_85 ROUTE 1 0.000 R2C7C.FCO to R2C7D.FCI n1418 FCITOFCO_D --- 0.317 R2C7D.FCI to R2C7D.FCO SLICE_73 ROUTE 1 0.000 R2C7D.FCO to R2C8A.FCI n1419 FCITOF0_DE --- 1.181 R2C8A.FCI to R2C8A.F0 SLICE_72 ROUTE 1 0.000 R2C8A.F0 to R2C8A.DI0 n118_adj_44 (to CLK180_OUT) -------- 8.868 (83.1% logic, 16.9% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C5B.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_72: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C8A.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.185ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i2 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i24 (to CLK180_OUT +) Delay: 8.716ns (82.8% logic, 17.2% route), 13 logic levels. Constraint Details: 8.716ns physical path delay SLICE_19 to SLICE_72 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.185ns Physical Path Details: Data path SLICE_19 to SLICE_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R2C5B.CLK to R2C5B.Q1 SLICE_19 (from CLK180_OUT) ROUTE 1 1.498 R2C5B.Q1 to R2C5B.A1 n25_adj_4 C1TOFCO_DE --- 1.795 R2C5B.A1 to R2C5B.FCO SLICE_19 ROUTE 1 0.000 R2C5B.FCO to R2C5C.FCI n1409 FCITOFCO_D --- 0.317 R2C5C.FCI to R2C5C.FCO SLICE_18 ROUTE 1 0.000 R2C5C.FCO to R2C5D.FCI n1410 FCITOFCO_D --- 0.317 R2C5D.FCI to R2C5D.FCO SLICE_14 ROUTE 1 0.000 R2C5D.FCO to R2C6A.FCI n1411 FCITOFCO_D --- 0.317 R2C6A.FCI to R2C6A.FCO SLICE_11 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1412 FCITOFCO_D --- 0.317 R2C6B.FCI to R2C6B.FCO SLICE_10 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1413 FCITOFCO_D --- 0.317 R2C6C.FCI to R2C6C.FCO SLICE_5 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1414 FCITOFCO_D --- 0.317 R2C6D.FCI to R2C6D.FCO SLICE_4 ROUTE 1 0.000 R2C6D.FCO to R2C7A.FCI n1415 FCITOFCO_D --- 0.317 R2C7A.FCI to R2C7A.FCO SLICE_0 ROUTE 1 0.000 R2C7A.FCO to R2C7B.FCI n1416 FCITOFCO_D --- 0.317 R2C7B.FCI to R2C7B.FCO SLICE_86 ROUTE 1 0.000 R2C7B.FCO to R2C7C.FCI n1417 FCITOFCO_D --- 0.317 R2C7C.FCI to R2C7C.FCO SLICE_85 ROUTE 1 0.000 R2C7C.FCO to R2C7D.FCI n1418 FCITOFCO_D --- 0.317 R2C7D.FCI to R2C7D.FCO SLICE_73 ROUTE 1 0.000 R2C7D.FCO to R2C8A.FCI n1419 FCITOF1_DE --- 1.298 R2C8A.FCI to R2C8A.F1 SLICE_72 ROUTE 1 0.000 R2C8A.F1 to R2C8A.DI1 n117_adj_45 (to CLK180_OUT) -------- 8.716 (82.8% logic, 17.2% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C5B.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_72: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C8A.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.185ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i0 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i22 (to CLK180_OUT +) Delay: 8.716ns (82.8% logic, 17.2% route), 13 logic levels. Constraint Details: 8.716ns physical path delay SLICE_58 to SLICE_73 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.185ns Physical Path Details: Data path SLICE_58 to SLICE_73: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R2C5A.CLK to R2C5A.Q1 SLICE_58 (from CLK180_OUT) ROUTE 1 1.498 R2C5A.Q1 to R2C5A.A1 n27_adj_2 C1TOFCO_DE --- 1.795 R2C5A.A1 to R2C5A.FCO SLICE_58 ROUTE 1 0.000 R2C5A.FCO to R2C5B.FCI n1408 FCITOFCO_D --- 0.317 R2C5B.FCI to R2C5B.FCO SLICE_19 ROUTE 1 0.000 R2C5B.FCO to R2C5C.FCI n1409 FCITOFCO_D --- 0.317 R2C5C.FCI to R2C5C.FCO SLICE_18 ROUTE 1 0.000 R2C5C.FCO to R2C5D.FCI n1410 FCITOFCO_D --- 0.317 R2C5D.FCI to R2C5D.FCO SLICE_14 ROUTE 1 0.000 R2C5D.FCO to R2C6A.FCI n1411 FCITOFCO_D --- 0.317 R2C6A.FCI to R2C6A.FCO SLICE_11 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1412 FCITOFCO_D --- 0.317 R2C6B.FCI to R2C6B.FCO SLICE_10 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1413 FCITOFCO_D --- 0.317 R2C6C.FCI to R2C6C.FCO SLICE_5 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1414 FCITOFCO_D --- 0.317 R2C6D.FCI to R2C6D.FCO SLICE_4 ROUTE 1 0.000 R2C6D.FCO to R2C7A.FCI n1415 FCITOFCO_D --- 0.317 R2C7A.FCI to R2C7A.FCO SLICE_0 ROUTE 1 0.000 R2C7A.FCO to R2C7B.FCI n1416 FCITOFCO_D --- 0.317 R2C7B.FCI to R2C7B.FCO SLICE_86 ROUTE 1 0.000 R2C7B.FCO to R2C7C.FCI n1417 FCITOFCO_D --- 0.317 R2C7C.FCI to R2C7C.FCO SLICE_85 ROUTE 1 0.000 R2C7C.FCO to R2C7D.FCI n1418 FCITOF1_DE --- 1.298 R2C7D.FCI to R2C7D.F1 SLICE_73 ROUTE 1 0.000 R2C7D.F1 to R2C7D.DI1 n119_adj_43 (to CLK180_OUT) -------- 8.716 (82.8% logic, 17.2% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_58: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C5A.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_73: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C7D.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.233ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i3 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i24 (to CLK180_OUT +) Delay: 8.668ns (82.7% logic, 17.3% route), 12 logic levels. Constraint Details: 8.668ns physical path delay SLICE_18 to SLICE_72 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.233ns Physical Path Details: Data path SLICE_18 to SLICE_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R2C5C.CLK to R2C5C.Q0 SLICE_18 (from CLK180_OUT) ROUTE 1 1.498 R2C5C.Q0 to R2C5C.A0 n24_adj_5 C0TOFCO_DE --- 2.064 R2C5C.A0 to R2C5C.FCO SLICE_18 ROUTE 1 0.000 R2C5C.FCO to R2C5D.FCI n1410 FCITOFCO_D --- 0.317 R2C5D.FCI to R2C5D.FCO SLICE_14 ROUTE 1 0.000 R2C5D.FCO to R2C6A.FCI n1411 FCITOFCO_D --- 0.317 R2C6A.FCI to R2C6A.FCO SLICE_11 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1412 FCITOFCO_D --- 0.317 R2C6B.FCI to R2C6B.FCO SLICE_10 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1413 FCITOFCO_D --- 0.317 R2C6C.FCI to R2C6C.FCO SLICE_5 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1414 FCITOFCO_D --- 0.317 R2C6D.FCI to R2C6D.FCO SLICE_4 ROUTE 1 0.000 R2C6D.FCO to R2C7A.FCI n1415 FCITOFCO_D --- 0.317 R2C7A.FCI to R2C7A.FCO SLICE_0 ROUTE 1 0.000 R2C7A.FCO to R2C7B.FCI n1416 FCITOFCO_D --- 0.317 R2C7B.FCI to R2C7B.FCO SLICE_86 ROUTE 1 0.000 R2C7B.FCO to R2C7C.FCI n1417 FCITOFCO_D --- 0.317 R2C7C.FCI to R2C7C.FCO SLICE_85 ROUTE 1 0.000 R2C7C.FCO to R2C7D.FCI n1418 FCITOFCO_D --- 0.317 R2C7D.FCI to R2C7D.FCO SLICE_73 ROUTE 1 0.000 R2C7D.FCO to R2C8A.FCI n1419 FCITOF1_DE --- 1.298 R2C8A.FCI to R2C8A.F1 SLICE_72 ROUTE 1 0.000 R2C8A.F1 to R2C8A.DI1 n117_adj_45 (to CLK180_OUT) -------- 8.668 (82.7% logic, 17.3% route), 12 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C5C.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_72: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C8A.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.233ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i1 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i22 (to CLK180_OUT +) Delay: 8.668ns (82.7% logic, 17.3% route), 12 logic levels. Constraint Details: 8.668ns physical path delay SLICE_19 to SLICE_73 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.233ns Physical Path Details: Data path SLICE_19 to SLICE_73: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R2C5B.CLK to R2C5B.Q0 SLICE_19 (from CLK180_OUT) ROUTE 1 1.498 R2C5B.Q0 to R2C5B.A0 n26_adj_3 C0TOFCO_DE --- 2.064 R2C5B.A0 to R2C5B.FCO SLICE_19 ROUTE 1 0.000 R2C5B.FCO to R2C5C.FCI n1409 FCITOFCO_D --- 0.317 R2C5C.FCI to R2C5C.FCO SLICE_18 ROUTE 1 0.000 R2C5C.FCO to R2C5D.FCI n1410 FCITOFCO_D --- 0.317 R2C5D.FCI to R2C5D.FCO SLICE_14 ROUTE 1 0.000 R2C5D.FCO to R2C6A.FCI n1411 FCITOFCO_D --- 0.317 R2C6A.FCI to R2C6A.FCO SLICE_11 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1412 FCITOFCO_D --- 0.317 R2C6B.FCI to R2C6B.FCO SLICE_10 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1413 FCITOFCO_D --- 0.317 R2C6C.FCI to R2C6C.FCO SLICE_5 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1414 FCITOFCO_D --- 0.317 R2C6D.FCI to R2C6D.FCO SLICE_4 ROUTE 1 0.000 R2C6D.FCO to R2C7A.FCI n1415 FCITOFCO_D --- 0.317 R2C7A.FCI to R2C7A.FCO SLICE_0 ROUTE 1 0.000 R2C7A.FCO to R2C7B.FCI n1416 FCITOFCO_D --- 0.317 R2C7B.FCI to R2C7B.FCO SLICE_86 ROUTE 1 0.000 R2C7B.FCO to R2C7C.FCI n1417 FCITOFCO_D --- 0.317 R2C7C.FCI to R2C7C.FCO SLICE_85 ROUTE 1 0.000 R2C7C.FCO to R2C7D.FCI n1418 FCITOF1_DE --- 1.298 R2C7D.FCI to R2C7D.F1 SLICE_73 ROUTE 1 0.000 R2C7D.F1 to R2C7D.DI1 n119_adj_43 (to CLK180_OUT) -------- 8.668 (82.7% logic, 17.3% route), 12 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C5B.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_73: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C7D.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.302ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i2 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i23 (to CLK180_OUT +) Delay: 8.599ns (82.6% logic, 17.4% route), 13 logic levels. Constraint Details: 8.599ns physical path delay SLICE_19 to SLICE_72 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.302ns Physical Path Details: Data path SLICE_19 to SLICE_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R2C5B.CLK to R2C5B.Q1 SLICE_19 (from CLK180_OUT) ROUTE 1 1.498 R2C5B.Q1 to R2C5B.A1 n25_adj_4 C1TOFCO_DE --- 1.795 R2C5B.A1 to R2C5B.FCO SLICE_19 ROUTE 1 0.000 R2C5B.FCO to R2C5C.FCI n1409 FCITOFCO_D --- 0.317 R2C5C.FCI to R2C5C.FCO SLICE_18 ROUTE 1 0.000 R2C5C.FCO to R2C5D.FCI n1410 FCITOFCO_D --- 0.317 R2C5D.FCI to R2C5D.FCO SLICE_14 ROUTE 1 0.000 R2C5D.FCO to R2C6A.FCI n1411 FCITOFCO_D --- 0.317 R2C6A.FCI to R2C6A.FCO SLICE_11 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1412 FCITOFCO_D --- 0.317 R2C6B.FCI to R2C6B.FCO SLICE_10 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1413 FCITOFCO_D --- 0.317 R2C6C.FCI to R2C6C.FCO SLICE_5 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1414 FCITOFCO_D --- 0.317 R2C6D.FCI to R2C6D.FCO SLICE_4 ROUTE 1 0.000 R2C6D.FCO to R2C7A.FCI n1415 FCITOFCO_D --- 0.317 R2C7A.FCI to R2C7A.FCO SLICE_0 ROUTE 1 0.000 R2C7A.FCO to R2C7B.FCI n1416 FCITOFCO_D --- 0.317 R2C7B.FCI to R2C7B.FCO SLICE_86 ROUTE 1 0.000 R2C7B.FCO to R2C7C.FCI n1417 FCITOFCO_D --- 0.317 R2C7C.FCI to R2C7C.FCO SLICE_85 ROUTE 1 0.000 R2C7C.FCO to R2C7D.FCI n1418 FCITOFCO_D --- 0.317 R2C7D.FCI to R2C7D.FCO SLICE_73 ROUTE 1 0.000 R2C7D.FCO to R2C8A.FCI n1419 FCITOF0_DE --- 1.181 R2C8A.FCI to R2C8A.F0 SLICE_72 ROUTE 1 0.000 R2C8A.F0 to R2C8A.DI0 n118_adj_44 (to CLK180_OUT) -------- 8.599 (82.6% logic, 17.4% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C5B.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_72: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C8A.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.302ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i0 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i21 (to CLK180_OUT +) Delay: 8.599ns (82.6% logic, 17.4% route), 13 logic levels. Constraint Details: 8.599ns physical path delay SLICE_58 to SLICE_73 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.302ns Physical Path Details: Data path SLICE_58 to SLICE_73: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R2C5A.CLK to R2C5A.Q1 SLICE_58 (from CLK180_OUT) ROUTE 1 1.498 R2C5A.Q1 to R2C5A.A1 n27_adj_2 C1TOFCO_DE --- 1.795 R2C5A.A1 to R2C5A.FCO SLICE_58 ROUTE 1 0.000 R2C5A.FCO to R2C5B.FCI n1408 FCITOFCO_D --- 0.317 R2C5B.FCI to R2C5B.FCO SLICE_19 ROUTE 1 0.000 R2C5B.FCO to R2C5C.FCI n1409 FCITOFCO_D --- 0.317 R2C5C.FCI to R2C5C.FCO SLICE_18 ROUTE 1 0.000 R2C5C.FCO to R2C5D.FCI n1410 FCITOFCO_D --- 0.317 R2C5D.FCI to R2C5D.FCO SLICE_14 ROUTE 1 0.000 R2C5D.FCO to R2C6A.FCI n1411 FCITOFCO_D --- 0.317 R2C6A.FCI to R2C6A.FCO SLICE_11 ROUTE 1 0.000 R2C6A.FCO to R2C6B.FCI n1412 FCITOFCO_D --- 0.317 R2C6B.FCI to R2C6B.FCO SLICE_10 ROUTE 1 0.000 R2C6B.FCO to R2C6C.FCI n1413 FCITOFCO_D --- 0.317 R2C6C.FCI to R2C6C.FCO SLICE_5 ROUTE 1 0.000 R2C6C.FCO to R2C6D.FCI n1414 FCITOFCO_D --- 0.317 R2C6D.FCI to R2C6D.FCO SLICE_4 ROUTE 1 0.000 R2C6D.FCO to R2C7A.FCI n1415 FCITOFCO_D --- 0.317 R2C7A.FCI to R2C7A.FCO SLICE_0 ROUTE 1 0.000 R2C7A.FCO to R2C7B.FCI n1416 FCITOFCO_D --- 0.317 R2C7B.FCI to R2C7B.FCO SLICE_86 ROUTE 1 0.000 R2C7B.FCO to R2C7C.FCI n1417 FCITOFCO_D --- 0.317 R2C7C.FCI to R2C7C.FCO SLICE_85 ROUTE 1 0.000 R2C7C.FCO to R2C7D.FCI n1418 FCITOF0_DE --- 1.181 R2C7D.FCI to R2C7D.F0 SLICE_73 ROUTE 1 0.000 R2C7D.F0 to R2C7D.DI0 n120_adj_42 (to CLK180_OUT) -------- 8.599 (82.6% logic, 17.4% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_58: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C5A.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_73: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS2 to R2C7D.CLK CLK180_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Report: 105.652MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; 325 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 73.868ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i0 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i24 (to CLK270_OUT +) Delay: 9.033ns (83.4% logic, 16.6% route), 14 logic levels. Constraint Details: 9.033ns physical path delay SLICE_60 to SLICE_64 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 73.868ns Physical Path Details: Data path SLICE_60 to SLICE_64: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C4A.CLK to R4C4A.Q1 SLICE_60 (from CLK270_OUT) ROUTE 1 1.498 R4C4A.Q1 to R4C4A.A1 n1611 C1TOFCO_DE --- 1.795 R4C4A.A1 to R4C4A.FCO SLICE_60 ROUTE 1 0.000 R4C4A.FCO to R4C4B.FCI n1394 FCITOFCO_D --- 0.317 R4C4B.FCI to R4C4B.FCO SLICE_56 ROUTE 1 0.000 R4C4B.FCO to R4C4C.FCI n1395 FCITOFCO_D --- 0.317 R4C4C.FCI to R4C4C.FCO SLICE_22 ROUTE 1 0.000 R4C4C.FCO to R4C4D.FCI n1396 FCITOFCO_D --- 0.317 R4C4D.FCI to R4C4D.FCO SLICE_21 ROUTE 1 0.000 R4C4D.FCO to R4C5A.FCI n1397 FCITOFCO_D --- 0.317 R4C5A.FCI to R4C5A.FCO SLICE_13 ROUTE 1 0.000 R4C5A.FCO to R4C5B.FCI n1398 FCITOFCO_D --- 0.317 R4C5B.FCI to R4C5B.FCO SLICE_9 ROUTE 1 0.000 R4C5B.FCO to R4C5C.FCI n1399 FCITOFCO_D --- 0.317 R4C5C.FCI to R4C5C.FCO SLICE_8 ROUTE 1 0.000 R4C5C.FCO to R4C5D.FCI n1400 FCITOFCO_D --- 0.317 R4C5D.FCI to R4C5D.FCO SLICE_84 ROUTE 1 0.000 R4C5D.FCO to R4C6A.FCI n1401 FCITOFCO_D --- 0.317 R4C6A.FCI to R4C6A.FCO SLICE_74 ROUTE 1 0.000 R4C6A.FCO to R4C6B.FCI n1402 FCITOFCO_D --- 0.317 R4C6B.FCI to R4C6B.FCO SLICE_69 ROUTE 1 0.000 R4C6B.FCO to R4C6C.FCI n1403 FCITOFCO_D --- 0.317 R4C6C.FCI to R4C6C.FCO SLICE_67 ROUTE 1 0.000 R4C6C.FCO to R4C6D.FCI n1404 FCITOFCO_D --- 0.317 R4C6D.FCI to R4C6D.FCO SLICE_65 ROUTE 1 0.000 R4C6D.FCO to R4C7A.FCI n1405 FCITOF1_DE --- 1.298 R4C7A.FCI to R4C7A.F1 SLICE_64 ROUTE 1 0.000 R4C7A.F1 to R4C7A.DI1 n117 (to CLK270_OUT) -------- 9.033 (83.4% logic, 16.6% route), 14 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_60: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C4A.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_64: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C7A.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 73.916ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i1 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i24 (to CLK270_OUT +) Delay: 8.985ns (83.3% logic, 16.7% route), 13 logic levels. Constraint Details: 8.985ns physical path delay SLICE_56 to SLICE_64 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 73.916ns Physical Path Details: Data path SLICE_56 to SLICE_64: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C4B.CLK to R4C4B.Q0 SLICE_56 (from CLK270_OUT) ROUTE 1 1.498 R4C4B.Q0 to R4C4B.A0 n26 C0TOFCO_DE --- 2.064 R4C4B.A0 to R4C4B.FCO SLICE_56 ROUTE 1 0.000 R4C4B.FCO to R4C4C.FCI n1395 FCITOFCO_D --- 0.317 R4C4C.FCI to R4C4C.FCO SLICE_22 ROUTE 1 0.000 R4C4C.FCO to R4C4D.FCI n1396 FCITOFCO_D --- 0.317 R4C4D.FCI to R4C4D.FCO SLICE_21 ROUTE 1 0.000 R4C4D.FCO to R4C5A.FCI n1397 FCITOFCO_D --- 0.317 R4C5A.FCI to R4C5A.FCO SLICE_13 ROUTE 1 0.000 R4C5A.FCO to R4C5B.FCI n1398 FCITOFCO_D --- 0.317 R4C5B.FCI to R4C5B.FCO SLICE_9 ROUTE 1 0.000 R4C5B.FCO to R4C5C.FCI n1399 FCITOFCO_D --- 0.317 R4C5C.FCI to R4C5C.FCO SLICE_8 ROUTE 1 0.000 R4C5C.FCO to R4C5D.FCI n1400 FCITOFCO_D --- 0.317 R4C5D.FCI to R4C5D.FCO SLICE_84 ROUTE 1 0.000 R4C5D.FCO to R4C6A.FCI n1401 FCITOFCO_D --- 0.317 R4C6A.FCI to R4C6A.FCO SLICE_74 ROUTE 1 0.000 R4C6A.FCO to R4C6B.FCI n1402 FCITOFCO_D --- 0.317 R4C6B.FCI to R4C6B.FCO SLICE_69 ROUTE 1 0.000 R4C6B.FCO to R4C6C.FCI n1403 FCITOFCO_D --- 0.317 R4C6C.FCI to R4C6C.FCO SLICE_67 ROUTE 1 0.000 R4C6C.FCO to R4C6D.FCI n1404 FCITOFCO_D --- 0.317 R4C6D.FCI to R4C6D.FCO SLICE_65 ROUTE 1 0.000 R4C6D.FCO to R4C7A.FCI n1405 FCITOF1_DE --- 1.298 R4C7A.FCI to R4C7A.F1 SLICE_64 ROUTE 1 0.000 R4C7A.F1 to R4C7A.DI1 n117 (to CLK270_OUT) -------- 8.985 (83.3% logic, 16.7% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_56: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C4B.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_64: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C7A.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 73.985ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i0 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i23 (to CLK270_OUT +) Delay: 8.916ns (83.2% logic, 16.8% route), 14 logic levels. Constraint Details: 8.916ns physical path delay SLICE_60 to SLICE_64 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 73.985ns Physical Path Details: Data path SLICE_60 to SLICE_64: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C4A.CLK to R4C4A.Q1 SLICE_60 (from CLK270_OUT) ROUTE 1 1.498 R4C4A.Q1 to R4C4A.A1 n1611 C1TOFCO_DE --- 1.795 R4C4A.A1 to R4C4A.FCO SLICE_60 ROUTE 1 0.000 R4C4A.FCO to R4C4B.FCI n1394 FCITOFCO_D --- 0.317 R4C4B.FCI to R4C4B.FCO SLICE_56 ROUTE 1 0.000 R4C4B.FCO to R4C4C.FCI n1395 FCITOFCO_D --- 0.317 R4C4C.FCI to R4C4C.FCO SLICE_22 ROUTE 1 0.000 R4C4C.FCO to R4C4D.FCI n1396 FCITOFCO_D --- 0.317 R4C4D.FCI to R4C4D.FCO SLICE_21 ROUTE 1 0.000 R4C4D.FCO to R4C5A.FCI n1397 FCITOFCO_D --- 0.317 R4C5A.FCI to R4C5A.FCO SLICE_13 ROUTE 1 0.000 R4C5A.FCO to R4C5B.FCI n1398 FCITOFCO_D --- 0.317 R4C5B.FCI to R4C5B.FCO SLICE_9 ROUTE 1 0.000 R4C5B.FCO to R4C5C.FCI n1399 FCITOFCO_D --- 0.317 R4C5C.FCI to R4C5C.FCO SLICE_8 ROUTE 1 0.000 R4C5C.FCO to R4C5D.FCI n1400 FCITOFCO_D --- 0.317 R4C5D.FCI to R4C5D.FCO SLICE_84 ROUTE 1 0.000 R4C5D.FCO to R4C6A.FCI n1401 FCITOFCO_D --- 0.317 R4C6A.FCI to R4C6A.FCO SLICE_74 ROUTE 1 0.000 R4C6A.FCO to R4C6B.FCI n1402 FCITOFCO_D --- 0.317 R4C6B.FCI to R4C6B.FCO SLICE_69 ROUTE 1 0.000 R4C6B.FCO to R4C6C.FCI n1403 FCITOFCO_D --- 0.317 R4C6C.FCI to R4C6C.FCO SLICE_67 ROUTE 1 0.000 R4C6C.FCO to R4C6D.FCI n1404 FCITOFCO_D --- 0.317 R4C6D.FCI to R4C6D.FCO SLICE_65 ROUTE 1 0.000 R4C6D.FCO to R4C7A.FCI n1405 FCITOF0_DE --- 1.181 R4C7A.FCI to R4C7A.F0 SLICE_64 ROUTE 1 0.000 R4C7A.F0 to R4C7A.DI0 n118 (to CLK270_OUT) -------- 8.916 (83.2% logic, 16.8% route), 14 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_60: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C4A.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_64: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C7A.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.033ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i1 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i23 (to CLK270_OUT +) Delay: 8.868ns (83.1% logic, 16.9% route), 13 logic levels. Constraint Details: 8.868ns physical path delay SLICE_56 to SLICE_64 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.033ns Physical Path Details: Data path SLICE_56 to SLICE_64: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C4B.CLK to R4C4B.Q0 SLICE_56 (from CLK270_OUT) ROUTE 1 1.498 R4C4B.Q0 to R4C4B.A0 n26 C0TOFCO_DE --- 2.064 R4C4B.A0 to R4C4B.FCO SLICE_56 ROUTE 1 0.000 R4C4B.FCO to R4C4C.FCI n1395 FCITOFCO_D --- 0.317 R4C4C.FCI to R4C4C.FCO SLICE_22 ROUTE 1 0.000 R4C4C.FCO to R4C4D.FCI n1396 FCITOFCO_D --- 0.317 R4C4D.FCI to R4C4D.FCO SLICE_21 ROUTE 1 0.000 R4C4D.FCO to R4C5A.FCI n1397 FCITOFCO_D --- 0.317 R4C5A.FCI to R4C5A.FCO SLICE_13 ROUTE 1 0.000 R4C5A.FCO to R4C5B.FCI n1398 FCITOFCO_D --- 0.317 R4C5B.FCI to R4C5B.FCO SLICE_9 ROUTE 1 0.000 R4C5B.FCO to R4C5C.FCI n1399 FCITOFCO_D --- 0.317 R4C5C.FCI to R4C5C.FCO SLICE_8 ROUTE 1 0.000 R4C5C.FCO to R4C5D.FCI n1400 FCITOFCO_D --- 0.317 R4C5D.FCI to R4C5D.FCO SLICE_84 ROUTE 1 0.000 R4C5D.FCO to R4C6A.FCI n1401 FCITOFCO_D --- 0.317 R4C6A.FCI to R4C6A.FCO SLICE_74 ROUTE 1 0.000 R4C6A.FCO to R4C6B.FCI n1402 FCITOFCO_D --- 0.317 R4C6B.FCI to R4C6B.FCO SLICE_69 ROUTE 1 0.000 R4C6B.FCO to R4C6C.FCI n1403 FCITOFCO_D --- 0.317 R4C6C.FCI to R4C6C.FCO SLICE_67 ROUTE 1 0.000 R4C6C.FCO to R4C6D.FCI n1404 FCITOFCO_D --- 0.317 R4C6D.FCI to R4C6D.FCO SLICE_65 ROUTE 1 0.000 R4C6D.FCO to R4C7A.FCI n1405 FCITOF0_DE --- 1.181 R4C7A.FCI to R4C7A.F0 SLICE_64 ROUTE 1 0.000 R4C7A.F0 to R4C7A.DI0 n118 (to CLK270_OUT) -------- 8.868 (83.1% logic, 16.9% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_56: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C4B.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_64: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C7A.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.185ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i2 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i24 (to CLK270_OUT +) Delay: 8.716ns (82.8% logic, 17.2% route), 13 logic levels. Constraint Details: 8.716ns physical path delay SLICE_56 to SLICE_64 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.185ns Physical Path Details: Data path SLICE_56 to SLICE_64: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C4B.CLK to R4C4B.Q1 SLICE_56 (from CLK270_OUT) ROUTE 1 1.498 R4C4B.Q1 to R4C4B.A1 n25 C1TOFCO_DE --- 1.795 R4C4B.A1 to R4C4B.FCO SLICE_56 ROUTE 1 0.000 R4C4B.FCO to R4C4C.FCI n1395 FCITOFCO_D --- 0.317 R4C4C.FCI to R4C4C.FCO SLICE_22 ROUTE 1 0.000 R4C4C.FCO to R4C4D.FCI n1396 FCITOFCO_D --- 0.317 R4C4D.FCI to R4C4D.FCO SLICE_21 ROUTE 1 0.000 R4C4D.FCO to R4C5A.FCI n1397 FCITOFCO_D --- 0.317 R4C5A.FCI to R4C5A.FCO SLICE_13 ROUTE 1 0.000 R4C5A.FCO to R4C5B.FCI n1398 FCITOFCO_D --- 0.317 R4C5B.FCI to R4C5B.FCO SLICE_9 ROUTE 1 0.000 R4C5B.FCO to R4C5C.FCI n1399 FCITOFCO_D --- 0.317 R4C5C.FCI to R4C5C.FCO SLICE_8 ROUTE 1 0.000 R4C5C.FCO to R4C5D.FCI n1400 FCITOFCO_D --- 0.317 R4C5D.FCI to R4C5D.FCO SLICE_84 ROUTE 1 0.000 R4C5D.FCO to R4C6A.FCI n1401 FCITOFCO_D --- 0.317 R4C6A.FCI to R4C6A.FCO SLICE_74 ROUTE 1 0.000 R4C6A.FCO to R4C6B.FCI n1402 FCITOFCO_D --- 0.317 R4C6B.FCI to R4C6B.FCO SLICE_69 ROUTE 1 0.000 R4C6B.FCO to R4C6C.FCI n1403 FCITOFCO_D --- 0.317 R4C6C.FCI to R4C6C.FCO SLICE_67 ROUTE 1 0.000 R4C6C.FCO to R4C6D.FCI n1404 FCITOFCO_D --- 0.317 R4C6D.FCI to R4C6D.FCO SLICE_65 ROUTE 1 0.000 R4C6D.FCO to R4C7A.FCI n1405 FCITOF1_DE --- 1.298 R4C7A.FCI to R4C7A.F1 SLICE_64 ROUTE 1 0.000 R4C7A.F1 to R4C7A.DI1 n117 (to CLK270_OUT) -------- 8.716 (82.8% logic, 17.2% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_56: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C4B.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_64: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C7A.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.185ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i0 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i22 (to CLK270_OUT +) Delay: 8.716ns (82.8% logic, 17.2% route), 13 logic levels. Constraint Details: 8.716ns physical path delay SLICE_60 to SLICE_65 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.185ns Physical Path Details: Data path SLICE_60 to SLICE_65: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C4A.CLK to R4C4A.Q1 SLICE_60 (from CLK270_OUT) ROUTE 1 1.498 R4C4A.Q1 to R4C4A.A1 n1611 C1TOFCO_DE --- 1.795 R4C4A.A1 to R4C4A.FCO SLICE_60 ROUTE 1 0.000 R4C4A.FCO to R4C4B.FCI n1394 FCITOFCO_D --- 0.317 R4C4B.FCI to R4C4B.FCO SLICE_56 ROUTE 1 0.000 R4C4B.FCO to R4C4C.FCI n1395 FCITOFCO_D --- 0.317 R4C4C.FCI to R4C4C.FCO SLICE_22 ROUTE 1 0.000 R4C4C.FCO to R4C4D.FCI n1396 FCITOFCO_D --- 0.317 R4C4D.FCI to R4C4D.FCO SLICE_21 ROUTE 1 0.000 R4C4D.FCO to R4C5A.FCI n1397 FCITOFCO_D --- 0.317 R4C5A.FCI to R4C5A.FCO SLICE_13 ROUTE 1 0.000 R4C5A.FCO to R4C5B.FCI n1398 FCITOFCO_D --- 0.317 R4C5B.FCI to R4C5B.FCO SLICE_9 ROUTE 1 0.000 R4C5B.FCO to R4C5C.FCI n1399 FCITOFCO_D --- 0.317 R4C5C.FCI to R4C5C.FCO SLICE_8 ROUTE 1 0.000 R4C5C.FCO to R4C5D.FCI n1400 FCITOFCO_D --- 0.317 R4C5D.FCI to R4C5D.FCO SLICE_84 ROUTE 1 0.000 R4C5D.FCO to R4C6A.FCI n1401 FCITOFCO_D --- 0.317 R4C6A.FCI to R4C6A.FCO SLICE_74 ROUTE 1 0.000 R4C6A.FCO to R4C6B.FCI n1402 FCITOFCO_D --- 0.317 R4C6B.FCI to R4C6B.FCO SLICE_69 ROUTE 1 0.000 R4C6B.FCO to R4C6C.FCI n1403 FCITOFCO_D --- 0.317 R4C6C.FCI to R4C6C.FCO SLICE_67 ROUTE 1 0.000 R4C6C.FCO to R4C6D.FCI n1404 FCITOF1_DE --- 1.298 R4C6D.FCI to R4C6D.F1 SLICE_65 ROUTE 1 0.000 R4C6D.F1 to R4C6D.DI1 n119 (to CLK270_OUT) -------- 8.716 (82.8% logic, 17.2% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_60: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C4A.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_65: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C6D.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.233ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i3 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i24 (to CLK270_OUT +) Delay: 8.668ns (82.7% logic, 17.3% route), 12 logic levels. Constraint Details: 8.668ns physical path delay SLICE_22 to SLICE_64 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.233ns Physical Path Details: Data path SLICE_22 to SLICE_64: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C4C.CLK to R4C4C.Q0 SLICE_22 (from CLK270_OUT) ROUTE 1 1.498 R4C4C.Q0 to R4C4C.A0 n24 C0TOFCO_DE --- 2.064 R4C4C.A0 to R4C4C.FCO SLICE_22 ROUTE 1 0.000 R4C4C.FCO to R4C4D.FCI n1396 FCITOFCO_D --- 0.317 R4C4D.FCI to R4C4D.FCO SLICE_21 ROUTE 1 0.000 R4C4D.FCO to R4C5A.FCI n1397 FCITOFCO_D --- 0.317 R4C5A.FCI to R4C5A.FCO SLICE_13 ROUTE 1 0.000 R4C5A.FCO to R4C5B.FCI n1398 FCITOFCO_D --- 0.317 R4C5B.FCI to R4C5B.FCO SLICE_9 ROUTE 1 0.000 R4C5B.FCO to R4C5C.FCI n1399 FCITOFCO_D --- 0.317 R4C5C.FCI to R4C5C.FCO SLICE_8 ROUTE 1 0.000 R4C5C.FCO to R4C5D.FCI n1400 FCITOFCO_D --- 0.317 R4C5D.FCI to R4C5D.FCO SLICE_84 ROUTE 1 0.000 R4C5D.FCO to R4C6A.FCI n1401 FCITOFCO_D --- 0.317 R4C6A.FCI to R4C6A.FCO SLICE_74 ROUTE 1 0.000 R4C6A.FCO to R4C6B.FCI n1402 FCITOFCO_D --- 0.317 R4C6B.FCI to R4C6B.FCO SLICE_69 ROUTE 1 0.000 R4C6B.FCO to R4C6C.FCI n1403 FCITOFCO_D --- 0.317 R4C6C.FCI to R4C6C.FCO SLICE_67 ROUTE 1 0.000 R4C6C.FCO to R4C6D.FCI n1404 FCITOFCO_D --- 0.317 R4C6D.FCI to R4C6D.FCO SLICE_65 ROUTE 1 0.000 R4C6D.FCO to R4C7A.FCI n1405 FCITOF1_DE --- 1.298 R4C7A.FCI to R4C7A.F1 SLICE_64 ROUTE 1 0.000 R4C7A.F1 to R4C7A.DI1 n117 (to CLK270_OUT) -------- 8.668 (82.7% logic, 17.3% route), 12 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_22: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C4C.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_64: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C7A.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.233ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i1 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i22 (to CLK270_OUT +) Delay: 8.668ns (82.7% logic, 17.3% route), 12 logic levels. Constraint Details: 8.668ns physical path delay SLICE_56 to SLICE_65 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.233ns Physical Path Details: Data path SLICE_56 to SLICE_65: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C4B.CLK to R4C4B.Q0 SLICE_56 (from CLK270_OUT) ROUTE 1 1.498 R4C4B.Q0 to R4C4B.A0 n26 C0TOFCO_DE --- 2.064 R4C4B.A0 to R4C4B.FCO SLICE_56 ROUTE 1 0.000 R4C4B.FCO to R4C4C.FCI n1395 FCITOFCO_D --- 0.317 R4C4C.FCI to R4C4C.FCO SLICE_22 ROUTE 1 0.000 R4C4C.FCO to R4C4D.FCI n1396 FCITOFCO_D --- 0.317 R4C4D.FCI to R4C4D.FCO SLICE_21 ROUTE 1 0.000 R4C4D.FCO to R4C5A.FCI n1397 FCITOFCO_D --- 0.317 R4C5A.FCI to R4C5A.FCO SLICE_13 ROUTE 1 0.000 R4C5A.FCO to R4C5B.FCI n1398 FCITOFCO_D --- 0.317 R4C5B.FCI to R4C5B.FCO SLICE_9 ROUTE 1 0.000 R4C5B.FCO to R4C5C.FCI n1399 FCITOFCO_D --- 0.317 R4C5C.FCI to R4C5C.FCO SLICE_8 ROUTE 1 0.000 R4C5C.FCO to R4C5D.FCI n1400 FCITOFCO_D --- 0.317 R4C5D.FCI to R4C5D.FCO SLICE_84 ROUTE 1 0.000 R4C5D.FCO to R4C6A.FCI n1401 FCITOFCO_D --- 0.317 R4C6A.FCI to R4C6A.FCO SLICE_74 ROUTE 1 0.000 R4C6A.FCO to R4C6B.FCI n1402 FCITOFCO_D --- 0.317 R4C6B.FCI to R4C6B.FCO SLICE_69 ROUTE 1 0.000 R4C6B.FCO to R4C6C.FCI n1403 FCITOFCO_D --- 0.317 R4C6C.FCI to R4C6C.FCO SLICE_67 ROUTE 1 0.000 R4C6C.FCO to R4C6D.FCI n1404 FCITOF1_DE --- 1.298 R4C6D.FCI to R4C6D.F1 SLICE_65 ROUTE 1 0.000 R4C6D.F1 to R4C6D.DI1 n119 (to CLK270_OUT) -------- 8.668 (82.7% logic, 17.3% route), 12 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_56: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C4B.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_65: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C6D.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.302ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i2 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i23 (to CLK270_OUT +) Delay: 8.599ns (82.6% logic, 17.4% route), 13 logic levels. Constraint Details: 8.599ns physical path delay SLICE_56 to SLICE_64 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.302ns Physical Path Details: Data path SLICE_56 to SLICE_64: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C4B.CLK to R4C4B.Q1 SLICE_56 (from CLK270_OUT) ROUTE 1 1.498 R4C4B.Q1 to R4C4B.A1 n25 C1TOFCO_DE --- 1.795 R4C4B.A1 to R4C4B.FCO SLICE_56 ROUTE 1 0.000 R4C4B.FCO to R4C4C.FCI n1395 FCITOFCO_D --- 0.317 R4C4C.FCI to R4C4C.FCO SLICE_22 ROUTE 1 0.000 R4C4C.FCO to R4C4D.FCI n1396 FCITOFCO_D --- 0.317 R4C4D.FCI to R4C4D.FCO SLICE_21 ROUTE 1 0.000 R4C4D.FCO to R4C5A.FCI n1397 FCITOFCO_D --- 0.317 R4C5A.FCI to R4C5A.FCO SLICE_13 ROUTE 1 0.000 R4C5A.FCO to R4C5B.FCI n1398 FCITOFCO_D --- 0.317 R4C5B.FCI to R4C5B.FCO SLICE_9 ROUTE 1 0.000 R4C5B.FCO to R4C5C.FCI n1399 FCITOFCO_D --- 0.317 R4C5C.FCI to R4C5C.FCO SLICE_8 ROUTE 1 0.000 R4C5C.FCO to R4C5D.FCI n1400 FCITOFCO_D --- 0.317 R4C5D.FCI to R4C5D.FCO SLICE_84 ROUTE 1 0.000 R4C5D.FCO to R4C6A.FCI n1401 FCITOFCO_D --- 0.317 R4C6A.FCI to R4C6A.FCO SLICE_74 ROUTE 1 0.000 R4C6A.FCO to R4C6B.FCI n1402 FCITOFCO_D --- 0.317 R4C6B.FCI to R4C6B.FCO SLICE_69 ROUTE 1 0.000 R4C6B.FCO to R4C6C.FCI n1403 FCITOFCO_D --- 0.317 R4C6C.FCI to R4C6C.FCO SLICE_67 ROUTE 1 0.000 R4C6C.FCO to R4C6D.FCI n1404 FCITOFCO_D --- 0.317 R4C6D.FCI to R4C6D.FCO SLICE_65 ROUTE 1 0.000 R4C6D.FCO to R4C7A.FCI n1405 FCITOF0_DE --- 1.181 R4C7A.FCI to R4C7A.F0 SLICE_64 ROUTE 1 0.000 R4C7A.F0 to R4C7A.DI0 n118 (to CLK270_OUT) -------- 8.599 (82.6% logic, 17.4% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_56: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C4B.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_64: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C7A.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 74.302ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i0 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i21 (to CLK270_OUT +) Delay: 8.599ns (82.6% logic, 17.4% route), 13 logic levels. Constraint Details: 8.599ns physical path delay SLICE_60 to SLICE_65 meets 83.333ns delay constraint less 0.000ns skew and 0.432ns DIN_SET requirement (totaling 82.901ns) by 74.302ns Physical Path Details: Data path SLICE_60 to SLICE_65: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R4C4A.CLK to R4C4A.Q1 SLICE_60 (from CLK270_OUT) ROUTE 1 1.498 R4C4A.Q1 to R4C4A.A1 n1611 C1TOFCO_DE --- 1.795 R4C4A.A1 to R4C4A.FCO SLICE_60 ROUTE 1 0.000 R4C4A.FCO to R4C4B.FCI n1394 FCITOFCO_D --- 0.317 R4C4B.FCI to R4C4B.FCO SLICE_56 ROUTE 1 0.000 R4C4B.FCO to R4C4C.FCI n1395 FCITOFCO_D --- 0.317 R4C4C.FCI to R4C4C.FCO SLICE_22 ROUTE 1 0.000 R4C4C.FCO to R4C4D.FCI n1396 FCITOFCO_D --- 0.317 R4C4D.FCI to R4C4D.FCO SLICE_21 ROUTE 1 0.000 R4C4D.FCO to R4C5A.FCI n1397 FCITOFCO_D --- 0.317 R4C5A.FCI to R4C5A.FCO SLICE_13 ROUTE 1 0.000 R4C5A.FCO to R4C5B.FCI n1398 FCITOFCO_D --- 0.317 R4C5B.FCI to R4C5B.FCO SLICE_9 ROUTE 1 0.000 R4C5B.FCO to R4C5C.FCI n1399 FCITOFCO_D --- 0.317 R4C5C.FCI to R4C5C.FCO SLICE_8 ROUTE 1 0.000 R4C5C.FCO to R4C5D.FCI n1400 FCITOFCO_D --- 0.317 R4C5D.FCI to R4C5D.FCO SLICE_84 ROUTE 1 0.000 R4C5D.FCO to R4C6A.FCI n1401 FCITOFCO_D --- 0.317 R4C6A.FCI to R4C6A.FCO SLICE_74 ROUTE 1 0.000 R4C6A.FCO to R4C6B.FCI n1402 FCITOFCO_D --- 0.317 R4C6B.FCI to R4C6B.FCO SLICE_69 ROUTE 1 0.000 R4C6B.FCO to R4C6C.FCI n1403 FCITOFCO_D --- 0.317 R4C6C.FCI to R4C6C.FCO SLICE_67 ROUTE 1 0.000 R4C6C.FCO to R4C6D.FCI n1404 FCITOF0_DE --- 1.181 R4C6D.FCI to R4C6D.F0 SLICE_65 ROUTE 1 0.000 R4C6D.F0 to R4C6D.DI0 n120 (to CLK270_OUT) -------- 8.599 (82.6% logic, 17.4% route), 13 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_60: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C4A.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_65: Name Fanout Delay (ns) Site Resource ROUTE 13 3.680 LPLL.CLKOS3 to R4C6D.CLK CLK270_OUT -------- 3.680 (0.0% logic, 100.0% route), 0 logic levels. Report: 105.652MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY PORT "EXTOSC" 24.000000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 35.006ns The internal maximum frequency of the following component is 150.150 MHz Logical Details: Cell type Pin name Component name Destination: PIO PAD EXTOSC Delay: 6.660ns -- based on Minimum Pulse Width Report: 150.150MHz is the maximum frequency for this preference. ================================================================================ Preference: PERIOD PORT "TOP_TCK" 0.100000 nS ; 0 items scored, 1 timing error detected. Note: Component internal maximum frequency has been exceeded. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 6.560ns The internal maximum frequency of the following component is 150.150 MHz Logical Details: Cell type Pin name Component name Destination: PIO PAD TOP_TCK Delay: 6.660ns -- based on Minimum Pulse Width Warning: 6.660ns is the minimum period for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "CLK" 2.080000 MHz ; | 2.080 MHz| 31.636 MHz| 3 | | | FREQUENCY NET "CLK_IN0" 12.000000 MHz ; | 12.000 MHz| 105.652 MHz| 14 | | | FREQUENCY NET "CLK0_OUT" 12.000000 MHz | | | ; | 12.000 MHz| 105.652 MHz| 14 | | | FREQUENCY NET "CLK90_OUT" 12.000000 MHz | | | ; | 12.000 MHz| 105.652 MHz| 14 | | | FREQUENCY NET "CLK180_OUT" 12.000000 | | | MHz ; | 12.000 MHz| 105.652 MHz| 14 | | | FREQUENCY NET "CLK270_OUT" 12.000000 | | | MHz ; | 12.000 MHz| 105.652 MHz| 14 | | | FREQUENCY PORT "EXTOSC" 24.000000 MHz ; | 24.000 MHz| 150.150 MHz| 0 | | | PERIOD PORT "TOP_TCK" 0.100000 nS ; | 0.100 ns| 6.660 ns| 0 * | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. No net is responsible for more than 10% of the timing errors. Clock Domains Analysis ------------------------ Found 6 clocks: Clock Domain: CLK Source: osc_internal.OSC Loads: 55 Covered under: FREQUENCY NET "CLK" 2.080000 MHz ; Clock Domain: CLK_IN0 Source: clk_selector.DCMOUT Loads: 14 Covered under: FREQUENCY NET "CLK_IN0" 12.000000 MHz ; Clock Domain: CLK0_OUT Source: pll.CLKOP Loads: 14 Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; Clock Domain: CLK90_OUT Source: pll.CLKOS Loads: 13 Covered under: FREQUENCY NET "CLK90_OUT" 12.000000 MHz ; Clock Domain: CLK180_OUT Source: pll.CLKOS2 Loads: 13 Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; Clock Domain: CLK270_OUT Source: pll.CLKOS3 Loads: 13 Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Timing summary (Setup): --------------- Timing errors: 1 Score: 0 Cumulative negative slack: 6560 Note: Component internal maximum frequency has been exceeded. Constraints cover 2468 paths, 8 nets, and 839 connections (96.4% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond_1.4_Production (87) Sat Feb 25 15:47:56 2012 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 1 -sphld m -o MachXO2_Breakout_test_hdl_xo2.twr MachXO2_Breakout_test_hdl_xo2.ncd MachXO2_Breakout_test_hdl_xo2.prf Design file: machxo2_breakout_test_hdl_xo2.ncd Preference file: machxo2_breakout_test_hdl_xo2.prf Device,speed: LCMXO2-1200ZE,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "CLK" 2.080000 MHz (0 errors)
  • 843 items scored, 0 timing errors detected.
  • FREQUENCY NET "CLK_IN0" 12.000000 MHz (0 errors)
  • 325 items scored, 0 timing errors detected.
  • FREQUENCY NET "CLK0_OUT" 12.000000 MHz (0 errors)
  • 325 items scored, 0 timing errors detected.
  • FREQUENCY NET "CLK90_OUT" 12.000000 MHz (0 errors)
  • 325 items scored, 0 timing errors detected.
  • FREQUENCY NET "CLK180_OUT" 12.000000 MHz (0 errors)
  • 325 items scored, 0 timing errors detected.
  • FREQUENCY NET "CLK270_OUT" 12.000000 MHz (0 errors)
  • 325 items scored, 0 timing errors detected.
  • FREQUENCY PORT "EXTOSC" 24.000000 MHz (0 errors)
  • 0 items scored, 0 timing errors detected.
  • PERIOD PORT "TOP_TCK" 0.100000 nS (0 errors)
  • 0 items scored, 0 timing errors detected. WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. WARNING - trce: Output clock frequency on pin CLKOP of pll is 12.0 MHz, which with divider 16, requires internal VCO frequency to be 192.0 MHz ( 12.0 MHz x 16), outside VCO valid range [400, 800] MHz. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "CLK" 2.080000 MHz ; 843 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.685ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SPI_ECHO/r_spi_i0_i4 (from CLK -) Destination: FF Data in SPI_ECHO/r_spi_i0_i5 (to CLK -) Delay: 0.618ns (41.6% logic, 58.4% route), 1 logic levels. Constraint Details: 0.618ns physical path delay SLICE_118 to SLICE_118 meets -0.067ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.067ns) by 0.685ns Physical Path Details: Data path SLICE_118 to SLICE_118: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C14C.CLK to R5C14C.Q0 SLICE_118 (from CLK) ROUTE 1 0.361 R5C14C.Q0 to R5C14C.M1 SPI_ECHO/r_spi_4 (to CLK) -------- 0.618 (41.6% logic, 58.4% route), 1 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_118: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R5C14C.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to SLICE_118: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R5C14C.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.685ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SPI_ECHO/r_spi_i0_i6 (from CLK -) Destination: FF Data in SPI_ECHO/r_spi_i0_i7 (to CLK -) Delay: 0.618ns (41.6% logic, 58.4% route), 1 logic levels. Constraint Details: 0.618ns physical path delay SLICE_119 to SLICE_119 meets -0.067ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.067ns) by 0.685ns Physical Path Details: Data path SLICE_119 to SLICE_119: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C14B.CLK to R3C14B.Q0 SLICE_119 (from CLK) ROUTE 1 0.361 R3C14B.Q0 to R3C14B.M1 SPI_ECHO/r_spi_6 (to CLK) -------- 0.618 (41.6% logic, 58.4% route), 1 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_119: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R3C14B.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to SLICE_119: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R3C14B.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.690ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q r_cs2_prev_49 (from CLK +) Destination: FF Data in r_cs2_52 (to CLK +) Delay: 0.623ns (41.3% logic, 58.7% route), 1 logic levels. Constraint Details: 0.623ns physical path delay SLICE_123 to SLICE_121 meets -0.067ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.067ns) by 0.690ns Physical Path Details: Data path SLICE_123 to SLICE_121: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R2C8C.CLK to R2C8C.Q0 SLICE_123 (from CLK) ROUTE 2 0.366 R2C8C.Q0 to R2C8D.M0 r_cs2_prev (to CLK) -------- 0.623 (41.3% logic, 58.7% route), 1 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_123: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R2C8C.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to SLICE_121: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R2C8D.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.690ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q r_jtck_prev_47 (from CLK +) Destination: FF Data in ISP/r_jtck_50 (to CLK +) Delay: 0.623ns (41.3% logic, 58.7% route), 1 logic levels. Constraint Details: 0.623ns physical path delay SLICE_125 to SLICE_124 meets -0.067ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.067ns) by 0.690ns Physical Path Details: Data path SLICE_125 to SLICE_124: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C10D.CLK to R4C10D.Q0 SLICE_125 (from CLK) ROUTE 2 0.366 R4C10D.Q0 to R4C10C.M0 r_jtck_prev (to CLK) -------- 0.623 (41.3% logic, 58.7% route), 1 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_125: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R4C10D.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to SLICE_124: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R4C10C.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count_111__i23 (from CLK +) Destination: FF Data in clk_count_111__i23 (to CLK +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_25 to SLICE_25 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_25 to SLICE_25: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C14A.CLK to R5C14A.Q0 SLICE_25 (from CLK) ROUTE 1 0.366 R5C14A.Q0 to R5C14A.A0 n4_adj_201 CTOF_DEL --- 0.199 R5C14A.A0 to R5C14A.F0 SLICE_25 ROUTE 1 0.000 R5C14A.F0 to R5C14A.DI0 n118_adj_226 (to CLK) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_25: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R5C14A.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to SLICE_25: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R5C14A.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count_111__i22 (from CLK +) Destination: FF Data in clk_count_111__i22 (to CLK +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_26 to SLICE_26 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_26 to SLICE_26: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C13D.CLK to R5C13D.Q1 SLICE_26 (from CLK) ROUTE 1 0.366 R5C13D.Q1 to R5C13D.A1 n5_adj_202 CTOF_DEL --- 0.199 R5C13D.A1 to R5C13D.F1 SLICE_26 ROUTE 1 0.000 R5C13D.F1 to R5C13D.DI1 n119_adj_227 (to CLK) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R5C13D.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R5C13D.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count_111__i21 (from CLK +) Destination: FF Data in clk_count_111__i21 (to CLK +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_26 to SLICE_26 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_26 to SLICE_26: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C13D.CLK to R5C13D.Q0 SLICE_26 (from CLK) ROUTE 1 0.366 R5C13D.Q0 to R5C13D.A0 n6_adj_203 CTOF_DEL --- 0.199 R5C13D.A0 to R5C13D.F0 SLICE_26 ROUTE 1 0.000 R5C13D.F0 to R5C13D.DI0 n120_adj_228 (to CLK) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R5C13D.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R5C13D.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count_111__i19 (from CLK +) Destination: FF Data in clk_count_111__i19 (to CLK +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_27 to SLICE_27 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_27 to SLICE_27: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C13C.CLK to R5C13C.Q0 SLICE_27 (from CLK) ROUTE 1 0.366 R5C13C.Q0 to R5C13C.A0 n8_adj_205 CTOF_DEL --- 0.199 R5C13C.A0 to R5C13C.F0 SLICE_27 ROUTE 1 0.000 R5C13C.F0 to R5C13C.DI0 n122_adj_230 (to CLK) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_27: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R5C13C.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to SLICE_27: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R5C13C.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count_111__i20 (from CLK +) Destination: FF Data in clk_count_111__i20 (to CLK +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_27 to SLICE_27 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_27 to SLICE_27: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C13C.CLK to R5C13C.Q1 SLICE_27 (from CLK) ROUTE 1 0.366 R5C13C.Q1 to R5C13C.A1 n7_adj_204 CTOF_DEL --- 0.199 R5C13C.A1 to R5C13C.F1 SLICE_27 ROUTE 1 0.000 R5C13C.F1 to R5C13C.DI1 n121_adj_229 (to CLK) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_27: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R5C13C.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to SLICE_27: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R5C13C.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count_111__i17 (from CLK +) Destination: FF Data in clk_count_111__i17 (to CLK +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_28 to SLICE_28 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_28 to SLICE_28: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C13B.CLK to R5C13B.Q0 SLICE_28 (from CLK) ROUTE 1 0.366 R5C13B.Q0 to R5C13B.A0 n10_adj_207 CTOF_DEL --- 0.199 R5C13B.A0 to R5C13B.F0 SLICE_28 ROUTE 1 0.000 R5C13B.F0 to R5C13B.DI0 n124_adj_232 (to CLK) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path osc_internal to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R5C13B.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path osc_internal to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 55 2.474 OSC.OSC to R5C13B.CLK CLK -------- 2.474 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: FREQUENCY NET "CLK_IN0" 12.000000 MHz ; 325 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i23 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i23 (to CLK_IN0 +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_38 to SLICE_38 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_38 to SLICE_38: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C14A.CLK to R3C14A.Q0 SLICE_38 (from CLK_IN0) ROUTE 1 0.366 R3C14A.Q0 to R3C14A.A0 n4_adj_152 CTOF_DEL --- 0.199 R3C14A.A0 to R3C14A.F0 SLICE_38 ROUTE 1 0.000 R3C14A.F0 to R3C14A.DI0 n118_adj_177 (to CLK_IN0) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_38: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C14A.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_38: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C14A.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i21 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i21 (to CLK_IN0 +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_39 to SLICE_39 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_39 to SLICE_39: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C13D.CLK to R3C13D.Q0 SLICE_39 (from CLK_IN0) ROUTE 1 0.366 R3C13D.Q0 to R3C13D.A0 n6_adj_154 CTOF_DEL --- 0.199 R3C13D.A0 to R3C13D.F0 SLICE_39 ROUTE 1 0.000 R3C13D.F0 to R3C13D.DI0 n120_adj_179 (to CLK_IN0) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13D.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13D.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i22 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i22 (to CLK_IN0 +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_39 to SLICE_39 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_39 to SLICE_39: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C13D.CLK to R3C13D.Q1 SLICE_39 (from CLK_IN0) ROUTE 1 0.366 R3C13D.Q1 to R3C13D.A1 n5_adj_153 CTOF_DEL --- 0.199 R3C13D.A1 to R3C13D.F1 SLICE_39 ROUTE 1 0.000 R3C13D.F1 to R3C13D.DI1 n119_adj_178 (to CLK_IN0) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13D.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13D.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i20 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i20 (to CLK_IN0 +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_40 to SLICE_40 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_40 to SLICE_40: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C13C.CLK to R3C13C.Q1 SLICE_40 (from CLK_IN0) ROUTE 1 0.366 R3C13C.Q1 to R3C13C.A1 n7_adj_155 CTOF_DEL --- 0.199 R3C13C.A1 to R3C13C.F1 SLICE_40 ROUTE 1 0.000 R3C13C.F1 to R3C13C.DI1 n121_adj_180 (to CLK_IN0) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_40: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13C.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_40: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13C.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i19 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i19 (to CLK_IN0 +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_40 to SLICE_40 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_40 to SLICE_40: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C13C.CLK to R3C13C.Q0 SLICE_40 (from CLK_IN0) ROUTE 1 0.366 R3C13C.Q0 to R3C13C.A0 n8_adj_156 CTOF_DEL --- 0.199 R3C13C.A0 to R3C13C.F0 SLICE_40 ROUTE 1 0.000 R3C13C.F0 to R3C13C.DI0 n122_adj_181 (to CLK_IN0) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_40: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13C.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_40: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13C.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i18 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i18 (to CLK_IN0 +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_41 to SLICE_41 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_41 to SLICE_41: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C13B.CLK to R3C13B.Q1 SLICE_41 (from CLK_IN0) ROUTE 1 0.366 R3C13B.Q1 to R3C13B.A1 n9_adj_157 CTOF_DEL --- 0.199 R3C13B.A1 to R3C13B.F1 SLICE_41 ROUTE 1 0.000 R3C13B.F1 to R3C13B.DI1 n123_adj_182 (to CLK_IN0) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_41: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13B.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_41: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13B.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i17 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i17 (to CLK_IN0 +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_41 to SLICE_41 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_41 to SLICE_41: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C13B.CLK to R3C13B.Q0 SLICE_41 (from CLK_IN0) ROUTE 1 0.366 R3C13B.Q0 to R3C13B.A0 n10_adj_158 CTOF_DEL --- 0.199 R3C13B.A0 to R3C13B.F0 SLICE_41 ROUTE 1 0.000 R3C13B.F0 to R3C13B.DI0 n124_adj_183 (to CLK_IN0) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_41: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13B.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_41: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13B.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i15 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i15 (to CLK_IN0 +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_42 to SLICE_42 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_42 to SLICE_42: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C13A.CLK to R3C13A.Q0 SLICE_42 (from CLK_IN0) ROUTE 1 0.366 R3C13A.Q0 to R3C13A.A0 n12_adj_160 CTOF_DEL --- 0.199 R3C13A.A0 to R3C13A.F0 SLICE_42 ROUTE 1 0.000 R3C13A.F0 to R3C13A.DI0 n126_adj_185 (to CLK_IN0) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13A.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13A.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i16 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i16 (to CLK_IN0 +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_42 to SLICE_42 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_42 to SLICE_42: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C13A.CLK to R3C13A.Q1 SLICE_42 (from CLK_IN0) ROUTE 1 0.366 R3C13A.Q1 to R3C13A.A1 n11_adj_159 CTOF_DEL --- 0.199 R3C13A.A1 to R3C13A.F1 SLICE_42 ROUTE 1 0.000 R3C13A.F1 to R3C13A.DI1 n125_adj_184 (to CLK_IN0) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13A.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C13A.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count0_112__i14 (from CLK_IN0 +) Destination: FF Data in clk_count0_112__i14 (to CLK_IN0 +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_43 to SLICE_43 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_43 to SLICE_43: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C12D.CLK to R3C12D.Q1 SLICE_43 (from CLK_IN0) ROUTE 1 0.366 R3C12D.Q1 to R3C12D.A1 n13_adj_161 CTOF_DEL --- 0.199 R3C12D.A1 to R3C12D.F1 SLICE_43 ROUTE 1 0.000 R3C12D.F1 to R3C12D.DI1 n127_adj_186 (to CLK_IN0) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path clk_selector to SLICE_43: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C12D.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path clk_selector to SLICE_43: Name Fanout Delay (ns) Site Resource ROUTE 14 0.624 DCM6.DCMOUT to R3C12D.CLK CLK_IN0 -------- 0.624 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; 325 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i10 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i10 (to CLK0_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_1 to SLICE_1 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C12B.CLK to R4C12B.Q1 SLICE_1 (from CLK0_OUT) ROUTE 1 0.366 R4C12B.Q1 to R4C12B.A1 n17_adj_116 CTOF_DEL --- 0.199 R4C12B.A1 to R4C12B.F1 SLICE_1 ROUTE 1 0.000 R4C12B.F1 to R4C12B.DI1 n131_adj_141 (to CLK0_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C12B.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C12B.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i9 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i9 (to CLK0_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_1 to SLICE_1 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_1 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C12B.CLK to R4C12B.Q0 SLICE_1 (from CLK0_OUT) ROUTE 1 0.366 R4C12B.Q0 to R4C12B.A0 n18_adj_117 CTOF_DEL --- 0.199 R4C12B.A0 to R4C12B.F0 SLICE_1 ROUTE 1 0.000 R4C12B.F0 to R4C12B.DI0 n132_adj_142 (to CLK0_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C12B.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C12B.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i0 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i0 (to CLK0_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_12 to SLICE_12 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_12 to SLICE_12: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C11A.CLK to R4C11A.Q1 SLICE_12 (from CLK0_OUT) ROUTE 1 0.366 R4C11A.Q1 to R4C11A.A1 n27_adj_126 CTOF_DEL --- 0.199 R4C11A.A1 to R4C11A.F1 SLICE_12 ROUTE 1 0.000 R4C11A.F1 to R4C11A.DI1 n141_adj_151 (to CLK0_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C11A.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C11A.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i8 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i8 (to CLK0_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_2 to SLICE_2 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_2 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C12A.CLK to R4C12A.Q1 SLICE_2 (from CLK0_OUT) ROUTE 1 0.366 R4C12A.Q1 to R4C12A.A1 n19_adj_118 CTOF_DEL --- 0.199 R4C12A.A1 to R4C12A.F1 SLICE_2 ROUTE 1 0.000 R4C12A.F1 to R4C12A.DI1 n133_adj_143 (to CLK0_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C12A.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C12A.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i7 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i7 (to CLK0_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_2 to SLICE_2 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_2 to SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C12A.CLK to R4C12A.Q0 SLICE_2 (from CLK0_OUT) ROUTE 1 0.366 R4C12A.Q0 to R4C12A.A0 n20_adj_119 CTOF_DEL --- 0.199 R4C12A.A0 to R4C12A.F0 SLICE_2 ROUTE 1 0.000 R4C12A.F0 to R4C12A.DI0 n134_adj_144 (to CLK0_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C12A.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C12A.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i5 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i5 (to CLK0_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_3 to SLICE_3 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C11D.CLK to R4C11D.Q0 SLICE_3 (from CLK0_OUT) ROUTE 1 0.366 R4C11D.Q0 to R4C11D.A0 n22_adj_121 CTOF_DEL --- 0.199 R4C11D.A0 to R4C11D.F0 SLICE_3 ROUTE 1 0.000 R4C11D.F0 to R4C11D.DI0 n136_adj_146 (to CLK0_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C11D.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C11D.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i6 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i6 (to CLK0_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_3 to SLICE_3 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_3 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C11D.CLK to R4C11D.Q1 SLICE_3 (from CLK0_OUT) ROUTE 1 0.366 R4C11D.Q1 to R4C11D.A1 n21_adj_120 CTOF_DEL --- 0.199 R4C11D.A1 to R4C11D.F1 SLICE_3 ROUTE 1 0.000 R4C11D.F1 to R4C11D.DI1 n135_adj_145 (to CLK0_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C11D.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C11D.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i23 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i23 (to CLK0_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_51 to SLICE_51 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_51 to SLICE_51: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C14A.CLK to R4C14A.Q0 SLICE_51 (from CLK0_OUT) ROUTE 1 0.366 R4C14A.Q0 to R4C14A.A0 n4_adj_103 CTOF_DEL --- 0.199 R4C14A.A0 to R4C14A.F0 SLICE_51 ROUTE 1 0.000 R4C14A.F0 to R4C14A.DI0 n118_adj_128 (to CLK0_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_51: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C14A.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_51: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C14A.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i21 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i21 (to CLK0_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_52 to SLICE_52 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_52 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C13D.CLK to R4C13D.Q0 SLICE_52 (from CLK0_OUT) ROUTE 1 0.366 R4C13D.Q0 to R4C13D.A0 n6_adj_105 CTOF_DEL --- 0.199 R4C13D.A0 to R4C13D.F0 SLICE_52 ROUTE 1 0.000 R4C13D.F0 to R4C13D.DI0 n120_adj_130 (to CLK0_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_52: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C13D.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_52: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C13D.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count1_113__i22 (from CLK0_OUT +) Destination: FF Data in clk_count1_113__i22 (to CLK0_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_52 to SLICE_52 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_52 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C13D.CLK to R4C13D.Q1 SLICE_52 (from CLK0_OUT) ROUTE 1 0.366 R4C13D.Q1 to R4C13D.A1 n5_adj_104 CTOF_DEL --- 0.199 R4C13D.A1 to R4C13D.F1 SLICE_52 ROUTE 1 0.000 R4C13D.F1 to R4C13D.DI1 n119_adj_129 (to CLK0_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_52: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C13D.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_52: Name Fanout Delay (ns) Site Resource ROUTE 14 1.077 LPLL.CLKOP to R4C13D.CLK CLK0_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: FREQUENCY NET "CLK90_OUT" 12.000000 MHz ; 325 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i23 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i23 (to CLK90_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_15 to SLICE_15 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_15 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C8A.CLK to R3C8A.Q0 SLICE_15 (from CLK90_OUT) ROUTE 1 0.366 R3C8A.Q0 to R3C8A.A0 n4_adj_54 CTOF_DEL --- 0.199 R3C8A.A0 to R3C8A.F0 SLICE_15 ROUTE 1 0.000 R3C8A.F0 to R3C8A.DI0 n118_adj_79 (to CLK90_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C8A.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C8A.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i21 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i21 (to CLK90_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_16 to SLICE_16 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_16 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C7D.CLK to R3C7D.Q0 SLICE_16 (from CLK90_OUT) ROUTE 1 0.366 R3C7D.Q0 to R3C7D.A0 n6_adj_56 CTOF_DEL --- 0.199 R3C7D.A0 to R3C7D.F0 SLICE_16 ROUTE 1 0.000 R3C7D.F0 to R3C7D.DI0 n120_adj_81 (to CLK90_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7D.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7D.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i22 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i22 (to CLK90_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_16 to SLICE_16 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_16 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C7D.CLK to R3C7D.Q1 SLICE_16 (from CLK90_OUT) ROUTE 1 0.366 R3C7D.Q1 to R3C7D.A1 n5_adj_55 CTOF_DEL --- 0.199 R3C7D.A1 to R3C7D.F1 SLICE_16 ROUTE 1 0.000 R3C7D.F1 to R3C7D.DI1 n119_adj_80 (to CLK90_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7D.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7D.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i20 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i20 (to CLK90_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_17 to SLICE_17 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_17 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C7C.CLK to R3C7C.Q1 SLICE_17 (from CLK90_OUT) ROUTE 1 0.366 R3C7C.Q1 to R3C7C.A1 n7_adj_57 CTOF_DEL --- 0.199 R3C7C.A1 to R3C7C.F1 SLICE_17 ROUTE 1 0.000 R3C7C.F1 to R3C7C.DI1 n121_adj_82 (to CLK90_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7C.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7C.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i19 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i19 (to CLK90_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_17 to SLICE_17 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_17 to SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C7C.CLK to R3C7C.Q0 SLICE_17 (from CLK90_OUT) ROUTE 1 0.366 R3C7C.Q0 to R3C7C.A0 n8_adj_58 CTOF_DEL --- 0.199 R3C7C.A0 to R3C7C.F0 SLICE_17 ROUTE 1 0.000 R3C7C.F0 to R3C7C.DI0 n122_adj_83 (to CLK90_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7C.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7C.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i18 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i18 (to CLK90_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_20 to SLICE_20 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_20 to SLICE_20: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C7B.CLK to R3C7B.Q1 SLICE_20 (from CLK90_OUT) ROUTE 1 0.366 R3C7B.Q1 to R3C7B.A1 n9_adj_59 CTOF_DEL --- 0.199 R3C7B.A1 to R3C7B.F1 SLICE_20 ROUTE 1 0.000 R3C7B.F1 to R3C7B.DI1 n123_adj_84 (to CLK90_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_20: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7B.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_20: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7B.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i17 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i17 (to CLK90_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_20 to SLICE_20 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_20 to SLICE_20: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C7B.CLK to R3C7B.Q0 SLICE_20 (from CLK90_OUT) ROUTE 1 0.366 R3C7B.Q0 to R3C7B.A0 n10_adj_60 CTOF_DEL --- 0.199 R3C7B.A0 to R3C7B.F0 SLICE_20 ROUTE 1 0.000 R3C7B.F0 to R3C7B.DI0 n124_adj_85 (to CLK90_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_20: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7B.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_20: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7B.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i15 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i15 (to CLK90_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_23 to SLICE_23 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_23 to SLICE_23: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C7A.CLK to R3C7A.Q0 SLICE_23 (from CLK90_OUT) ROUTE 1 0.366 R3C7A.Q0 to R3C7A.A0 n12_adj_62 CTOF_DEL --- 0.199 R3C7A.A0 to R3C7A.F0 SLICE_23 ROUTE 1 0.000 R3C7A.F0 to R3C7A.DI0 n126_adj_87 (to CLK90_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_23: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7A.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_23: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7A.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i16 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i16 (to CLK90_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_23 to SLICE_23 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_23 to SLICE_23: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C7A.CLK to R3C7A.Q1 SLICE_23 (from CLK90_OUT) ROUTE 1 0.366 R3C7A.Q1 to R3C7A.A1 n11_adj_61 CTOF_DEL --- 0.199 R3C7A.A1 to R3C7A.F1 SLICE_23 ROUTE 1 0.000 R3C7A.F1 to R3C7A.DI1 n125_adj_86 (to CLK90_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_23: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7A.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_23: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C7A.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count2_114__i14 (from CLK90_OUT +) Destination: FF Data in clk_count2_114__i14 (to CLK90_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_24 to SLICE_24 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_24 to SLICE_24: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R3C6D.CLK to R3C6D.Q1 SLICE_24 (from CLK90_OUT) ROUTE 1 0.366 R3C6D.Q1 to R3C6D.A1 n13_adj_63 CTOF_DEL --- 0.199 R3C6D.A1 to R3C6D.F1 SLICE_24 ROUTE 1 0.000 R3C6D.F1 to R3C6D.DI1 n127_adj_88 (to CLK90_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_24: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C6D.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_24: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS to R3C6D.CLK CLK90_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; 325 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i15 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i15 (to CLK180_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_0 to SLICE_0 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_0 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R2C7A.CLK to R2C7A.Q0 SLICE_0 (from CLK180_OUT) ROUTE 1 0.366 R2C7A.Q0 to R2C7A.A0 n12_adj_17 CTOF_DEL --- 0.199 R2C7A.A0 to R2C7A.F0 SLICE_0 ROUTE 1 0.000 R2C7A.F0 to R2C7A.DI0 n126_adj_36 (to CLK180_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C7A.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C7A.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i16 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i16 (to CLK180_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_0 to SLICE_0 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_0 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R2C7A.CLK to R2C7A.Q1 SLICE_0 (from CLK180_OUT) ROUTE 1 0.366 R2C7A.Q1 to R2C7A.A1 n11_adj_18 CTOF_DEL --- 0.199 R2C7A.A1 to R2C7A.F1 SLICE_0 ROUTE 1 0.000 R2C7A.F1 to R2C7A.DI1 n125_adj_37 (to CLK180_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C7A.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C7A.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i9 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i9 (to CLK180_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_10 to SLICE_10 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R2C6B.CLK to R2C6B.Q0 SLICE_10 (from CLK180_OUT) ROUTE 1 0.366 R2C6B.Q0 to R2C6B.A0 n18_adj_11 CTOF_DEL --- 0.199 R2C6B.A0 to R2C6B.F0 SLICE_10 ROUTE 1 0.000 R2C6B.F0 to R2C6B.DI0 n132_adj_30 (to CLK180_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C6B.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C6B.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i10 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i10 (to CLK180_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_10 to SLICE_10 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_10 to SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R2C6B.CLK to R2C6B.Q1 SLICE_10 (from CLK180_OUT) ROUTE 1 0.366 R2C6B.Q1 to R2C6B.A1 n17_adj_12 CTOF_DEL --- 0.199 R2C6B.A1 to R2C6B.F1 SLICE_10 ROUTE 1 0.000 R2C6B.F1 to R2C6B.DI1 n131_adj_31 (to CLK180_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C6B.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C6B.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i7 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i7 (to CLK180_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_11 to SLICE_11 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_11 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R2C6A.CLK to R2C6A.Q0 SLICE_11 (from CLK180_OUT) ROUTE 1 0.366 R2C6A.Q0 to R2C6A.A0 n20_adj_9 CTOF_DEL --- 0.199 R2C6A.A0 to R2C6A.F0 SLICE_11 ROUTE 1 0.000 R2C6A.F0 to R2C6A.DI0 n134_adj_28 (to CLK180_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C6A.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C6A.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i8 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i8 (to CLK180_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_11 to SLICE_11 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_11 to SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R2C6A.CLK to R2C6A.Q1 SLICE_11 (from CLK180_OUT) ROUTE 1 0.366 R2C6A.Q1 to R2C6A.A1 n19_adj_10 CTOF_DEL --- 0.199 R2C6A.A1 to R2C6A.F1 SLICE_11 ROUTE 1 0.000 R2C6A.F1 to R2C6A.DI1 n133_adj_29 (to CLK180_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C6A.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C6A.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i6 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i6 (to CLK180_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_14 to SLICE_14 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_14 to SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R2C5D.CLK to R2C5D.Q1 SLICE_14 (from CLK180_OUT) ROUTE 1 0.366 R2C5D.Q1 to R2C5D.A1 n21_adj_8 CTOF_DEL --- 0.199 R2C5D.A1 to R2C5D.F1 SLICE_14 ROUTE 1 0.000 R2C5D.F1 to R2C5D.DI1 n135_adj_27 (to CLK180_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C5D.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C5D.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i5 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i5 (to CLK180_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_14 to SLICE_14 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_14 to SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R2C5D.CLK to R2C5D.Q0 SLICE_14 (from CLK180_OUT) ROUTE 1 0.366 R2C5D.Q0 to R2C5D.A0 n22_adj_7 CTOF_DEL --- 0.199 R2C5D.A0 to R2C5D.F0 SLICE_14 ROUTE 1 0.000 R2C5D.F0 to R2C5D.DI0 n136 (to CLK180_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C5D.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C5D.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i3 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i3 (to CLK180_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_18 to SLICE_18 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_18 to SLICE_18: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R2C5C.CLK to R2C5C.Q0 SLICE_18 (from CLK180_OUT) ROUTE 1 0.366 R2C5C.Q0 to R2C5C.A0 n24_adj_5 CTOF_DEL --- 0.199 R2C5C.A0 to R2C5C.F0 SLICE_18 ROUTE 1 0.000 R2C5C.F0 to R2C5C.DI0 n138_adj_50 (to CLK180_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C5C.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C5C.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count3_115__i4 (from CLK180_OUT +) Destination: FF Data in clk_count3_115__i4 (to CLK180_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_18 to SLICE_18 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_18 to SLICE_18: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R2C5C.CLK to R2C5C.Q1 SLICE_18 (from CLK180_OUT) ROUTE 1 0.366 R2C5C.Q1 to R2C5C.A1 n23_adj_6 CTOF_DEL --- 0.199 R2C5C.A1 to R2C5C.F1 SLICE_18 ROUTE 1 0.000 R2C5C.F1 to R2C5C.DI1 n137_adj_49 (to CLK180_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C5C.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS2 to R2C5C.CLK CLK180_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; 325 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i7 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i7 (to CLK270_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_13 to SLICE_13 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_13 to SLICE_13: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C5A.CLK to R4C5A.Q0 SLICE_13 (from CLK270_OUT) ROUTE 1 0.366 R4C5A.Q0 to R4C5A.A0 n1609 CTOF_DEL --- 0.199 R4C5A.A0 to R4C5A.F0 SLICE_13 ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 n134 (to CLK270_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C5A.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C5A.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i8 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i8 (to CLK270_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_13 to SLICE_13 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_13 to SLICE_13: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C5A.CLK to R4C5A.Q1 SLICE_13 (from CLK270_OUT) ROUTE 1 0.366 R4C5A.Q1 to R4C5A.A1 n19 CTOF_DEL --- 0.199 R4C5A.A1 to R4C5A.F1 SLICE_13 ROUTE 1 0.000 R4C5A.F1 to R4C5A.DI1 n133 (to CLK270_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C5A.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C5A.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i6 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i6 (to CLK270_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_21 to SLICE_21 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_21 to SLICE_21: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C4D.CLK to R4C4D.Q1 SLICE_21 (from CLK270_OUT) ROUTE 1 0.366 R4C4D.Q1 to R4C4D.A1 n1602 CTOF_DEL --- 0.199 R4C4D.A1 to R4C4D.F1 SLICE_21 ROUTE 1 0.000 R4C4D.F1 to R4C4D.DI1 n135 (to CLK270_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_21: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C4D.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_21: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C4D.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i5 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i5 (to CLK270_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_21 to SLICE_21 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_21 to SLICE_21: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C4D.CLK to R4C4D.Q0 SLICE_21 (from CLK270_OUT) ROUTE 1 0.366 R4C4D.Q0 to R4C4D.A0 n1610 CTOF_DEL --- 0.199 R4C4D.A0 to R4C4D.F0 SLICE_21 ROUTE 1 0.000 R4C4D.F0 to R4C4D.DI0 n136_adj_26 (to CLK270_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_21: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C4D.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_21: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C4D.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i3 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i3 (to CLK270_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_22 to SLICE_22 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_22 to SLICE_22: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C4C.CLK to R4C4C.Q0 SLICE_22 (from CLK270_OUT) ROUTE 1 0.366 R4C4C.Q0 to R4C4C.A0 n24 CTOF_DEL --- 0.199 R4C4C.A0 to R4C4C.F0 SLICE_22 ROUTE 1 0.000 R4C4C.F0 to R4C4C.DI0 n138 (to CLK270_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_22: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C4C.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_22: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C4C.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i4 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i4 (to CLK270_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_22 to SLICE_22 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_22 to SLICE_22: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C4C.CLK to R4C4C.Q1 SLICE_22 (from CLK270_OUT) ROUTE 1 0.366 R4C4C.Q1 to R4C4C.A1 n1613 CTOF_DEL --- 0.199 R4C4C.A1 to R4C4C.F1 SLICE_22 ROUTE 1 0.000 R4C4C.F1 to R4C4C.DI1 n137 (to CLK270_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_22: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C4C.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_22: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C4C.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i2 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i2 (to CLK270_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_56 to SLICE_56 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_56 to SLICE_56: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C4B.CLK to R4C4B.Q1 SLICE_56 (from CLK270_OUT) ROUTE 1 0.366 R4C4B.Q1 to R4C4B.A1 n25 CTOF_DEL --- 0.199 R4C4B.A1 to R4C4B.F1 SLICE_56 ROUTE 1 0.000 R4C4B.F1 to R4C4B.DI1 n139 (to CLK270_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_56: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C4B.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_56: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C4B.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i1 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i1 (to CLK270_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_56 to SLICE_56 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_56 to SLICE_56: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C4B.CLK to R4C4B.Q0 SLICE_56 (from CLK270_OUT) ROUTE 1 0.366 R4C4B.Q0 to R4C4B.A0 n26 CTOF_DEL --- 0.199 R4C4B.A0 to R4C4B.F0 SLICE_56 ROUTE 1 0.000 R4C4B.F0 to R4C4B.DI0 n1604 (to CLK270_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_56: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C4B.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_56: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C4B.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i0 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i0 (to CLK270_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_60 to SLICE_60 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_60 to SLICE_60: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C4A.CLK to R4C4A.Q1 SLICE_60 (from CLK270_OUT) ROUTE 1 0.366 R4C4A.Q1 to R4C4A.A1 n1611 CTOF_DEL --- 0.199 R4C4A.A1 to R4C4A.F1 SLICE_60 ROUTE 1 0.000 R4C4A.F1 to R4C4A.DI1 n141 (to CLK270_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_60: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C4A.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_60: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C4A.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.854ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q clk_count4_116__i23 (from CLK270_OUT +) Destination: FF Data in clk_count4_116__i23 (to CLK270_OUT +) Delay: 0.822ns (55.5% logic, 44.5% route), 2 logic levels. Constraint Details: 0.822ns physical path delay SLICE_64 to SLICE_64 meets -0.032ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.032ns) by 0.854ns Physical Path Details: Data path SLICE_64 to SLICE_64: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C7A.CLK to R4C7A.Q0 SLICE_64 (from CLK270_OUT) ROUTE 1 0.366 R4C7A.Q0 to R4C7A.A0 n4 CTOF_DEL --- 0.199 R4C7A.A0 to R4C7A.F0 SLICE_64 ROUTE 1 0.000 R4C7A.F0 to R4C7A.DI0 n118 (to CLK270_OUT) -------- 0.822 (55.5% logic, 44.5% route), 2 logic levels. Clock Skew Details: Source Clock Path pll to SLICE_64: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C7A.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path pll to SLICE_64: Name Fanout Delay (ns) Site Resource ROUTE 13 1.077 LPLL.CLKOS3 to R4C7A.CLK CLK270_OUT -------- 1.077 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: FREQUENCY PORT "EXTOSC" 24.000000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: PERIOD PORT "TOP_TCK" 0.100000 nS ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "CLK" 2.080000 MHz ; | -| -| 1 | | | FREQUENCY NET "CLK_IN0" 12.000000 MHz ; | -| -| 2 | | | FREQUENCY NET "CLK0_OUT" 12.000000 MHz | | | ; | -| -| 2 | | | FREQUENCY NET "CLK90_OUT" 12.000000 MHz | | | ; | -| -| 2 | | | FREQUENCY NET "CLK180_OUT" 12.000000 | | | MHz ; | -| -| 2 | | | FREQUENCY NET "CLK270_OUT" 12.000000 | | | MHz ; | -| -| 2 | | | FREQUENCY PORT "EXTOSC" 24.000000 MHz ; | -| -| 0 | | | PERIOD PORT "TOP_TCK" 0.100000 nS ; | -| -| 0 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 6 clocks: Clock Domain: CLK Source: osc_internal.OSC Loads: 55 Covered under: FREQUENCY NET "CLK" 2.080000 MHz ; Clock Domain: CLK_IN0 Source: clk_selector.DCMOUT Loads: 14 Covered under: FREQUENCY NET "CLK_IN0" 12.000000 MHz ; Clock Domain: CLK0_OUT Source: pll.CLKOP Loads: 14 Covered under: FREQUENCY NET "CLK0_OUT" 12.000000 MHz ; Clock Domain: CLK90_OUT Source: pll.CLKOS Loads: 13 Covered under: FREQUENCY NET "CLK90_OUT" 12.000000 MHz ; Clock Domain: CLK180_OUT Source: pll.CLKOS2 Loads: 13 Covered under: FREQUENCY NET "CLK180_OUT" 12.000000 MHz ; Clock Domain: CLK270_OUT Source: pll.CLKOS3 Loads: 13 Covered under: FREQUENCY NET "CLK270_OUT" 12.000000 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 2468 paths, 8 nets, and 839 connections (96.4% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 1 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 6560 (6560+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------