Synthesis and Ngdbuild Report #Build: Synplify Pro F-2011.09L, Build 022R, Oct 19 2011 #install: Y:\Program_Files\lscc\diamond\1.4\synpbase #OS: Windows XP 5.1 #Hostname: K-SUZUKI-FQ1 $ Start of Compile #Thu Feb 23 17:36:14 2012 Synopsys Verilog Compiler, version comp560rcp1, Build 045R, built Oct 18 2011 @N|Running in 32-bit mode Copyright (C) 1994-2011 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. @I::"Y:\Program_Files\lscc\diamond\1.4\synpbase\lib\lucent\machxo.v" @I::"Y:\Program_Files\lscc\diamond\1.4\synpbase\lib\vlog\scemi_objects.v" @I::"Y:\Program_Files\lscc\diamond\1.4\synpbase\lib\vlog\hypermods.v" @I::"Y:\Program_Files\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr_xo\source\rtavr_defs.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr_xo\source\rtavr_common.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_alu.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_cpi.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s0_fetch.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_smp.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\isp_sample\isp.v" @I::"Z:\AVR_CORE\rtavr_diamond\rtavr_xo\source\xo2_isp.v" Verilog syntax check successful! Selecting top level module xo2_isp @N: CG364 :"Y:\Program_Files\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo.v":591:7:591:11|Synthesizing module JTAGD @N: CG364 :"Y:\Program_Files\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo.v":1372:7:1372:10|Synthesizing module OSCC @N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\isp_sample\isp.v":83:7:83:9|Synthesizing module isp @W: CG532 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\isp_sample\isp.v":215:4:215:10|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored @N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":67:7:67:18|Synthesizing module rtavr_gpr_16 @N: CL134 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":187:0:187:5|Found RAM gpr, depth=16, width=8 @N: CL134 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":187:0:187:5|Found RAM gpr, depth=16, width=8 @N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":43:7:43:22|Synthesizing module rtavr_ior_timer0 BASE_ADDR=6'b010101 Generated name = rtavr_ior_timer0_21 @W: CL279 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":213:2:213:7|Pruning register bits 9 to 6 of r_prescaler[9:0] @N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":37:7:37:18|Synthesizing module rtavr_ior_ps CPUID=32'b00000000000000000000000000000000 Generated name = rtavr_ior_ps_0s @W: CL189 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":403:4:403:9|Register bit r_sph[2] is always 0, optimizing ... @W: CL189 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":403:4:403:9|Register bit r_sph[3] is always 0, optimizing ... @W: CL189 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":403:4:403:9|Register bit r_sph[4] is always 0, optimizing ... @W: CL189 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":403:4:403:9|Register bit r_sph[5] is always 0, optimizing ... @W: CL189 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":403:4:403:9|Register bit r_sph[6] is always 0, optimizing ... @W: CL189 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":403:4:403:9|Register bit r_sph[7] is always 0, optimizing ... @W: CL279 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":403:4:403:9|Pruning register bits 7 to 2 of r_sph[7:0] @N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":80:7:80:19|Synthesizing module rtavr_ior_spi BASE_ADDR=6'b101110 Generated name = rtavr_ior_spi_46 @W: CL169 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Pruning register r_ps[6:0] @W: CL169 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Pruning register r_count_en @N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":66:7:66:21|Synthesizing module rtavr_ior_usart BASE_ADDR=6'b001110 Generated name = rtavr_ior_usart_14 @W: CL169 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Pruning register rx_parity @W: CL265 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Pruning bit 9 of tx_data[9:0] -- not in use ... @W: CL271 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Pruning bits 10 to 9 of rx_data[10:0] -- not in use ... @W: CL265 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Pruning bit 3 of tx_ps[3:0] -- not in use ... @W: CL265 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Pruning bit 3 of rx_ps[3:0] -- not in use ... @N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":51:7:51:20|Synthesizing module rtavr_ior_port BASE_ADDR=6'b011011 Generated name = rtavr_ior_port_27 @N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":47:7:47:15|Synthesizing module rtavr_ior CPUID=32'b00000000000000000000000000000000 Generated name = rtavr_ior_0s @N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":43:7:43:16|Synthesizing module rtavr_sram SIZE=32'b00000000000000000000010000000000 Generated name = rtavr_sram_1024s @N: CL134 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":104:4:104:9|Found RAM mem, depth=1024, width=8 @W: CL271 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":104:4:104:9|Pruning bits 12 to 10 of r_addrb[12:0] -- not in use ... @N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":60:7:60:15|Synthesizing module rtavr_rom SIZE=32'b00000000000000000000010000000000 Generated name = rtavr_rom_1024s @W: CG532 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":283:2:283:8|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored @N: CL134 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Found RAM rom, depth=1024, width=16 @W: CL271 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Pruning bits 11 to 10 of r_addrb[11:0] -- not in use ... @W: CL118 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":163:1:163:2|Latch generated from always block for signal r_doa[15:0]; possible missing assignment in an if or case statement. @N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s0_fetch.v":30:7:30:20|Synthesizing module rtavr_s0_fetch @N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v":42:7:42:21|Synthesizing module rtavr_s1_decode @W: CL169 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v":736:2:736:7|Pruning register r_wdr @N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_alu.v":40:7:40:15|Synthesizing module rtavr_alu @N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr.v":76:7:76:11|Synthesizing module rtavr @N: CG364 :"Z:\AVR_CORE\rtavr_diamond\rtavr_xo\source\xo2_isp.v":23:7:23:13|Synthesizing module xo2_isp @W: CL246 :"Z:\AVR_CORE\rtavr_diamond\rtavr_xo\source\xo2_isp.v":31:17:31:19|Input port bits 1 to 0 of LED[7:0] are unused @W: CL156 :"Z:\AVR_CORE\rtavr_diamond\rtavr_xo\source\xo2_isp.v":145:10:145:13|*Input JTDI to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible. @W: CL156 :"Z:\AVR_CORE\rtavr_diamond\rtavr_xo\source\xo2_isp.v":161:16:161:18|*Input PIN[23:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible. @W: CL246 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":66:15:66:19|Input port bits 11 to 10 of ADDRA[11:0] are unused @W: CL246 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":72:17:72:21|Input port bits 12 to 11 of ADDRB[12:0] are unused @W: CL159 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":69:10:69:12|Input OEA is unused @W: CL246 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_sram.v":49:15:49:19|Input port bits 12 to 10 of ADDRB[12:0] are unused @W: CL246 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":73:18:73:20|Input port bits 15 to 0 of PIN[23:0] are unused @W: CL157 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":71:18:71:20|*Output DDR has undriven bits -- simulation mismatch possible. @W: CL157 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|*Output PORT has undriven bits -- simulation mismatch possible. @W: CL159 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":62:10:62:15|Input WE_pin is unused @W: CL159 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":68:16:68:21|Input DI_pin is unused @W: CL138 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing register 'RXB8' because it is only assigned 0 or its original value. @W: CL138 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing register 'TXB8' because it is only assigned 0 or its original value. @W: CL189 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Register bit UPE is always 0, optimizing ... @W: CL189 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Register bit r_count_max_x[1] is always 0, optimizing ... @W: CL260 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Pruning register bit 1 of r_count_max_x[1:0] @W: CL159 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":76:10:76:17|Input WE_ubrrl is unused @W: CL159 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":77:10:77:17|Input WE_ubrrh is unused @W: CL159 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":78:10:78:17|Input WE_ucsrc is unused @W: CL159 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":97:10:97:15|Input XCK_IN is unused @W: CL159 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":98:10:98:16|Input XCK_DDR is unused @W: CL159 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":92:10:92:16|Input WE_spsr is unused @W: CL159 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":105:10:105:15|Input SS_DDR is unused @W: CL159 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":109:10:109:16|Input MISO_IN is unused @W: CL246 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ps.v":56:18:56:22|Input port bits 15 to 10 of SP_IN[15:0] are unused @W: CL159 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":55:10:55:17|Input WE_ocr0b is unused @W: CL159 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":56:10:56:17|Input WE_ocr0a is unused @W: CL159 :"Z:\AVR_CORE\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":59:10:59:18|Input WE_tccr0a is unused @END Premap Report (contents appended below) @N:"Z:\AVR_CORE\rtavr_diamond\rtavr_xo\synlog\MachXO_Breakout_rtavr_xo_premap.srr" Synopsys Lattice Technology Pre-mapping, Version maplat, Build 239R, Built Oct 19 2011 10:56:21 Copyright (C) 1994-2011, Synopsys Inc. All Rights Reserved Product Version F-2011.09L Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N: MF249 |Running in 32-bit mode. @N: MF257 |Gated clock conversion enabled @N: MF546 |Generated clock conversion enabled Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 50MB) Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 50MB) @W: FX474 |User specified initial value found in some of the sequential elements in the design. Applying an initial value to a register may not deliver the best synthesis results. For example, registers with initial values may be preserved and retiming/pipelining may not be performed. To improve synthesis results you may want to remove the register initialization from the RTL code @W: FX469 :|Found undriven nets tri0_inst ..., mapper will optimize them. @W: FX469 :|Found undriven nets tri1_inst ..., mapper will optimize them. @W: FX469 :|Found undriven nets tri2_inst ..., mapper will optimize them. @W: FX469 :|Found undriven nets tri3_inst ..., mapper will optimize them. @W: FX469 :|Found undriven nets tri4_inst ..., mapper will optimize them. @W: FX469 :|Found undriven nets tri5_inst ..., mapper will optimize them. @W: MT462 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":158:18:158:27|Net RTAVR.ROM.CLK_L appears to be an unidentified clock source. Assuming default frequency. syn_allowed_resources : blockrams=3 set on top level netlist xo2_isp Finished Pre Mapping Phase. (Time elapsed 0h:00m:01s; Memory used current: 76MB peak: 78MB) Pre Mapping successful! At Mapper Exit (Time elapsed 0h:00m:01s; Memory used current: 44MB peak: 78MB) Process took 0h:00m:04s realtime, 0h:00m:01s cputime # Thu Feb 23 17:36:30 2012 ###########################################################] Map & Optimize Report (contents appended below) @N:"Z:\AVR_CORE\rtavr_diamond\rtavr_xo\synlog\MachXO_Breakout_rtavr_xo_fpga_mapper.srr" Synopsys Lattice Technology Mapper, Version maplat, Build 239R, Built Oct 19 2011 10:56:21 Copyright (C) 1994-2011, Synopsys Inc. All Rights Reserved Product Version F-2011.09L Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N: MF249 |Running in 32-bit mode. @N: MF257 |Gated clock conversion enabled @N: MF546 |Generated clock conversion enabled Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N: MF203 |Set autoconstraint_io Starting Optimization and Mapping (Time elapsed 0h:00m:01s; Memory used current: 76MB peak: 78MB) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_1 on net PORT_1 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_2 on net PORT_2 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_3 on net PORT_3 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_4 on net PORT_4 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_5 on net PORT_5 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_6 on net PORT_6 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_7 on net PORT_7 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_8 on net PORT_8 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_9 on net PORT_9 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_10 on net PORT_10 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_11 on net PORT_11 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_12 on net PORT_12 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_13 on net PORT_13 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_14 on net PORT_14 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_15 on net PORT_15 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":72:18:72:21|Tristate driver PORT_16 on net PORT_16 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_1 on net DDR_1 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_2 on net DDR_2 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_3 on net DDR_3 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_4 on net DDR_4 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_5 on net DDR_5 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_6 on net DDR_6 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_7 on net DDR_7 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_8 on net DDR_8 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_9 on net DDR_9 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_10 on net DDR_10 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_11 on net DDR_11 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_12 on net DDR_12 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_13 on net DDR_13 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_14 on net DDR_14 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_15 on net DDR_15 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_ms.v":1139:50:1139:60|Tristate driver DDR_16 on net DDR_16 has its enable tied to GND (module rtavr_ior_0s) @W: MO111 :|Tristate driver DDR_t[0] on net DDR[0] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[1] on net DDR[1] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[2] on net DDR[2] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[3] on net DDR[3] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[4] on net DDR[4] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[5] on net DDR[5] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[6] on net DDR[6] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[7] on net DDR[7] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[8] on net DDR[8] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[9] on net DDR[9] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[10] on net DDR[10] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[11] on net DDR[11] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[12] on net DDR[12] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[13] on net DDR[13] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[14] on net DDR[14] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver DDR_t[15] on net DDR[15] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[0] on net PORT[0] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[1] on net PORT[1] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[2] on net PORT[2] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[3] on net PORT[3] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[4] on net PORT[4] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[5] on net PORT[5] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[6] on net PORT[6] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[7] on net PORT[7] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[8] on net PORT[8] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[9] on net PORT[9] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[10] on net PORT[10] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[11] on net PORT[11] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[12] on net PORT[12] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[13] on net PORT[13] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[14] on net PORT[14] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver PORT_t[15] on net PORT[15] has its enable tied to GND (module rtavr) @W: MO111 :|Tristate driver tri0_inst on net LED[7] has its enable tied to GND (module xo2_isp) @W: MO111 :|Tristate driver tri1_inst on net LED[6] has its enable tied to GND (module xo2_isp) @W: MO111 :|Tristate driver tri2_inst on net LED[5] has its enable tied to GND (module xo2_isp) @W: MO111 :|Tristate driver tri3_inst on net LED[4] has its enable tied to GND (module xo2_isp) @W: MO111 :|Tristate driver tri4_inst on net LED[3] has its enable tied to GND (module xo2_isp) @W: MO111 :|Tristate driver tri5_inst on net LED[2] has its enable tied to GND (module xo2_isp) @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Removing sequential instance i_spi.r_spi_mclk of view:PrimLib.sdffre(prim) in hierarchy view:work.rtavr_ior_0s(verilog) because there are no references to its outputs Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 76MB peak: 78MB) @N:"z:\avr_core\rtavr_diamond\rtavr-0.9.5\isp_sample\isp.v":165:4:165:9|Found counter in view:work.isp(verilog) inst r_pr[15:0] @N:"z:\avr_core\rtavr_diamond\rtavr-0.9.5\isp_sample\isp.v":165:4:165:9|Found counter in view:work.isp(verilog) inst r_count[3:0] @N: FX702 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Found startup values on ram instance ROM.rom[15:0] @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_00 = 03649090600E4740E0730E05F0BE700E25F026600C0600C0600C0600C0600C0600C0600C0600C060 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_01 = 0E06802E170EE6802E170E06802E170EE700E64909249092670C2680F603036490C0700E6700F603 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_02 = 0D0700E0680E0700D0700E06802E170E0700D01702E700E06802E170E0700D01702E700E06802E17 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_03 = 0EE680E0680EE680E0700D0700E0680E0700D0700E0680E0700D0700E0680E0700D0700E0680E070 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_04 = 02E700E0700E6680E0680EE680E8700D0740EE680E8700D0740EE680E8700D0740EE680E8700D074 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_05 = 02E700D01702E770D0700E6700E4680E4680E46802E170E0700D01702E700E06802E170E0700D017 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_06 = 05E1702E48000560AC26058520A4680E01702E710EC410B65B0E2490D01702E700D01702E770D017 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_07 = 090560AC560AC680E0700E07108241082410B65B0E0700E4730D0680AC5604C2C0A4520D0730E027 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_08 = 0D0680D0740D0680E8680E8680E8570AE570AE680E0710E0720AC560AC560D0700E6700E84809048 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_09 = 0121702E5B0B6490924A070410827E02E1709438082490FC1702E4A09048090480E070094680D068 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_0A = 00E4A026070941500E4A022070943C00E4A09048070410820902E170B65B09249094480903808249 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_0B = 0922705E1702E7A0060B0804002E1702E17094400820702E170944002E170942C00E4A01A0709407 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_0C = 0B65B09249094410F6030167B0944A094700922E070170C01702E4A0704A0704A0941702E4108249 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_0D = 0D0680924909441082680E07002E170944809041082680E04002E170D00501A700E04A0FC1302E17 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_0E = 04E2F0B65B0D06804020040280864308643040200402804028080480904804E2F02E1702E170B65B @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_0F = 0402802E1702E1709448090480904809048090480906804028080480904804E2F040280924909249 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_10 = 0FC1302E170402802E170B65B0D06809249094680402802E170402802E1702E17094680402802E17 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_11 = 04028080480904804E2F08241082410B65B0D06802E4A0FC1302E170402802E17082410824102E4A @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_12 = 02E1708241082410B65B0D0680E070040280E07002E1704028094480904809048090480904809068 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_13 = 09457094590BA4D0BC5D0E073094480901702E680E07002E170B65B0924909448090480906802E17 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_14 = 05E5B0B64A02E170F6200504A094780060B01E0701E070C07F026130947D0F84C0264A0FA7C09A13 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_15 = 02E1702E170F603040280F64A0944A0940F01E0F00E0F01E0F00E600FE1302613026400904809027 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_16 = 026170FA40090480902705E5B0B64A04E4A0947B094270944A0F4110D0680D07E0D01302E7D09413 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_17 = 01E0F0C07001A0D0941304E2704E4A0944A0947B0941304E2704E4A0944A0947A01E680D0680FC68 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_18 = 01E6002E1701A0D02E71080480904804E2F0B65B0941702E1702E4A0947B0940F01E0501A780060B @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_19 = 0941302E1702E1702E1702E170944A0944A0F64A01E0F01E0F00A0500A0D0F003006030160F01E0F @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_1A = 0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F000000CE4A @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_1B = 0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_1C = 0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_1D = 0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_1E = 0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_1.INITVAL_1F = 0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F0FE7F @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_00 = 1492D242021ECE4160A0021CD3BCD139F1F2221B0381D03C1F04021044230482504C270502905410 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_01 = 100F32FB6C31EF02FB6C100F42FB6C31ED0189DF39F1F21FD3228023C3B134B3D002B0148103B3B1 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_02 = 1EC61102F90C2801F860102EF2BB4C0C4811E95D29861102EC2BB4C0C4811E35D29861102EF2FB6C @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_03 = 31ED411ED631EE10C0801C861102E70C2801D460102EA0C0801DA61102F00C2801E660102F30C080 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_04 = 2C09010010000CA11ECC31ECB0C08F19C6031ECE0C08F1A26031ED10C08F1A86031ED10C08F1A860 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_05 = 2D88F1557D2D9801A2700D19230CD430CD330CC12E3601208418D712C090104CB2E360120811A171 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_06 = 2DD712C12F000801239A31C91100C7081712C19B115813FDED30B2F1457D2D88F14D7D2D98014D7D @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_07 = 25E9B114790D0C1120802E564369A3325813FDED160A032D8800000104933358E126821A0981037F @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_08 = 2C15F2B0802C55B1015D1035F10293104710C1010E1621218413E8E0FA6C288702CC903112F25F2F @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_09 = 30DF53C9DE39BCF3BF0810331301803EFE62108126181301F73CD0821F1F39FDF12080311622C75F @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_0A = 3110830D88211863110830D8821080311083BFCF10331301863EBE43BDCD39FDF211DF39E8126181 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_0B = 3039F31F95308312B348323803EFE62B34821181307883EFE6211833EFE6210803110830D8821186 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_0C = 3BDCD39FDF2113034393307E12958732C442834009F48013F73CD0811F0811F82211953093026391 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_0D = 0000039FDF21180322D10E0633EFE6211DF39F80322DB0E16D32F86231752C8702C15028F553EFE6 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_0E = 37FAF37DAD000000E0600A041379AB33589160A0120811A0CC371A9333893BFC72F3682AF463BDCD @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_0F = 0E0612F3682AF46211DF39F2F25F2F25F2F25F2F25EAE1A0CC331892F3693BFC7160A42F96D2BB4D @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_10 = 2AF662B74A160A136FA63BDCD0000039FDF210791208132B840E0612F3682AF46210851208132B84 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_11 = 1A0C4331892F3693BFCF369A3325813FDED00000375A032FAA32B840A0412B3482F96B2B5492ED60 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_12 = 30D97369A3325813FDED00000160A0120810E0602AF460E061211DF39F2F25F2F25F2F25F2F25E5C @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_13 = 210342118F31FFF2815E0A144211DF39F9730C640A04026B243BDCD39FDF2112F25F2F25E3A2C975 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_14 = 3DBFE3DB0830595322901018732C292E7632EF662AF260058024555211813001E311083038003F88 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_15 = 2D57B31D9F2D37612080313672EF8732D5528933245F53C9B3344042C1AA377EE3FF5028331243FF @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_16 = 24B2932F5028331243FF3DBFE3DB0833F81321F62117F2C3700352200C3100977015272539721133 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_17 = 377AA00F51377AA2113333F8F2FF612E180321EE211332BF4F27F21261402A0382440B058042AE0F @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_18 = 3540D3F7EA377AA274A12A141263213FFED3FDED2119B315792D190301A92B599311B734C1036FA6 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_19 = 2113333F8E2F76A2B34826F26321802E1602D33A333882EF663EBE4367A2041F53C9B3345FF3DDBB @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_1A = 3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF000013FEF8 @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_1B = 3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_1C = 3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_1D = 3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_1E = 3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF @N: FX276 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_rom_4p.v":138:4:138:9|Startup value rom_0_0.INITVAL_1F = 3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF3FFFF @N: MF179 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr.v":1052:12:1052:26|Found 8 bit by 8 bit '==' comparator, 'un4_SBIX_BIT_OUT' @N: FX404 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":162:24:164:21|Found addmux in view:work.rtavr_gpr_16(verilog) inst un1_gpr_4[8:0] from un1_gpr_3[8:0] @N:"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_spi.v":261:2:261:7|Found counter in view:work.rtavr_ior_0s(verilog) inst i_spi.r_count[3:0] @W: BN132 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":126:2:126:7|Removing instance RTAVR.IOR.i_port_c.r_pin[6], because it is equivalent to instance RTAVR.IOR.i_port_c.r_pin[5] @W: BN132 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":126:2:126:7|Removing instance RTAVR.IOR.i_port_c.r_pin[5], because it is equivalent to instance RTAVR.IOR.i_port_c.r_pin[4] @W: BN132 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":126:2:126:7|Removing instance RTAVR.IOR.i_port_c.r_pin[4], because it is equivalent to instance RTAVR.IOR.i_port_c.r_pin[2] @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_port.v":126:2:126:7|Removing sequential instance i_port_c.r_pin[2] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_0s(verilog) because there are no references to its outputs @N:"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_timer0.v":213:2:213:7|Found counter in view:work.rtavr_ior_ps_0s(verilog) inst i_timer0.r_prescaler[5:0] @N:"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Found counter in view:work.rtavr_ior_usart_14(verilog) inst rx_count[4:0] @N:"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Found counter in view:work.rtavr_ior_usart_14(verilog) inst r_ps[11:0] @N:"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Found counter in view:work.rtavr_ior_usart_14(verilog) inst tx_count[4:0] @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance rx_data[8] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance rx_data[7] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance rx_data[6] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance rx_data[5] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance rx_data[4] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance rx_data[3] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance rx_data[2] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance rx_data[1] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance rx_data[0] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance r_udr_rx[7] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance r_udr_rx[6] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance r_udr_rx[5] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance r_udr_rx[4] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance r_udr_rx[3] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance r_udr_rx[2] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance r_udr_rx[1] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance r_udr_rx[0] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr_ior_usart_14(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_s1_decode.v":736:2:736:7|Removing sequential instance S1.r_pc_rd of view:UNILIB.FDSE(PRIM) in hierarchy view:work.rtavr(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance IOR.i_usart.tx_mclk of view:UNILIB.FDRE(PRIM) in hierarchy view:work.rtavr(verilog) because there are no references to its outputs Finished factoring (Time elapsed 0h:00m:05s; Memory used current: 84MB peak: 85MB) @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.r_udr_tx[7] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.r_udr_tx[6] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.r_udr_tx[5] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.r_udr_tx[4] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.r_udr_tx[3] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.r_udr_tx[2] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.r_udr_tx[1] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.r_udr_tx[0] of view:UNILIB.FDRE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.tx_data[8] of view:UNILIB.FDSE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.tx_data[7] of view:UNILIB.FDSE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.tx_data[6] of view:UNILIB.FDSE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.tx_data[5] of view:UNILIB.FDSE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.tx_data[4] of view:UNILIB.FDSE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.tx_data[3] of view:UNILIB.FDSE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.tx_data[2] of view:UNILIB.FDSE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.tx_data[1] of view:UNILIB.FDSE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.tx_data[0] of view:UNILIB.FDSE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs @N: BN362 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_ior_usart.v":340:2:340:7|Removing sequential instance RTAVR.IOR.i_usart.r_txd of view:UNILIB.FDSE(PRIM) in hierarchy view:work.xo2_isp(verilog) because there are no references to its outputs #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[ ====================================================================================== Instance:Pin Generated Clock Optimization Status ====================================================================================== RTAVR.ROM.r_dobh:C Not Done RTAVR.r_clk:C Not Done ISP.r2_store:C Done ISP.r_sck:C Done ISP.r_cs:C Done ISP.r_load:C Done ISP.r_count[2]:C Done ISP.r_count[1]:C Done ISP.r_count[0]:C Done ISP.r_count[3]:C Done ISP.r_pr[15:0]:C Done ISP.r_spi[7]:C Done ISP.r_spi[6]:C Done ISP.r_spi[5]:C Done ISP.r_spi[4]:C Done ISP.r_spi[3]:C Done ISP.r_spi[2]:C Done ISP.r_spi[1]:C Done ISP.r_spi[0]:C Done ISP.r_pr_inc:C Done ISP.r_sstpr_lo:C Done ISP.r_store:C Done ISP.r_data[7]:C Done ISP.r_data[6]:C Done ISP.r_data[5]:C Done ISP.r_data[4]:C Done ISP.r_data[3]:C Done ISP.r_data[2]:C Done ISP.r_data[1]:C Done ISP.r_data[0]:C Done ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################] Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:05s; Memory used current: 82MB peak: 85MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:07s; Memory used current: 80MB peak: 85MB) Starting Early Timing Optimization (Time elapsed 0h:00m:09s; Memory used current: 81MB peak: 85MB) Finished Early Timing Optimization (Time elapsed 0h:00m:09s; Memory used current: 81MB peak: 85MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:10s; Memory used current: 80MB peak: 85MB) Finished preparing to map (Time elapsed 0h:00m:12s; Memory used current: 81MB peak: 85MB) Finished technology mapping (Time elapsed 0h:00m:18s; Memory used current: 105MB peak: 117MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ ------------------------------------------------------------ @N: FX104 |Net "CLK_OUT" with "176" loads has been buffered by "2" buffers due to a soft fanout limit of "100" Net buffering Report for view:work.xo2_isp(verilog): Added 2 Buffers Added 0 Registers via replication Added 0 LUTs via replication Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:20s; Memory used current: 105MB peak: 117MB) @N: FX164 |The option to pack flops in the IOB has not been specified @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr_xo\source\xo2_isp.v":31:17:31:19|Tristate driver LED_obuft_2_.un1[0] on net LED[2] has its enable tied to GND (module xo2_isp) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr_xo\source\xo2_isp.v":31:17:31:19|Tristate driver LED_obuft_3_.un1[0] on net LED[3] has its enable tied to GND (module xo2_isp) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr_xo\source\xo2_isp.v":31:17:31:19|Tristate driver LED_obuft_4_.un1[0] on net LED[4] has its enable tied to GND (module xo2_isp) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr_xo\source\xo2_isp.v":31:17:31:19|Tristate driver LED_obuft_5_.un1[0] on net LED[5] has its enable tied to GND (module xo2_isp) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr_xo\source\xo2_isp.v":31:17:31:19|Tristate driver LED_obuft_6_.un1[0] on net LED[6] has its enable tied to GND (module xo2_isp) @W: MO111 :"z:\avr_core\rtavr_diamond\rtavr_xo\source\xo2_isp.v":31:17:31:19|Tristate driver LED_obuft_7_.un1[0] on net LED[7] has its enable tied to GND (module xo2_isp) @N: FO126 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":187:0:187:5|Generating RAM RTAVR.GPR.gpr_1[7:0] @N: FO126 :"z:\avr_core\rtavr_diamond\rtavr-0.9.5\soc\rtavr_gpr_16.v":187:0:187:5|Generating RAM RTAVR.GPR.gpr[7:0] Finished restoring hierarchy (Time elapsed 0h:00m:22s; Memory used current: 106MB peak: 117MB) Writing Analyst data base Z:\AVR_CORE\rtavr_diamond\rtavr_xo\MachXO_Breakout_rtavr_xo.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:24s; Memory used current: 107MB peak: 117MB) Writing EDIF Netlist and constraint files F-2011.09L Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:25s; Memory used current: 111MB peak: 117MB) Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:26s; Memory used current: 109MB peak: 117MB) ================= Gated clock report ================= The following instances have been converted Seq Inst Instance Port Clock ------------------------------------------------------- RTAVR.ROM.DOA[15] CK RTAVR.CLK_OUT_i RTAVR.ROM.DOA[14] CK RTAVR.CLK_OUT_i RTAVR.ROM.DOA[13] CK RTAVR.CLK_OUT_i RTAVR.ROM.DOA[12] CK RTAVR.CLK_OUT_i RTAVR.ROM.DOA[11] CK RTAVR.CLK_OUT_i RTAVR.ROM.DOA[10] CK RTAVR.CLK_OUT_i RTAVR.ROM.DOA[9] CK RTAVR.CLK_OUT_i RTAVR.ROM.DOA[8] CK RTAVR.CLK_OUT_i RTAVR.ROM.DOA[7] CK RTAVR.CLK_OUT_i RTAVR.ROM.DOA[6] CK RTAVR.CLK_OUT_i RTAVR.ROM.DOA[5] CK RTAVR.CLK_OUT_i RTAVR.ROM.DOA[4] CK RTAVR.CLK_OUT_i RTAVR.ROM.DOA[3] CK RTAVR.CLK_OUT_i RTAVR.ROM.DOA[2] CK RTAVR.CLK_OUT_i RTAVR.ROM.DOA[1] CK RTAVR.CLK_OUT_i RTAVR.ROM.DOA[0] CK RTAVR.CLK_OUT_i ======================================================= The following instances have NOT been converted Seq Inst Instance Port Clock Reason for not converting ----------------------------------------------------------------------------------------------------------------- ISP.r_data[7] CK RTAVR.CLK_OUTgen Gated clock either has NO DRIVER or has MULTIPLE DRIVERS ISP.r_data[6] CK RTAVR.CLK_OUTgen Gated clock either has NO DRIVER or has MULTIPLE DRIVERS ISP.r_data[5] CK RTAVR.CLK_OUTgen Gated clock either has NO DRIVER or has MULTIPLE DRIVERS ISP.r_data[4] CK RTAVR.CLK_OUTgen Gated clock either has NO DRIVER or has MULTIPLE DRIVERS ISP.r_data[3] CK RTAVR.CLK_OUTgen Gated clock either has NO DRIVER or has MULTIPLE DRIVERS ISP.r_data[2] CK RTAVR.CLK_OUTgen Gated clock either has NO DRIVER or has MULTIPLE DRIVERS ISP.r_data[1] CK RTAVR.CLK_OUTgen Gated clock either has NO DRIVER or has MULTIPLE DRIVERS ISP.r_data[0] CK RTAVR.CLK_OUTgen Gated clock either has NO DRIVER or has MULTIPLE DRIVERS ================================================================================================================= ================= End gated clock report ================= Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:26s; Memory used current: 109MB peak: 117MB) Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:26s; Memory used current: 109MB peak: 117MB) @N: MF333 |Generated clock conversion enabled, but no generated clocks found in design Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:26s; Memory used current: 109MB peak: 117MB) @W: MT246 :"z:\avr_core\rtavr_diamond\rtavr_xo\source\xo2_isp.v":76:7:76:18|Blackbox OSCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"z:\avr_core\rtavr_diamond\rtavr_xo\source\xo2_isp.v":42:14:42:18|Blackbox JTAGD is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT420 |Found inferred clock xo2_isp|CLK_INT_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:CLK_INT" Found clock rtavr|r_clk_derived_clock with period 1000.00ns ##### START OF TIMING REPORT #####[ # Timing Report written on Thu Feb 23 17:37:20 2012 # Top view: xo2_isp Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 3 Constraint File(s): @N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing. Performance Summary ******************* Worst slack in design: 479.777 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------- rtavr|r_clk_derived_clock 1.0 MHz 50.8 MHz 1000.000 19.696 986.804 derived (from xo2_isp|CLK_INT_inferred_clock) Inferred_clkgroup_0 xo2_isp|CLK_INT_inferred_clock 1.0 MHz 24.7 MHz 1000.000 40.446 479.777 inferred Inferred_clkgroup_0 System 1.0 MHz 222.1 MHz 1000.000 4.503 995.497 system system_clkgroup ============================================================================================================================================================================ Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 1000.000 995.497 | No paths - | No paths - | No paths - System xo2_isp|CLK_INT_inferred_clock | 1000.000 981.329 | No paths - | 1000.000 986.972 | No paths - System rtavr|r_clk_derived_clock | No paths - | No paths - | 1000.000 993.401 | No paths - xo2_isp|CLK_INT_inferred_clock System | No paths - | No paths - | No paths - | 1000.000 992.744 xo2_isp|CLK_INT_inferred_clock xo2_isp|CLK_INT_inferred_clock | 1000.000 988.119 | 1000.000 972.419 | 500.000 481.763 | 500.000 479.777 xo2_isp|CLK_INT_inferred_clock rtavr|r_clk_derived_clock | No paths - | 1000.000 991.849 | 500.000 490.152 | No paths - rtavr|r_clk_derived_clock xo2_isp|CLK_INT_inferred_clock | No paths - | 1000.000 986.804 | No paths - | No paths - rtavr|r_clk_derived_clock rtavr|r_clk_derived_clock | No paths - | 1000.000 996.040 | No paths - | No paths - ============================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* Input Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock ----------------------------------------------------------------------------- TOP_TCK System (rising) NA 0.000 997.770 TOP_TDI System (rising) NA 0.000 997.770 TOP_TMS System (rising) NA 0.000 997.770 ============================================================================= Output Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock ------------------------------------------------------------------------------------------------------ LED[0] xo2_isp|CLK_INT_inferred_clock (falling) NA 7.256 1000.000 LED[1] xo2_isp|CLK_INT_inferred_clock (falling) NA 7.256 1000.000 LED[2] NA NA NA NA NA LED[3] NA NA NA NA NA LED[4] NA NA NA NA NA LED[5] NA NA NA NA NA LED[6] NA NA NA NA NA LED[7] NA NA NA NA NA TOP_TDO System (rising) NA 4.503 1000.000 ====================================================================================================== ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report Part: lcmxo2280c-3 Register bits: 369 of 2280 (16%) Latch bits: 16 PIC Latch: 0 I/O cells: 12 Block Rams : 3 of 3 (100%) Details: CCU2: 77 DPR16X2B: 4 FD1P3AX: 107 FD1P3IX: 240 FD1P3JX: 2 FD1S1AY: 16 FD1S3AX: 2 FD1S3IX: 17 FD1S3JX: 1 GSR: 1 IB: 3 INV: 6 L6MUX21: 2 OB: 9 ORCALUT4: 992 PFUMX: 102 PUR: 1 SP8KB: 3 SPR16X2B: 4 VHI: 1 VLO: 1 false: 15 true: 15 Mapper successful! At Mapper Exit (Time elapsed 0h:00m:26s; Memory used current: 28MB peak: 117MB) Process took 0h:00m:51s realtime, 0h:00m:26s cputime # Thu Feb 23 17:37:22 2012 ###########################################################]