Synthesis and Ngdbuild  Report
#Build: Synplify Pro F-2011.09L, Build 022R, Oct 19 2011
#install: C:\lscc\diamond\1.4\synpbase
#OS: Windows XP 5.1
#Hostname: BANDIT

$ Start of Compile
#Fri Feb 24 10:00:43 2012

Synopsys Verilog Compiler, version comp560rcp1, Build 045R, built Oct 18 2011
@N|Running in 32-bit mode
Copyright (C) 1994-2011 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@I::"C:\lscc\diamond\1.4\synpbase\lib\lucent\machxo2.v"
@I::"C:\lscc\diamond\1.4\synpbase\lib\vlog\scemi_objects.v"
@I::"C:\lscc\diamond\1.4\synpbase\lib\vlog\hypermods.v"
@I::"C:\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo2.v"
@I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v"
@W: CG921 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":45:7:45:9|RXD is already declared in this scope.
@W: CG921 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":46:7:46:9|CTS is already declared in this scope.
@W: CG921 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":47:7:47:15|EXTOSC_EN is already declared in this scope.
@W: CG921 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":221:7:221:9|CLK is already declared in this scope.
@I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr_tools-0.6\test_hdl\isp.v"
@I::"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr_tools-0.6\test_hdl\spi_echo.v"
Verilog syntax check successful!
Selecting top level module tool_test
@N: CG364 :"C:\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo2.v":1540:7:1540:11|Synthesizing module JTAGF

@N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr_tools-0.6\test_hdl\spi_echo.v":17:7:17:14|Synthesizing module spi_echo

@W: CG133 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr_tools-0.6\test_hdl\spi_echo.v":29:8:29:15|No assignment to r_spi_in
@N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr_tools-0.6\test_hdl\isp.v":70:7:70:9|Synthesizing module isp

@N: CL134 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\rtavr_tools-0.6\test_hdl\isp.v":241:4:241:9|Found RAM mem, depth=1024, width=8
@N: CG364 :"C:\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo2.v":1793:7:1793:10|Synthesizing module OSCH

@N: CG364 :"C:\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo2.v":1520:7:1520:10|Synthesizing module DCMA

@N: CG364 :"C:\lscc\diamond\1.4\cae_library\synthesis\verilog\machxo2.v":1730:7:1730:13|Synthesizing module EHXPLLJ

@N: CG364 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":25:7:25:15|Synthesizing module tool_test

@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input CLKFB on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PHASESEL1 on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PHASESEL0 on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PHASEDIR on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PHASESTEP on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input LOADREG on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input STDBY on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLWAKESYNC on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input RST on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input RESETM on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input RESETC on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input RESETD on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input ENCLKOP on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLCLK on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLRST on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLSTB on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLWE on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLDATI7 on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLDATI6 on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLDATI5 on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLDATI4 on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLDATI3 on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLDATI2 on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLDATI1 on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLDATI0 on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLADDR4 on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLADDR3 on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLADDR2 on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLADDR1 on instance pll, tying to 0
@W: CG781 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Undriven input PLLADDR0 on instance pll, tying to 0
@W: CL271 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":244:2:244:7|Pruning bits 26 to 25 of clk_count0[26:0] -- not in use ...

@W: CL271 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":250:2:250:7|Pruning bits 26 to 25 of clk_count1[26:0] -- not in use ...

@W: CL271 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":257:2:257:7|Pruning bits 26 to 25 of clk_count2[26:0] -- not in use ...

@W: CL271 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":261:2:261:7|Pruning bits 26 to 25 of clk_count3[26:0] -- not in use ...

@W: CL271 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":265:2:265:7|Pruning bits 26 to 25 of clk_count4[26:0] -- not in use ...

@W: CL271 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":233:2:233:7|Pruning bits 26 to 25 of clk_count[26:0] -- not in use ...

@W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":36:10:36:12|Input TXD is unused
@W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":36:15:36:17|Input RTS is unused
@W: CL159 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":36:20:36:22|Input DTR is unused
@W: CL158 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":37:10:37:12|Inout RXD is unused
@W: CL158 :"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":37:15:37:17|Inout CTS is unused
@END
Premap Report (contents appended below)
@N:"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\synlog\MachXO2_Breakout_test_hdl_xo2_premap.srr"
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 239R, Built Oct 19 2011 10:56:21
Copyright (C) 1994-2011, Synopsys Inc.  All Rights Reserved
Product Version F-2011.09L

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled 
@N: MF546 |Generated clock conversion enabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 50MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 50MB)

@W: FX474 |User specified initial value found in some of the sequential elements in the design. Applying an initial value to a register may not deliver the best synthesis results. For example, registers with initial values may be preserved and retiming/pipelining may not be performed. To improve synthesis results you may want to remove the register initialization from the RTL code 
syn_allowed_resources : blockrams=7  set on top level netlist tool_test

Finished Pre Mapping Phase. (Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 77MB)

Pre Mapping successful!

At Mapper Exit (Time elapsed 0h:00m:01s; Memory used current: 43MB peak: 77MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Feb 24 10:00:47 2012

###########################################################]
Map & Optimize Report (contents appended below)
@N:"C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\synlog\MachXO2_Breakout_test_hdl_xo2_fpga_mapper.srr"
Synopsys Lattice Technology Mapper, Version maplat, Build 239R, Built Oct 19 2011 10:56:21
Copyright (C) 1994-2011, Synopsys Inc.  All Rights Reserved
Product Version F-2011.09L

Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled 
@N: MF546 |Generated clock conversion enabled 

Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)


Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

@N: MF203 |Set autoconstraint_io 


Starting Optimization and Mapping (Time elapsed 0h:00m:01s; Memory used current: 74MB peak: 77MB)


Available hyper_sources - for debug and ip models
	None Found


Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 77MB)

@N: BN362 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr_tools-0.6\test_hdl\spi_echo.v":40:4:40:9|Removing sequential instance SPI_ECHO.r_data[7] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.tool_test(verilog) because there are no references to its outputs 
@N: BN362 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr_tools-0.6\test_hdl\spi_echo.v":40:4:40:9|Removing sequential instance SPI_ECHO.r_data[6] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.tool_test(verilog) because there are no references to its outputs 
@N: BN362 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr_tools-0.6\test_hdl\spi_echo.v":40:4:40:9|Removing sequential instance SPI_ECHO.r_data[5] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.tool_test(verilog) because there are no references to its outputs 
@N: BN362 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr_tools-0.6\test_hdl\spi_echo.v":40:4:40:9|Removing sequential instance SPI_ECHO.r_data[4] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.tool_test(verilog) because there are no references to its outputs 
@N: BN362 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr_tools-0.6\test_hdl\spi_echo.v":40:4:40:9|Removing sequential instance SPI_ECHO.r_data[3] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.tool_test(verilog) because there are no references to its outputs 
@N: BN362 :"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr_tools-0.6\test_hdl\spi_echo.v":40:4:40:9|Removing sequential instance SPI_ECHO.r_data[2] of view:UNILIB.FDCPE(PRIM) in hierarchy view:work.tool_test(verilog) because there are no references to its outputs 
@N:"c:\documents and settings\suz\my documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":265:2:265:7|Found counter in view:work.tool_test(verilog) inst clk_count4[24:0]
@N:"c:\documents and settings\suz\my documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":261:2:261:7|Found counter in view:work.tool_test(verilog) inst clk_count3[24:0]
@N:"c:\documents and settings\suz\my documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":257:2:257:7|Found counter in view:work.tool_test(verilog) inst clk_count2[24:0]
@N:"c:\documents and settings\suz\my documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":250:2:250:7|Found counter in view:work.tool_test(verilog) inst clk_count1[24:0]
@N:"c:\documents and settings\suz\my documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":244:2:244:7|Found counter in view:work.tool_test(verilog) inst clk_count0[24:0]
@N:"c:\documents and settings\suz\my documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":233:2:233:7|Found counter in view:work.tool_test(verilog) inst clk_count[24:0]
@N:"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr_tools-0.6\test_hdl\isp.v":163:4:163:9|Found counter in view:work.isp(verilog) inst r_pr[15:0]
@N:"c:\documents and settings\suz\my documents\rtavr_diamond\rtavr_tools-0.6\test_hdl\isp.v":163:4:163:9|Found counter in view:work.isp(verilog) inst r_count[3:0]

Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 75MB peak: 77MB)



#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[

======================================================================================
                                Instance:Pin        Generated Clock Optimization Status
======================================================================================
                          SPI_ECHO.r_sck:C              Not Done
                              r_cs1_prev:C              Not Done
                        clk_count0[24:0]:C              Not Done
                        clk_count1[24:0]:C              Not Done
                        clk_count2[24:0]:C              Not Done
                        clk_count3[24:0]:C              Not Done
                        clk_count4[24:0]:C              Not Done


##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]


Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 77MB)



Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 77MB)


Starting Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 77MB)


Finished Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 77MB)


Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:02s; Memory used current: 75MB peak: 77MB)


Finished preparing to map (Time elapsed 0h:00m:03s; Memory used current: 76MB peak: 77MB)


Finished technology mapping (Time elapsed 0h:00m:03s; Memory used current: 76MB peak: 77MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:03s; Memory used current: 76MB peak: 77MB)

@N: FX164 |The option to pack flops in the IOB has not been specified 

Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 76MB peak: 77MB)

Writing Analyst data base C:\Documents and Settings\suz\My Documents\rtavr_diamond\test_hdl_xo2\MachXO2_Breakout_test_hdl_xo2.srm

Finished Writing Netlist Databases (Time elapsed 0h:00m:05s; Memory used current: 76MB peak: 77MB)

Writing EDIF Netlist and constraint files
F-2011.09L

Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:07s; Memory used current: 79MB peak: 80MB)


Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:08s; Memory used current: 79MB peak: 80MB)

@N: MF276 |Gated clock conversion enabled, but no gated clocks found in design 

Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:08s; Memory used current: 79MB peak: 80MB)


Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:08s; Memory used current: 79MB peak: 80MB)

@N: MF333 |Generated clock conversion enabled, but no generated clocks found in design 

Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:08s; Memory used current: 79MB peak: 80MB)

@W: MT246 :"c:\documents and settings\suz\my documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":197:3:197:5|Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\documents and settings\suz\my documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":180:7:180:18|Blackbox DCMA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\documents and settings\suz\my documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":168:29:168:40|Blackbox OSCH is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT246 :"c:\documents and settings\suz\my documents\rtavr_diamond\test_hdl_xo2\source\tool_test.v":50:14:50:18|Blackbox JTAGF is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock tool_test|CLK270_OUT_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:CLK270_OUT"

@W: MT420 |Found inferred clock tool_test|CLK180_OUT_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:CLK180_OUT"

@W: MT420 |Found inferred clock tool_test|CLK90_OUT_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:CLK90_OUT"

@W: MT420 |Found inferred clock tool_test|CLK0_OUT_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:CLK0_OUT"

@W: MT420 |Found inferred clock tool_test|CLK_IN0_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:CLK_IN0"

@W: MT420 |Found inferred clock tool_test|CLK_INT_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:CLK_INT"



##### START OF TIMING REPORT #####[
# Timing Report written on Fri Feb 24 10:00:56 2012
#


Top view:               tool_test
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.


Performance Summary 
*******************


Worst slack in design: 495.105

                                        Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock                          Frequency     Frequency     Period        Period        Slack       Type         Group              
--------------------------------------------------------------------------------------------------------------------------------------------
tool_test|CLK0_OUT_inferred_clock       1.0 MHz       191.5 MHz     1000.000      5.221         994.779     inferred     Inferred_clkgroup_2
tool_test|CLK90_OUT_inferred_clock      1.0 MHz       191.5 MHz     1000.000      5.221         994.779     inferred     Inferred_clkgroup_3
tool_test|CLK180_OUT_inferred_clock     1.0 MHz       191.5 MHz     1000.000      5.221         994.779     inferred     Inferred_clkgroup_4
tool_test|CLK270_OUT_inferred_clock     1.0 MHz       191.5 MHz     1000.000      5.221         994.779     inferred     Inferred_clkgroup_5
tool_test|CLK_IN0_inferred_clock        1.0 MHz       191.5 MHz     1000.000      5.221         994.779     inferred     Inferred_clkgroup_1
tool_test|CLK_INT_inferred_clock        1.0 MHz       102.2 MHz     1000.000      9.789         495.105     inferred     Inferred_clkgroup_0
System                                  1.0 MHz       153.8 MHz     1000.000      6.504         993.496     system       system_clkgroup    
============================================================================================================================================





Clock Relationships
*******************

Clocks                                                                    |    rise  to  rise     |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                             Ending                               |  constraint  slack    |  constraint  slack    |  constraint  slack    |  constraint  slack  
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                               System                               |  1000.000    993.496  |  No paths    -        |  No paths    -        |  No paths    -      
System                               tool_test|CLK_INT_inferred_clock     |  1000.000    997.230  |  No paths    -        |  1000.000    999.197  |  No paths    -      
tool_test|CLK_INT_inferred_clock     System                               |  1000.000    994.504  |  No paths    -        |  No paths    -        |  1000.000    995.144
tool_test|CLK_INT_inferred_clock     tool_test|CLK_INT_inferred_clock     |  1000.000    994.779  |  1000.000    991.538  |  500.000     495.109  |  500.000     495.105
tool_test|CLK_IN0_inferred_clock     System                               |  1000.000    994.504  |  No paths    -        |  No paths    -        |  No paths    -      
tool_test|CLK_IN0_inferred_clock     tool_test|CLK_IN0_inferred_clock     |  1000.000    994.779  |  No paths    -        |  No paths    -        |  No paths    -      
tool_test|CLK0_OUT_inferred_clock    System                               |  1000.000    994.504  |  No paths    -        |  No paths    -        |  No paths    -      
tool_test|CLK0_OUT_inferred_clock    tool_test|CLK0_OUT_inferred_clock    |  1000.000    994.779  |  No paths    -        |  No paths    -        |  No paths    -      
tool_test|CLK90_OUT_inferred_clock   System                               |  1000.000    994.504  |  No paths    -        |  No paths    -        |  No paths    -      
tool_test|CLK90_OUT_inferred_clock   tool_test|CLK90_OUT_inferred_clock   |  1000.000    994.779  |  No paths    -        |  No paths    -        |  No paths    -      
tool_test|CLK180_OUT_inferred_clock  System                               |  1000.000    994.504  |  No paths    -        |  No paths    -        |  No paths    -      
tool_test|CLK180_OUT_inferred_clock  tool_test|CLK180_OUT_inferred_clock  |  1000.000    994.779  |  No paths    -        |  No paths    -        |  No paths    -      
tool_test|CLK270_OUT_inferred_clock  System                               |  1000.000    994.504  |  No paths    -        |  No paths    -        |  No paths    -      
tool_test|CLK270_OUT_inferred_clock  tool_test|CLK270_OUT_inferred_clock  |  1000.000    994.779  |  No paths    -        |  No paths    -        |  No paths    -      
========================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port        Starting            User           Arrival     Required          
Name        Reference           Constraint     Time        Time         Slack
            Clock                                                            
-----------------------------------------------------------------------------
CTS         NA                  NA             NA          NA           NA   
DTR         NA                  NA             NA          NA           NA   
EXTOSC      System (rising)     NA             0.000       993.496           
RTS         NA                  NA             NA          NA           NA   
RXD         NA                  NA             NA          NA           NA   
TOP_TCK     System (rising)     NA             0.000       998.020           
TOP_TDI     System (rising)     NA             0.000       998.020           
TOP_TMS     System (rising)     NA             0.000       998.020           
TXD         NA                  NA             NA          NA           NA   
=============================================================================


Output Ports: 

Port          Starting                                         User           Arrival     Required          
Name          Reference                                        Constraint     Time        Time         Slack
              Clock                                                                                         
------------------------------------------------------------------------------------------------------------
EXTOSC_EN     System (rising)                                  NA             6.504       1000.000          
LED[0]        tool_test|CLK_INT_inferred_clock (falling)       NA             4.856       1000.000          
LED[1]        tool_test|CLK_INT_inferred_clock (falling)       NA             4.856       1000.000          
LED[2]        tool_test|CLK270_OUT_inferred_clock (rising)     NA             5.496       1000.000          
LED[3]        tool_test|CLK180_OUT_inferred_clock (rising)     NA             5.496       1000.000          
LED[4]        tool_test|CLK90_OUT_inferred_clock (rising)      NA             5.496       1000.000          
LED[5]        tool_test|CLK0_OUT_inferred_clock (rising)       NA             5.496       1000.000          
LED[6]        tool_test|CLK_IN0_inferred_clock (rising)        NA             5.496       1000.000          
LED[7]        tool_test|CLK_INT_inferred_clock (rising)        NA             5.496       1000.000          
TOP_TDO       System (rising)                                  NA             3.884       1000.000          
============================================================================================================


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report
Part: lcmxo2_1200ze-1

Register bits: 208 of 1280 (16%)
PIC Latch:       0
I/O cells:       14


Details:
CCU2D:          87
FD1P3AX:        46
FD1S3AX:        153
FD1S3IX:        7
GSR:            1
IB:             4
INV:            12
OB:             10
OFS1P3DX:       2
ORCALUT4:       61
PUR:            1
SP8KC:          1
VHI:            1
VLO:            1
false:          3
true:           3
Mapper successful!

At Mapper Exit (Time elapsed 0h:00m:08s; Memory used current: 25MB peak: 80MB)

Process took 0h:00m:09s realtime, 0h:00m:08s cputime
# Fri Feb 24 10:00:56 2012

###########################################################]