// states
`define IDLE	 	5'h00
`define CYCTYPE		5'h01

`define ADDR1		5'h02
`define ADDR2		5'h03
`define ADDR3		5'h04
`define ADDR4		5'h05
`define CHANSZ1		5'h06
`define CHANSZ2		5'h07
  // Host Initlated Write Sequences
`define HW_DATA1	5'h08
`define HW_DATA2	5'h09
`define HW_TAR_H1	5'h0A
`define HW_TAR_H2	5'h0B
`define HW_SYNC		5'h0C
`define HW_TAR_P1	5'h0E
`define HW_TAR_P2	5'h0F
  // Host Initlated Read Sequences
`define HR_TAR_H1	5'h10
`define HR_TAR_H2	5'h11
`define HR_SYNC		5'h12
`define HR_DATA1	5'h14
`define HR_DATA2	5'h15
`define HR_TAR_P1	5'h16
`define HR_TAR_P2	5'h17
// end states

module lpc_slave (
	input LCLK
	, input LRESET
	, input LFRAME
	, inout [3:0] LDA

	, input [7:0] DATA_IN
	, output [7:0] DATA_OUT
	, output [15:0] ADDR_OUT
	, output DATA_WR
	, output DATA_RD
	);

	reg [4:0] state;
	reg [3:0] cyctype;
	reg s_out;
	reg [3:0] r_lda;

	reg [15:0] r_addr;
	reg [7:0] r_data;
	reg r_wr;
	reg r_rd;
	assign DATA_OUT = r_data;
	assign ADDR_OUT = r_addr;
	assign DATA_WR = r_wr;
	assign DATA_RD = r_rd;
	assign LDA = (s_out) ? r_lda : 4'bzzzz;
	
	always @(posedge LCLK)
	begin
	  if (LRESET) 
	    begin
		    state <= `IDLE;
	    end
	  else if (~LFRAME)
	    begin
		    state <= (LDA == 4'b0000)? `CYCTYPE : `IDLE;
	    end
	  else if (state == `CYCTYPE)
	    begin
		    state <=  (LDA[3:2] == 2'b00) ? `ADDR1
`ifdef SUPPORT_DMA
			     :(LDA[3:2] == 2'b01) ? `CHANSZ1
`endif
			     : `IDLE;
		    cyctype <= LDA[3:1];
	    end
	  else if ( state == `ADDR1 ) 
	    begin
		    state <= `ADDR2;
		    r_addr[3:0] <= LDA;
	    end
	  else if ( state == `ADDR2 ) 
	    begin
		    state <= `ADDR3;
		    r_addr[7:4] <= LDA;
	    end
	  else if ( state == `ADDR3 ) 
	    begin
		    state <= `ADDR4;
		    r_addr[11:8] <= LDA;
	    end
	  else if ( state == `ADDR4 ) 
	    begin
		    state <= cyctype[0] ? `HW_DATA1 : `HR_TAR_H1;
		    r_addr[15:12] <= LDA;
	    end
`ifdef SUPPORT_DMA
	  else if ( state == `CHANSZ1 ) 
	    begin
		    state <= `CHANSZ2;
		    r_chan[3:0] <= LDA;
	    end
	  else if ( state == `CHANSZ2 ) 
	    begin
		    state <= `xxx;
		    r_size[3:0] <= LDA;
	    end
`endif
	  // Host Initlated Write Sequences
	  else if ( state == `HW_DATA1 ) 
	    begin
		    state <= `HW_DATA2;
		    r_data[3:0] <= LDA;
	    end
	  else if ( state == `HW_DATA2 ) 
	    begin
		    state <= `HW_TAR_H1;
		    r_data[7:4] <= LDA;
	    end
	  else if ( state == `HW_TAR_H1 )  state <= `HW_TAR_H2;
	  else if ( state == `HW_TAR_H2 )  state <= `HW_SYNC;
	  else if ( state == `HW_SYNC )    state <= `HW_TAR_P1;
	  else if ( state == `HW_TAR_P1 )  state <= `IDLE;
	  // Host Initlated Read Sequences
	  else if ( state == `HR_TAR_H1 )  state <= `HR_TAR_H2;
	  else if ( state == `HR_TAR_H2 )  state <= `HR_SYNC;
	  else if ( state == `HR_SYNC )    state <= `HR_DATA1;
	  else if ( state == `HR_DATA1 )   state <= `HR_DATA2;
	  else if ( state == `HR_DATA2 )   state <= `HR_TAR_P1;
	  else if ( state == `HR_TAR_P1 )  state <= `IDLE;
	  else                             state <= `IDLE;
	end // always

	always @(negedge LCLK)
	begin
	  // Host Initlated Write Sequences
	  if ( state == `HW_SYNC ) 
	    begin
		    s_out <= 1'b1;
		    r_lda <= 4'b0000; // Ready
	    end
	  else if ( state == `HW_TAR_P1 ) 
	    begin
		    s_out <= 1'b1;
		    r_lda <= 4'b1111;
	    end
	  // Host Initlated Read Sequences
	  else if ( state == `HR_SYNC ) 
	    begin
		    s_out <= 1'b1;
		    r_lda <= 4'b0000;
	    end
	  else if ( state == `HR_DATA1 ) 
	    begin
		    s_out <= 1'b1;
		    r_lda <= DATA_IN[3:0];
	    end
	  else if ( state == `HR_DATA2 ) 
	    begin
		    s_out <= 1'b0;
		    r_lda <= DATA_IN[7:4];
	    end
	  else if ( state == `HR_TAR_P1 ) 
	    begin
		    s_out <= 1'b1;
		    r_lda <= 4'b1111;
	    end
	  else
	    begin
		    s_out <= 1'b0;
		    r_lda <= 4'b1111;
	    end

	r_wr <= ( state == `HW_TAR_H1 ) | ( state == `HW_TAR_H2 );
	r_rd <= ( state == `HR_TAR_H1 ) | ( state == `HR_TAR_H2 );
	end // always
endmodule