// states
`define IDLE	 	5'h00
`define CYCTYPE		5'h01

`define ADDR1		5'h02
`define ADDR2		5'h03
`define ADDR3		5'h04
`define ADDR4		5'h05
`define CHANSZ1		5'h06
`define CHANSZ2		5'h07
  // Host Initlated Write Sequences
`define HW_DATA1	5'h08
`define HW_DATA2	5'h09
`define HW_TAR_H1	5'h0A
`define HW_TAR_H2	5'h0B
`define HW_SYNC		5'h0C
`define HW_TAR_P1	5'h0E
`define HW_TAR_P2	5'h0F
  // Host Initlated Read Sequences
`define HR_TAR_H1	5'h10
`define HR_TAR_H2	5'h11
`define HR_SYNC		5'h12
`define HR_DATA1	5'h14
`define HR_DATA2	5'h15
`define HR_TAR_P1	5'h16
`define HR_TAR_P2	5'h17

`define START		5'h1D
`define SYNC_TIMEOUT1	5'h1E
`define SYNC_TIMEOUT2	5'h1F
// end states

//`define XXX

module lpc_master (
	input LCLK
	, input LRESET
	, output LFRAME
	, inout [3:0] LDA

	, input [7:0] DATA_IN
	, output [7:0] DATA_OUT
	, input [15:0] ADDR_IN
	, input DATA_WR
	, input DATA_RD
	, output READY
	, output RD_ACK
	, output WR_ACK
	);

	reg [4:0] state;
	reg [3:0] sync_cnt;
	reg s_out;
	reg s_frame;
	reg [3:0] r_lda;

	reg [7:0] r_data_out;
	reg [7:0] r_data;
	reg [15:0] r_addr;
	reg r_wr;
	reg rd_ack;

	assign DATA_OUT = r_data_out;
	assign WR_ACK = r_wr;
	assign RD_ACK = rd_ack;
	
	assign LDA = (s_out) ? r_lda : 4'bzzzz;
	assign LFRAME = s_frame;
	assign READY = (state == `IDLE);

	always @(posedge LCLK)
	begin
	  if ( state == `HR_DATA1 ) 
		    r_data_out[3:0] <= LDA;

	  if ( state == `HR_DATA2 ) 
	    begin
		    r_data_out[7:4] <= LDA;
		    rd_ack <= 1'b1;
	    end
	  else      rd_ack <= 1'b0;

	  if (( state == `HW_SYNC ) | ( state == `HR_SYNC ))
		    sync_cnt <= sync_cnt + 1;
	  else	    sync_cnt <= 4'b0;


	  if (LRESET) 
	    begin
		    state <= `IDLE;
	    end
	  else if ((state == `IDLE) & (DATA_WR | DATA_RD))
	    begin
		    state <= `START;
		    r_wr <= DATA_RD ? 1'b0 :  DATA_WR;
		    r_addr <= ADDR_IN;
		    if (DATA_RD) r_data <= DATA_IN;
	    end
	  else if (state == `START)     state <= `CYCTYPE;
	  else if (state == `CYCTYPE)   state <= `ADDR1;
	  else if ( state == `ADDR1 )   state <= `ADDR2;
	  else if ( state == `ADDR2 )   state <= `ADDR3;
	  else if ( state == `ADDR3 )   state <= `ADDR4;
	  else if ( state == `ADDR4 ) 
	    begin
		    state <= r_wr ? `HW_DATA1 : `HR_TAR_H1;
	    end
	  // Host Initlated Write Sequences
	  else if ( state == `HW_DATA1 )  state <= `HW_DATA2;
	  else if ( state == `HW_DATA2 )  state <= `HW_TAR_H1;
	  else if ( state == `HW_TAR_H1 ) state <= `HW_TAR_H2;
	  else if ( state == `HW_TAR_H2 ) state <= `HW_SYNC;
	  else if ( state == `HW_SYNC ) 
	    begin
		    state <=  (LDA == 4'b0000) ? `HW_TAR_P1
			     :((LDA == 4'b0101) & (sync_cnt != 4'b1111)) ? `HW_SYNC
			     :((LDA == 4'b0110) & (sync_cnt != 4'b1111)) ? `HW_SYNC
		             : `SYNC_TIMEOUT1;
	    end
	  else if ( state == `HW_TAR_P1 )  state <= `HW_TAR_P1;
	  else if ( state == `HW_TAR_P2 )  state <= `IDLE;
	  // Host Initlated Read Sequences
	  else if ( state == `HR_TAR_H1 )  state <= `HR_TAR_H2;
	  else if ( state == `HR_TAR_H2 )  state <= `HR_SYNC;
	  else if ( state == `HR_SYNC ) 
	    begin
		    state <=  (LDA == 4'b0000) ? `HR_DATA1
			     :((LDA == 4'b0101) & (sync_cnt != 4'b1111)) ? `HR_SYNC
			     :((LDA == 4'b0110) & (sync_cnt != 4'b1111)) ? `HR_SYNC
		             : `SYNC_TIMEOUT1;
	    end
	  else if ( state == `HR_DATA1 )       state <= `HR_DATA2;
	  else if ( state == `HR_DATA2 )       state <= `HR_TAR_P1;
	  else if ( state == `HR_TAR_P1 )      state <= `HR_TAR_P2;
	  else if ( state == `HR_TAR_P2 )      state <= `IDLE;

	  else if ( state == `SYNC_TIMEOUT1 )  state <= `SYNC_TIMEOUT2 ;
	  else if ( state == `SYNC_TIMEOUT2 )  state <= `IDLE ;
	  else                                 state <= `IDLE;
	end // always

	always @(negedge LCLK)
	begin
	  if (state == `START)
	    begin
		    s_frame <= 1'b0;
		    s_out <= 1'b1;
		    r_lda <= 4'b0000; // START
	    end
	  else if (state == `SYNC_TIMEOUT1)
	    begin
		    s_frame <= 1'b0;
		    s_out <= 1'b0;
	    end
	  else if (state == `SYNC_TIMEOUT2)
	    begin
		    s_frame <= 1'b0;
		    s_out <= 1'b1;
		    r_lda <= 4'b1111;
	    end
	  else if (state == `CYCTYPE)
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b1;
		    r_lda <= { 3'b000 , r_wr };
	    end
	  else if ( state == `ADDR1 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b1;
		    r_lda <= r_addr[3:0];
	    end
	  else if ( state == `ADDR2 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b1;
		    r_lda <= r_addr[7:4];
	    end
	  else if ( state == `ADDR3 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b1;
		    r_lda <= r_addr[11:8];
	    end
	  else if ( state == `ADDR4 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b1;
		    r_lda <= r_addr[15:12];
	    end
	  // Host Initlated Write Sequences
	  else if ( state == `HW_DATA1 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b1;
		    r_lda <= r_data[3:0];
	    end
	  else if ( state == `HW_DATA2 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b1;
		    r_lda <= r_data[7:4];
	    end
	  else if ( state == `HW_TAR_H1 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b1;
		    r_lda <= 4'b1111;
	    end
	  else if ( state == `HW_TAR_H2 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b0;
	    end
	  else if ( state == `HW_SYNC ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b0;
	    end
	  else if ( state == `HW_TAR_P1 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b1;
		    r_lda <= 4'b1111;
	    end
	  else if ( state == `HW_TAR_P2 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b0;
	    end
	  // Host Initlated Read Sequences
	  else if ( state == `HR_TAR_H1 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b1;
		    r_lda <= 4'b1111;
	    end
	  else if ( state == `HR_TAR_H2 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b0;
	    end
	  else if ( state == `HR_SYNC ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b0;
	    end
	  else if ( state == `HR_DATA1 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b0;
	    end
	  else if ( state == `HR_DATA2 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b0;
	    end
	  else if ( state == `HR_TAR_P1 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b0;
	    end
	  else if ( state == `HR_TAR_P2 ) 
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b0;
	    end
	  else
	    begin
		    s_frame <= 1'b1;
		    s_out <= 1'b0;
	    end
	end // always

endmodule