module artemis_isp (
		input  CLK1 	// MAIN CLOCK (33MHz) // GLK
		, input  CLK2 	// HOST CLOCK (8 MHz or 6/12/24/48 MHz) // GLK

		// SPI FLASH
		, output  SF_C 
		, input   SF_DO 
		, output  SF_DIO 
		, output  SF_S 

		// CONFIG or LED
		, inout   INIT_B 	// HOST
		, inout   M1 	// HOST or LED
		, inout   M2 	// HOST or LED

		, output  VS0 	// LED
		, output  VS2 	// LED

		// USART (or SPI SLAVE)
		, input  TXD 	// or MOSI	// input only
		, output   RXD 	// or MISO
		, input   DTR 	// or SS
		, input   RTS 	// or SCLK	// GCLK
		);

// EXT card sample pin-assign
//    MicroSD     USB               PLL
//  #1 VCC
//  #2 DETECT      D- PULLUP        PLLCTRL
//  #3 DAT2          --               --
//  #4 DAT3/CS     D-               INV
//  #5   --        D+               XIN
//  #6 CMD/DI      D+ PULLUP          --
//  #7 DAT0/DO     VBUS DETECT      GND
//  #8 DAT1        VBUS SWITCH       --
//  #9 CLK            --            XOUT
//                               (PLLCLOCK)
//  #10 GND

`include "rtavr_defs.v"

  wire [7:0] STATUS;   // STATUS[2] : DFS(= CLKFX) not LOCKED

  DCM_SP #(  
`ifdef USE_DMY_CLOCK
        .CLKFX_MULTIPLY(4),       // 2 to 32
        .CLKFX_DIVIDE(1) ,        // 1 to 32
//        .CLK_FEEDBACK("NONE") ,
`elsif SYS_DRIVEN_CLK4PH
        .CLK_FEEDBACK("1X") ,
`else
        .CLKFX_MULTIPLY(4),       // 2 to 32
        .CLKFX_DIVIDE(1) ,        // 1 to 32
//        .CLK_FEEDBACK("NONE") ,
`endif
//        .DFS_FREQUENCY_MODE("LOW") ,  // Spartan-3A has no modes
//        .DLL_FREQUENCY_MODE("LOW") ,  // Spartan-3A has no modes
//        .STARTUP_WAIT("TRUE")
      .STARTUP_WAIT("FALSE")
  ) DCM1 (
        .CLKIN(CLKIN)
        , .LOCKED(LOCKED)
        , .STATUS(STATUS)
      , .RST(RST)
  `ifdef USE_DMY_CLOCK
        , .CLKFX(CLKFX_OUT)
  `elsif SYS_DRIVEN_CLK4PH
        , .CLKFB(CLKFB)
	, .CLK2X(CLK2X_OUT)
        , .CLK0(CLK0_OUT)
	, .CLK90(CLK90_OUT)
	, .CLK180(CLK180_OUT)
	, .CLK270(CLK270_OUT)
  `else
        , .CLKFX(CLKFX_OUT)
  `endif
  );
  
  BSCAN_SPARTAN3A bscan (
	.RESET(BSCAN_RESET) 
//	, .SHIFT(BSCAN_SHIFT)
//	, .CAPTURE(BSCAN_CAPTURE)
//	, .UPDATE(BSCAN_UPDATE)

	, .TDI(TDI)
	, .TCK(TCK)
	, .TMS(TMS) 

	// signals for USER1
	, .DRCK1(DRCK1)
	, .SEL1(SEL1)
	, .TDO1(TDO1)

	// signals for USER2
	, .DRCK2(DRCK2)
	, .SEL2(SEL2)
	, .TDO2(TDO2) 
	);

`ifdef SUPPORT_ISP
    wire [15:0] ISP_ADDR;
    wire [7:0]  ISP_STORE_DATA;
    wire [7:0]  ISP_LOAD_DATA;

  isp ISP (.CLK(CLK)
		, .MOSI(TDI)
                , .SCK(DRCK2)
                , .CS(SEL2)
                , .MISO(TDO2)

                , .ISP_STORE(ISP_STORE)
                , .ISP_LOAD(ISP_LOAD)
                , .ISP_ADDR(ISP_ADDR)
                , .ISP_STORE_DATA(ISP_STORE_DATA)
                , .ISP_LOAD_DATA(ISP_LOAD_DATA)
		);
`endif

  `ifdef RTAVR_PORT_ESCALATION
    wire [23:0] DDR;
    wire [23:0] PORT;
    wire [23:0] PIN;
  `endif
  
  rtavr RTAVR (.RESET(RESET)
  `ifdef USE_DMY_CLOCK
    `ifdef SYS_DRIVEN_CLK4PH
		, .CLK4X(CLKFX)
    `else
		, .CLK2X(CLKFX)
    `endif
		, .CLK_OUT(CLK_OUT)
  `elsif SYS_DRIVEN_CLK4PH
		, .CLK2X(CLK2X)
		, .CLK_0(CLK_0)
		, .CLK_90(CLK_90)
		, .CLK_180(CLK_180)
		, .CLK_270(CLK_270)
  `else
		, .CLK2X(CLKFX)
		, .CLK_OUT(CLK_OUT)
  `endif

  `ifdef RTAVR_PORT_ESCALATION
		, .DDR(DDR[23:0])
		, .PORT(PORT[23:0])
		, .PIN(PIN[23:0])
  `else
    `ifdef IOR_HAVE_PORTA
		, .PORTA(PORTA[7:0])
    `endif
    `ifdef IOR_HAVE_PORTB
		, .PORTB(PORTB[7:0])
    `endif
    `ifdef IOR_HAVE_PORTC
		, .PORTC(PORTC[7:0])
    `endif
  `endif
`ifdef SUPPORT_ISP
	,  .ISP_STORE(ISP_STORE)
	,  .ISP_LOAD(ISP_LOAD)
	,  .ISP_ADDR(ISP_ADDR[15:0])
	,  .ISP_STORE_DATA(ISP_STORE_DATA[7:0])
	,  .ISP_LOAD_DATA(ISP_LOAD_DATA[7:0])
`endif
 );

//  assign CLKIN = CLK2;
  IBUFG BUFG_CLKIN
//    # (.IBUF_DELAY_VALUE(5))  
	(.I(CLK2) , .O(CLKIN));

    reg [15:0] r_rst_once = 16'hffff;
    always @(posedge CLKIN)
    begin
	r_rst_once   <=  { r_rst_once[14:0]   , 1'b0 };
    end

//    initial
//    begin
//       r_rst_once   <= 16'hffff;
//    end
    assign RST = r_rst_once;
//    assign RST = CLK1;
  
`ifdef USE_DMY_CLOCK
   assign CLKFX = CLKFX_OUT;
//  BUFG BUFG_CLKFX (.I(CLKFX_OUT) , .O(CLKFX));
//  BUFG BUFG_CLKFB (.I(CLK0_OUT) , .O(CLKFB));
   assign CLK = CLK_OUT;
    assign RESET = BSCAN_RESET | ~LOCKED | STATUS[2];
`elsif SYS_DRIVEN_CLK4PH
//    BUFG BUFG_CLKFB (.I(CLK0_OUT) , .O(CLKFB));
//    BUFG BUFG_CLK0 (.I(CLK0_OUT) , .O(CLK_0));
//    BUFG BUFG_CLK90 (.I(CLK90_OUT) , .O(CLK_90));
//    BUFG BUFG_CLK180 (.I(CLK180_OUT) , .O(CLK_180));
//    BUFG BUFG_CLK270 (.I(CLK270_OUT) , .O(CLK_270));
//    BUFG BUFG_CLK2X (.I(CLK2X_OUT) , .O(CLK2X));
    assign CLKFB   = CLK0_OUT;
    assign CLK_0   = CLK0_OUT;
    assign CLK_90  = CLK90_OUT;
    assign CLK_180 = CLK180_OUT;
    assign CLK_270 = CLK270_OUT;
    assign CLK2X   = CLK2X_OUT;
    assign CLK = CLK_180;
    assign RESET = BSCAN_RESET | ~LOCKED;
`else
  assign CLKFX = CLKFX_OUT;
//    BUFG BUFG_CLKFX (.I(CLKFX_OUT) , .O(CLKFX));
//  BUFG BUFG_CLKFB (.I(CLK0_OUT) , .O(CLKFB));
    assign CLK = CLK_OUT;
   assign RESET = BSCAN_RESET | ~LOCKED | STATUS[2];
`endif
 
//`define	 SS_BIT    16     // PC0
//`define	 SCK_BIT   17     // PC1
//`define	 MISO_BIT  18     // PC2
//`define	 MOSI_BIT  20     // PC4
//`define	 RX_BIT    21     // PC5
//`define	 TX_BIT    22     // PC6
// PC3 (19): -> VS0
// PC7 (23): -> VS2
  `ifdef RTAVR_PORT_ESCALATION
	assign VS0 = DDR[19] ? PORT[19] : "H";
	assign PIN[19] = VS0;
	assign VS2 = DDR[23] ? PORT[23] : "H";
	assign PIN[23] = VS2;
    `ifdef IOR_HAVE_SPI
	assign PIN[`SS_BIT]   = SEL1;
	assign PIN[`SCK_BIT]  = DRCK1;
	assign PIN[`MOSI_BIT] = TDI;
	assign TDO1 = PORT[`MOSI_BIT];
    `endif
    `ifdef IOR_HAVE_USART
	assign PIN[`RX_BIT]   = TXD;
	assign RXD = DDR[`TX_BIT] ? PORT[`TX_BIT] : "H";
	assign PIN[`TX_BIT]   = RXD;
    `endif 
 `endif

        // CONFIG or LED
        assign INIT_B   = "Z"; // HOST
        assign M1       = "Z"; // HOST or LED
        assign M2       = "Z"; // HOST or LED
endmodule