module artemis_50a ( input CLK1 // MAIN CLOCK (33MHz) // GLK , input CLK2 // HOST CLOCK (8 MHz or 6/12/24/48 MHz) // GLK // SPI FLASH , output SF_C , input SF_DO , output SF_DIO , output SF_S // CONFIG or LED , inout INIT_B // HOST , inout M1 // HOST or LED , inout M2 // HOST or LED , output VS0 // LED , output VS2 // LED // USART (or SPI SLAVE) , input TXD // or MOSI // input only , output RXD // or MISO , input DTR // or SS , input RTS // or SCLK // GCLK // EXTERNAL (1) (EXT_1 = 3V3 , EXT_10 = GND ) , inout EXT_2 , inout EXT_3 , inout EXT_4 // DIFF_A_P , inout EXT_5 // DIFF_A_M , inout EXT_6 // DIFF_B_P , inout EXT_7 // DIFF_B_M , input EXT_8 // INPUT only , inout EXT_9 // GCLK // EXTERNAL (2) (EXT2_1 == 5V , EXT2_10 = GND) , inout EXT2_2 , inout EXT2_3 // LHCLK , inout EXT2_4 // LHCLK , inout EXT2_5 // LHCLK , inout EXT2_6 , inout EXT2_7 , input EXT2_8 , inout EXT2_9 ); // EXT card sample pin-assign // MicroSD USB PLL // #1 VCC // #2 DETECT D- PULLUP PLLCTRL // #3 DAT2 -- -- // #4 DAT3/CS D- INV // #5 -- D+ XIN // #6 CMD/DI D+ PULLUP -- // #7 DAT0/DO VBUS DETECT GND // #8 DAT1 VBUS SWITCH -- // #9 CLK -- XOUT // (PLLCLOCK) // #10 GND `include "rtavr_defs.v" BSCAN_SPARTAN3A bscan ( .RESET(BSCAN_RESET) , .SHIFT(BSCAN_SHIFT) , .CAPTURE(BSCAN_CAPTURE) , .UPDATE(BSCAN_UPDATE) , .TDI(TDI) , .TCK(TCK) , .TMS(TMS) // signals for USER1 , .DRCK1(DRCK1) , .SEL1(SEL1) , .TDO1(TDO1) // signals for USER2 , .DRCK2(DRCK2) , .SEL2(SEL2) , .TDO2(TDO2) ); `ifdef SUPPORT_ISP wire [15:0] ISP_ADDR; wire [7:0] ISP_STORE_DATA; wire [7:0] ISP_LOAD_DATA; isp ISP (.CLK(CLK) , .MOSI(TDI) , .SCK(DRCK2) , .CS(SEL2) , .MISO(TDO2) , .ISP_STORE(ISP_STORE) , .ISP_LOAD(ISP_LOAD) , .ISP_ADDR(ISP_ADDR) , .ISP_STORE_DATA(ISP_STORE_DATA) , .ISP_LOAD_DATA(ISP_LOAD_DATA) ); `endif wire RESET = BSCAN_RESET; wire CLK2X = CLK2; `ifdef RTAVR_PORT_ESCALATION wire [23:0] DDR; wire [23:0] PORT; wire [23:0] PIN; `endif rtavr RTAVR (.RESET(RESET), .CLK2X(CLK2X) , .CLK(CLK) `ifdef RTAVR_PORT_ESCALATION , .DDR(DDR[23:0]) , .PORT(PORT[23:0]) , .PIN(PIN[23:0]) `else `ifdef IOR_HAVE_PORTA , .PORTA(PORTA[7:0]) `endif `ifdef IOR_HAVE_PORTB , .PORTB(PORTB[7:0]) `endif `ifdef IOR_HAVE_PORTC , .PORTC(PORTC[7:0]) `endif `endif `ifdef SUPPORT_ISP , .ISP_STORE(ISP_STORE) , .ISP_LOAD(ISP_LOAD) , .ISP_ADDR(ISP_ADDR[15:0]) , .ISP_STORE_DATA(ISP_STORE_DATA[7:0]) , .ISP_LOAD_DATA(ISP_LOAD_DATA[7:0]) `endif ); //`define SS_BIT 16 // PC0 //`define SCK_BIT 17 // PC1 //`define MOSI_BIT 20 // PC4 //`define MISO_BIT 18 // PC2 //`define RX_BIT 21 // PC5 //`define TX_BIT 22 // PC6 `ifdef RTAVR_PORT_ESCALATION assign VS0 = DDR[19] ? PORT[19] : "H"; assign PIN[19] = VS0; assign VS2 = DDR[23] ? PORT[23] : "H"; assign PIN[23] = VS2; `ifdef IOR_HAVE_SPI assign PIN[`SS_BIT] = SEL1; assign PIN[`SCK_BIT] = DRCK1; assign PIN[`MOSI_BIT] = TDI; assign TDO1 = PORT[`MOSI_BIT]; `endif `ifdef IOR_HAVE_USART assign PIN[`RX_BIT] = TXD; assign RXD = DDR[`TX_BIT] ? PORT[`TX_BIT] : "H"; assign PIN[`TX_BIT] = RXD; `endif `endif // CONFIG or LED assign INIT_B = "H"; // HOST assign M1 = "H"; // HOST or LED assign M2 = "H"; // HOST or LED // EXTERNAL (1) assign EXT_2 = "H"; assign EXT_3 = "H"; assign EXT_4 = "H"; // DIFF_A_P assign EXT_5 = "H"; // DIFF_A_M assign EXT_6 = "H"; // DIFF_B_P assign EXT_7 = "H"; // DIFF_B_M // assign EXT_8 = "H"; // INPUT only assign EXT_9 = "H"; // GCLK // EXTERNAL (2) assign EXT2_2 = "H"; assign EXT2_3 = "H"; assign EXT2_4 = "H"; // assign EXT2_5 = "H"; // assign EXT2_6 = "H"; // assign EXT2_7 = "H"; // assign EXT2_8 = "H"; // endmodule